[mirror_edk2.git] / MdePkg / Include / Protocol / SmmCpu.h

/** @file\r
  EFI SMM CPU Protocol as defined in the PI 1.2 specification.\r
\r
  This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r
  save state areas. In some cases, difference processors provide the same information in the save state, \r
  but not in the same format. These so-called pseudo-registers provide this information in a standard \r
  format.  \r
\r
  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
#ifndef _SMM_CPU_H_\r
#define _SMM_CPU_H_\r
\r
#define EFI_SMM_CPU_PROTOCOL_GUID \\r
  { \\r
    0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \\r
  }\r
\r
///\r
/// Save State register index\r
///\r
typedef enum {\r
  ///\r
  /// x86/X64 standard registers\r
  ///\r
  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE       = 4,\r
  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE       = 5,\r
  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE       = 6,\r
  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT      = 7,\r
  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT      = 8,\r
  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT      = 9,\r
  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO       = 10,\r
  EFI_SMM_SAVE_STATE_REGISTER_ES            = 20,\r
  EFI_SMM_SAVE_STATE_REGISTER_CS            = 21,\r
  EFI_SMM_SAVE_STATE_REGISTER_SS            = 22,\r
  EFI_SMM_SAVE_STATE_REGISTER_DS            = 23,\r
  EFI_SMM_SAVE_STATE_REGISTER_FS            = 24,\r
  EFI_SMM_SAVE_STATE_REGISTER_GS            = 25,\r
  EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL      = 26,\r
  EFI_SMM_SAVE_STATE_REGISTER_TR_SEL        = 27,\r
  EFI_SMM_SAVE_STATE_REGISTER_DR7           = 28,\r
  EFI_SMM_SAVE_STATE_REGISTER_DR6           = 29,\r
  EFI_SMM_SAVE_STATE_REGISTER_R8            = 30,\r
  EFI_SMM_SAVE_STATE_REGISTER_R9            = 31,\r
  EFI_SMM_SAVE_STATE_REGISTER_R10           = 32,\r
  EFI_SMM_SAVE_STATE_REGISTER_R11           = 33,\r
  EFI_SMM_SAVE_STATE_REGISTER_R12           = 34,\r
  EFI_SMM_SAVE_STATE_REGISTER_R13           = 35,\r
  EFI_SMM_SAVE_STATE_REGISTER_R14           = 36,\r
  EFI_SMM_SAVE_STATE_REGISTER_R15           = 37,  \r
  EFI_SMM_SAVE_STATE_REGISTER_RAX           = 38,\r
  EFI_SMM_SAVE_STATE_REGISTER_RBX           = 39,\r
  EFI_SMM_SAVE_STATE_REGISTER_RCX           = 40,\r
  EFI_SMM_SAVE_STATE_REGISTER_RDX           = 41,\r
  EFI_SMM_SAVE_STATE_REGISTER_RSP           = 42,\r
  EFI_SMM_SAVE_STATE_REGISTER_RBP           = 43,\r
  EFI_SMM_SAVE_STATE_REGISTER_RSI           = 44,\r
  EFI_SMM_SAVE_STATE_REGISTER_RDI           = 45,\r
  EFI_SMM_SAVE_STATE_REGISTER_RIP           = 46,\r
  EFI_SMM_SAVE_STATE_REGISTER_RFLAGS        = 51,\r
  EFI_SMM_SAVE_STATE_REGISTER_CR0           = 52,\r
  EFI_SMM_SAVE_STATE_REGISTER_CR3           = 53,\r
  EFI_SMM_SAVE_STATE_REGISTER_CR4           = 54,\r
  EFI_SMM_SAVE_STATE_REGISTER_FCW           = 256,\r
  EFI_SMM_SAVE_STATE_REGISTER_FSW           = 257,\r
  EFI_SMM_SAVE_STATE_REGISTER_FTW           = 258,  \r
  EFI_SMM_SAVE_STATE_REGISTER_OPCODE        = 259,\r
  EFI_SMM_SAVE_STATE_REGISTER_FP_EIP        = 260,\r
  EFI_SMM_SAVE_STATE_REGISTER_FP_CS         = 261,\r
  EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET    = 262,\r
  EFI_SMM_SAVE_STATE_REGISTER_FP_DS         = 263,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM0           = 264,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM1           = 265,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM2           = 266,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM3           = 267,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM4           = 268,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM5           = 269,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM6           = 270,\r
  EFI_SMM_SAVE_STATE_REGISTER_MM7           = 271,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM0          = 272,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM1          = 273,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM2          = 274,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM3          = 275,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM4          = 276,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM5          = 277,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM6          = 278,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM7          = 279,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM8          = 280,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM9          = 281,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM10         = 282,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM11         = 283,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM12         = 284,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM13         = 285,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM14         = 286,\r
  EFI_SMM_SAVE_STATE_REGISTER_XMM15         = 287,  \r
  ///\r
  /// Pseudo-Registers\r
  ///\r
  EFI_SMM_SAVE_STATE_REGISTER_IO            = 512,\r
  EFI_SMM_SAVE_STATE_REGISTER_LMA           = 513\r
} EFI_SMM_SAVE_STATE_REGISTER;  \r
\r
///\r
/// The EFI_SMM_SAVE_STATE_REGISTER_LMA pseudo-register values\r
/// If the processor acts in 32-bit mode at the time the SMI occurred, the pseudo register value \r
/// EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise, \r
/// EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.\r
///\r
#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT  32\r
#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT  64\r
\r
///\r
/// Size width of I/O instruction\r
///\r
typedef enum {\r
  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8      = 0,\r
  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16     = 1,\r
  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32     = 2,\r
  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64     = 3\r
} EFI_SMM_SAVE_STATE_IO_WIDTH;\r
\r
///\r
/// Types of I/O instruction\r
///\r
typedef enum {\r
  EFI_SMM_SAVE_STATE_IO_TYPE_INPUT       = 1,\r
  EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT      = 2,\r
  EFI_SMM_SAVE_STATE_IO_TYPE_STRING      = 4,\r
  EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX  = 8\r
} EFI_SMM_SAVE_STATE_IO_TYPE;\r
\r
///\r
/// Structure of the data which is returned when ReadSaveState() is called with \r
/// EFI_SMM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will \r
/// return EFI_NOT_FOUND.\r
///\r
/// This structure describes the I/O operation which was in process when the SMI was generated.\r
///\r
typedef struct _EFI_SMM_SAVE_STATE_IO_INFO {\r
  ///\r
  /// For input instruction (IN, INS), this is data read before the SMI occurred. For output \r
  /// instructions (OUT, OUTS) this is data that was written before the SMI occurred. The \r
  /// width of the data is specified by IoWidth.\r
  ///\r
  /// Note: inconsistency with PI 1.2 spec here. wait for spec update.\r
  ///\r
  UINTN                         IoData;\r
  ///\r
  /// The I/O port that was being accessed when the SMI was triggered.\r
  ///\r
  UINT16                        IoPort;\r
  ///\r
  /// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.\r
  ///\r
  EFI_SMM_SAVE_STATE_IO_WIDTH   IoWidth;\r
  ///\r
  /// Defines type of I/O instruction.\r
  ///\r
  EFI_SMM_SAVE_STATE_IO_TYPE    IoType;\r
} EFI_SMM_SAVE_STATE_IO_INFO;\r
  \r
typedef struct _EFI_SMM_CPU_PROTOCOL  EFI_SMM_CPU_PROTOCOL;\r
\r
/**\r
  Read data from the CPU save state.\r
\r
  This function is used to read the specified number of bytes of the specified register from the CPU \r
  save state of the specified CPU and place the value into the buffer. If the CPU does not support the\r
  specified register Register, then EFI_NOT_FOUND  should be returned. If the CPU does not \r
  support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r
\r
  @param[in]  This               The EFI_SMM_CPU_PROTOCOL instance.\r
  @param[in]  Width              The number of bytes to read from the CPU save state.\r
  @param[in]  Register           Specifies the CPU register to read form the save state.\r
  @param[in]  CpuIndex           Specifies the zero-based index of the CPU save state.\r
  @param[out] Buffer             Upon return, this holds the CPU register value read from the save state.\r
    \r
  @retval EFI_SUCCESS            The register was read from Save State.\r
  @retval EFI_NOT_FOUND          The register is not defined for the Save State of Processor.\r
  @retval EFI_INVALID_PARAMETER  Input parameters are not valid, for example, Processor No or register width \r
                                 is not correct.This or Buffer is NULL.\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SMM_READ_SAVE_STATE)(\r
  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
  IN UINTN                        Width,\r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        CpuIndex,\r
  OUT VOID                        *Buffer\r
  );\r
\r
\r
/**\r
  Write data to the CPU save state.\r
\r
  This function is used to write the specified number of bytes of the specified register to the CPU save \r
  state of the specified CPU and place the value into the buffer. If the CPU does not support the \r
  specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not \r
  support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r
\r
  @param[in]  This               The EFI_SMM_CPU_PROTOCOL instance.\r
  @param[in]  Width              The number of bytes to write to the CPU save state.\r
  @param[in]  Register           Specifies the CPU register to write to the save state.\r
  @param[in]  CpuIndex           Specifies the zero-based index of the CPU save state.\r
  @param[in]  Buffer             Upon entry, this holds the new CPU register value.\r
  \r
  @retval EFI_SUCCESS            The register was written to Save State.\r
  @retval EFI_NOT_FOUND          The register is not defined for the Save State of Processor.\r
  @retval EFI_INVALID_PARAMETER  Input parameters are not valid. For example: \r
                                 ProcessorIndex or Width is not correct.\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SMM_WRITE_SAVE_STATE)(\r
  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
  IN UINTN                        Width, \r
  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
  IN UINTN                        CpuIndex,\r
  IN CONST VOID                   *Buffer\r
  );\r
\r
///\r
/// EFI SMM CPU Protocol provides access to CPU-related information while in SMM.\r
///\r
/// This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r
/// save state areas. In some cases, difference processors provide the same information in the save state, \r
/// but not in the same format. These so-called pseudo-registers provide this information in a standard \r
/// format.  \r
///\r
struct _EFI_SMM_CPU_PROTOCOL {\r
  EFI_SMM_READ_SAVE_STATE   ReadSaveState;\r
  EFI_SMM_WRITE_SAVE_STATE  WriteSaveState;\r
};\r
\r
extern EFI_GUID gEfiSmmCpuProtocolGuid;\r
\r
#endif\r
\r
Commit	Line	Data
d0778dd7	1	/** @file\r
	2	EFI SMM CPU Protocol as defined in the PI 1.2 specification.\r
	3	\r
	4	This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r
	5	save state areas. In some cases, difference processors provide the same information in the save state, \r
	6	but not in the same format. These so-called pseudo-registers provide this information in a standard \r
	7	format. \r
	8	\r
9df063a0 HT	9	Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>\r
9df063a0 HT	10	This program and the accompanying materials \r
d0778dd7	11	are licensed and made available under the terms and conditions of the BSD License \r
	12	which accompanies this distribution. The full text of the license may be found at \r
	13	http://opensource.org/licenses/bsd-license.php \r
	14	\r
	15	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	16	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	17	\r
	18	**/\r
	19	\r
	20	#ifndef _SMM_CPU_H_\r
	21	#define _SMM_CPU_H_\r
	22	\r
d0778dd7	23	#define EFI_SMM_CPU_PROTOCOL_GUID \\r
	24	{ \\r
	25	0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \\r
	26	}\r
	27	\r
	28	///\r
	29	/// Save State register index\r
	30	///\r
	31	typedef enum {\r
	32	///\r
	33	/// x86/X64 standard registers\r
	34	///\r
	35	EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4,\r
	36	EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5,\r
	37	EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6,\r
	38	EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7,\r
	39	EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8,\r
	40	EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9,\r
	41	EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10,\r
	42	EFI_SMM_SAVE_STATE_REGISTER_ES = 20,\r
	43	EFI_SMM_SAVE_STATE_REGISTER_CS = 21,\r
	44	EFI_SMM_SAVE_STATE_REGISTER_SS = 22,\r
	45	EFI_SMM_SAVE_STATE_REGISTER_DS = 23,\r
	46	EFI_SMM_SAVE_STATE_REGISTER_FS = 24,\r
	47	EFI_SMM_SAVE_STATE_REGISTER_GS = 25,\r
	48	EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26,\r
	49	EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27,\r
	50	EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28,\r
	51	EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29,\r
	52	EFI_SMM_SAVE_STATE_REGISTER_R8 = 30,\r
	53	EFI_SMM_SAVE_STATE_REGISTER_R9 = 31,\r
	54	EFI_SMM_SAVE_STATE_REGISTER_R10 = 32,\r
	55	EFI_SMM_SAVE_STATE_REGISTER_R11 = 33,\r
	56	EFI_SMM_SAVE_STATE_REGISTER_R12 = 34,\r
	57	EFI_SMM_SAVE_STATE_REGISTER_R13 = 35,\r
	58	EFI_SMM_SAVE_STATE_REGISTER_R14 = 36,\r
	59	EFI_SMM_SAVE_STATE_REGISTER_R15 = 37, \r
	60	EFI_SMM_SAVE_STATE_REGISTER_RAX = 38,\r
	61	EFI_SMM_SAVE_STATE_REGISTER_RBX = 39,\r
	62	EFI_SMM_SAVE_STATE_REGISTER_RCX = 40,\r
	63	EFI_SMM_SAVE_STATE_REGISTER_RDX = 41,\r
	64	EFI_SMM_SAVE_STATE_REGISTER_RSP = 42,\r
	65	EFI_SMM_SAVE_STATE_REGISTER_RBP = 43,\r
	66	EFI_SMM_SAVE_STATE_REGISTER_RSI = 44,\r
	67	EFI_SMM_SAVE_STATE_REGISTER_RDI = 45,\r
	68	EFI_SMM_SAVE_STATE_REGISTER_RIP = 46,\r
	69	EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51,\r
	70	EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52,\r
	71	EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53,\r
	72	EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54,\r
	73	EFI_SMM_SAVE_STATE_REGISTER_FCW = 256,\r
	74	EFI_SMM_SAVE_STATE_REGISTER_FSW = 257,\r
	75	EFI_SMM_SAVE_STATE_REGISTER_FTW = 258, \r
	76	EFI_SMM_SAVE_STATE_REGISTER_OPCODE = 259,\r
	77	EFI_SMM_SAVE_STATE_REGISTER_FP_EIP = 260,\r
	78	EFI_SMM_SAVE_STATE_REGISTER_FP_CS = 261,\r
	79	EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET = 262,\r
	80	EFI_SMM_SAVE_STATE_REGISTER_FP_DS = 263,\r
	81	EFI_SMM_SAVE_STATE_REGISTER_MM0 = 264,\r
	82	EFI_SMM_SAVE_STATE_REGISTER_MM1 = 265,\r
	83	EFI_SMM_SAVE_STATE_REGISTER_MM2 = 266,\r
	84	EFI_SMM_SAVE_STATE_REGISTER_MM3 = 267,\r
	85	EFI_SMM_SAVE_STATE_REGISTER_MM4 = 268,\r
	86	EFI_SMM_SAVE_STATE_REGISTER_MM5 = 269,\r
87	EFI_SMM_SAVE_STATE_REGISTER_MM6 = 270,\r
88	EFI_SMM_SAVE_STATE_REGISTER_MM7 = 271,\r
89	EFI_SMM_SAVE_STATE_REGISTER_XMM0 = 272,\r
90	EFI_SMM_SAVE_STATE_REGISTER_XMM1 = 273,\r
91	EFI_SMM_SAVE_STATE_REGISTER_XMM2 = 274,\r
92	EFI_SMM_SAVE_STATE_REGISTER_XMM3 = 275,\r
93	EFI_SMM_SAVE_STATE_REGISTER_XMM4 = 276,\r
94	EFI_SMM_SAVE_STATE_REGISTER_XMM5 = 277,\r
95	EFI_SMM_SAVE_STATE_REGISTER_XMM6 = 278,\r
96	EFI_SMM_SAVE_STATE_REGISTER_XMM7 = 279,\r
97	EFI_SMM_SAVE_STATE_REGISTER_XMM8 = 280,\r
98	EFI_SMM_SAVE_STATE_REGISTER_XMM9 = 281,\r
99	EFI_SMM_SAVE_STATE_REGISTER_XMM10 = 282,\r
100	EFI_SMM_SAVE_STATE_REGISTER_XMM11 = 283,\r
101	EFI_SMM_SAVE_STATE_REGISTER_XMM12 = 284,\r
102	EFI_SMM_SAVE_STATE_REGISTER_XMM13 = 285,\r
103	EFI_SMM_SAVE_STATE_REGISTER_XMM14 = 286,\r
104	EFI_SMM_SAVE_STATE_REGISTER_XMM15 = 287, \r
105	///\r
106	/// Pseudo-Registers\r
107	///\r
108	EFI_SMM_SAVE_STATE_REGISTER_IO = 512,\r
109	EFI_SMM_SAVE_STATE_REGISTER_LMA = 513\r
110	} EFI_SMM_SAVE_STATE_REGISTER; \r
111	\r
112	///\r
113	/// The EFI_SMM_SAVE_STATE_REGISTER_LMA pseudo-register values\r
114	/// If the processor acts in 32-bit mode at the time the SMI occurred, the pseudo register value \r
115	/// EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise, \r
116	/// EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.\r
117	///\r
118	#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT 32\r
119	#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT 64\r
120	\r
121	///\r
122	/// Size width of I/O instruction\r
123	///\r
124	typedef enum {\r
125	EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 = 0,\r
126	EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 = 1,\r
127	EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 = 2,\r
128	EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 = 3\r
129	} EFI_SMM_SAVE_STATE_IO_WIDTH;\r
130	\r
131	///\r
132	/// Types of I/O instruction\r
133	///\r
134	typedef enum {\r
135	EFI_SMM_SAVE_STATE_IO_TYPE_INPUT = 1,\r
136	EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT = 2,\r
137	EFI_SMM_SAVE_STATE_IO_TYPE_STRING = 4,\r
138	EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8\r
139	} EFI_SMM_SAVE_STATE_IO_TYPE;\r
140	\r
141	///\r
142	/// Structure of the data which is returned when ReadSaveState() is called with \r
143	/// EFI_SMM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will \r
144	/// return EFI_NOT_FOUND.\r
145	///\r
146	/// This structure describes the I/O operation which was in process when the SMI was generated.\r
147	///\r
148	typedef struct _EFI_SMM_SAVE_STATE_IO_INFO {\r
149	///\r
150	/// For input instruction (IN, INS), this is data read before the SMI occurred. For output \r
151	/// instructions (OUT, OUTS) this is data that was written before the SMI occurred. The \r
152	/// width of the data is specified by IoWidth.\r
153	///\r
154	/// Note: inconsistency with PI 1.2 spec here. wait for spec update.\r
155	///\r
156	UINTN IoData;\r
157	///\r
158	/// The I/O port that was being accessed when the SMI was triggered.\r
159	///\r
160	UINT16 IoPort;\r
161	///\r
162	/// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.\r
163	///\r
164	EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;\r
165	///\r
166	/// Defines type of I/O instruction.\r
167	///\r
168	EFI_SMM_SAVE_STATE_IO_TYPE IoType;\r
169	} EFI_SMM_SAVE_STATE_IO_INFO;\r
170	\r
171	typedef struct _EFI_SMM_CPU_PROTOCOL EFI_SMM_CPU_PROTOCOL;\r
172	\r
173	/**\r
174	Read data from the CPU save state.\r
175	\r
176	This function is used to read the specified number of bytes of the specified register from the CPU \r
177	save state of the specified CPU and place the value into the buffer. If the CPU does not support the\r
178	specified register Register, then EFI_NOT_FOUND should be returned. If the CPU does not \r
179	support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r
180	\r
181	@param[in] This The EFI_SMM_CPU_PROTOCOL instance.\r
182	@param[in] Width The number of bytes to read from the CPU save state.\r
183	@param[in] Register Specifies the CPU register to read form the save state.\r
184	@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
185	@param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r
186	\r
187	@retval EFI_SUCCESS The register was read from Save State.\r
188	@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
189	@retval EFI_INVALID_PARAMETER Input parameters are not valid, for example, Processor No or register width \r
190	is not correct.This or Buffer is NULL.\r
191	**/\r
192	typedef\r
193	EFI_STATUS\r
194	(EFIAPI *EFI_SMM_READ_SAVE_STATE)(\r
195	IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
196	IN UINTN Width,\r
197	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
198	IN UINTN CpuIndex,\r
199	OUT VOID *Buffer\r
200	);\r
201	\r
202	\r
203	/**\r
204	Write data to the CPU save state.\r
205	\r
206	This function is used to write the specified number of bytes of the specified register to the CPU save \r
207	state of the specified CPU and place the value into the buffer. If the CPU does not support the \r
208	specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not \r
209	support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r
210	\r
211	@param[in] This The EFI_SMM_CPU_PROTOCOL instance.\r
212	@param[in] Width The number of bytes to write to the CPU save state.\r
213	@param[in] Register Specifies the CPU register to write to the save state.\r
214	@param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r
215	@param[in] Buffer Upon entry, this holds the new CPU register value.\r
216	\r
217	@retval EFI_SUCCESS The register was written to Save State.\r
218	@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r
219	@retval EFI_INVALID_PARAMETER Input parameters are not valid. For example: \r
220	ProcessorIndex or Width is not correct.\r
221	**/\r
222	typedef\r
223	EFI_STATUS\r
224	(EFIAPI *EFI_SMM_WRITE_SAVE_STATE)(\r
225	IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
226	IN UINTN Width, \r
227	IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
228	IN UINTN CpuIndex,\r
229	IN CONST VOID *Buffer\r
230	);\r
231	\r
232	///\r
233	/// EFI SMM CPU Protocol provides access to CPU-related information while in SMM.\r
234	///\r
235	/// This protocol allows SMM drivers to access architecture-standard registers from any of the CPU \r
236	/// save state areas. In some cases, difference processors provide the same information in the save state, \r
237	/// but not in the same format. These so-called pseudo-registers provide this information in a standard \r
238	/// format. \r
239	///\r
240	struct _EFI_SMM_CPU_PROTOCOL {\r
241	EFI_SMM_READ_SAVE_STATE ReadSaveState;\r
242	EFI_SMM_WRITE_SAVE_STATE WriteSaveState;\r
243	};\r
244	\r
245	extern EFI_GUID gEfiSmmCpuProtocolGuid;\r
246	\r
247	#endif\r
248	\r