[mirror_edk2.git] / MdePkg / Include / Protocol / SpiHc.h

/** @file\r
  This file defines the SPI Host Controller Protocol.\r
\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Revision Reference:\r
    This Protocol was introduced in UEFI PI Specification 1.6.\r
\r
**/\r
\r
#ifndef __SPI_HC_PROTOCOL_H__\r
#define __SPI_HC_PROTOCOL_H__\r
\r
#include <Protocol/SpiConfiguration.h>\r
#include <Protocol/SpiIo.h>\r
\r
///\r
/// Global ID for the SPI Host Controller Protocol\r
///\r
#define EFI_SPI_HOST_GUID  \\r
  { 0xc74e5db2, 0xfa96, 0x4ae2,   \\r
    { 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }}\r
\r
///\r
/// EDK2-style name\r
///\r
#define EFI_SPI_HC_PROTOCOL_GUID  EFI_SPI_HOST_GUID\r
\r
typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL;\r
\r
/**\r
  Assert or deassert the SPI chip select.\r
\r
  This routine is called at TPL_NOTIFY.\r
  Update the value of the chip select line for a SPI peripheral. The SPI bus\r
  layer calls this routine either in the board layer or in the SPI controller\r
  to manipulate the chip select pin at the start and end of a SPI transaction.\r
\r
  @param[in] This           Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
  @param[in] SpiPeripheral  The address of an EFI_SPI_PERIPHERAL data structure\r
                            describing the SPI peripheral whose chip select pin\r
                            is to be manipulated. The routine may access the\r
                            ChipSelectParameter field to gain sufficient\r
                            context to complete the operati on.\r
  @param[in] PinValue       The value to be applied to the chip select line of\r
                            the SPI peripheral.\r
\r
  @retval EFI_SUCCESS            The chip select was set as requested\r
  @retval EFI_NOT_READY          Support for the chip select is not properly\r
                                 initialized\r
  @retval EFI_INVALID_PARAMETER  The ChipSeLect value or its contents are\r
                                 invalid\r
\r
**/\r
typedef EFI_STATUS\r
(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (\r
  IN CONST EFI_SPI_HC_PROTOCOL  *This,\r
  IN CONST EFI_SPI_PERIPHERAL   *SpiPeripheral,\r
  IN BOOLEAN                    PinValue\r
  );\r
\r
/**\r
  Set up the clock generator to produce the correct clock frequency, phase and\r
  polarity for a SPI chip.\r
\r
  This routine is called at TPL_NOTIFY.\r
  This routine updates the clock generator to generate the correct frequency\r
  and polarity for the SPI clock.\r
\r
  @param[in] This           Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
  @param[in] SpiPeripheral  Pointer to a EFI_SPI_PERIPHERAL data structure from\r
                            which the routine can access the ClockParameter,\r
                            ClockPhase and ClockPolarity fields. The routine\r
                            also has access to the names for the SPI bus and\r
                            chip which can be used during debugging.\r
  @param[in] ClockHz        Pointer to the requested clock frequency. The SPI\r
                            host controller will choose a supported clock\r
                            frequency which is less then or equal to this\r
                            value. Specify zero to turn the clock generator\r
                            off. The actual clock frequency supported by the\r
                            SPI host controller will be returned.\r
\r
  @retval EFI_SUCCESS      The clock was set up successfully\r
  @retval EFI_UNSUPPORTED  The SPI controller was not able to support the\r
                           frequency requested by ClockHz\r
\r
**/\r
typedef EFI_STATUS\r
(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (\r
  IN CONST EFI_SPI_HC_PROTOCOL  *This,\r
  IN CONST EFI_SPI_PERIPHERAL   *SpiPeripheral,\r
  IN UINT32                      *ClockHz\r
  );\r
\r
/**\r
  Perform the SPI transaction on the SPI peripheral using the SPI host\r
  controller.\r
\r
  This routine is called at TPL_NOTIFY.\r
  This routine synchronously returns EFI_SUCCESS indicating that the\r
  asynchronous SPI transaction was started. The routine then waits for\r
  completion of the SPI transaction prior to returning the final transaction\r
  status.\r
\r
  @param[in] This            Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
  @param[in] BusTransaction  Pointer to a EFI_SPI_BUS_ TRANSACTION containing\r
                             the description of the SPI transaction to perform.\r
\r
  @retval EFI_SUCCESS          The transaction completed successfully\r
  @retval EFI_BAD_BUFFER_SIZE  The BusTransaction->WriteBytes value is invalid,\r
                               or the BusTransaction->ReadinBytes value is\r
                               invalid\r
  @retval EFI_UNSUPPORTED      The BusTransaction-> Transaction Type is\r
                               unsupported\r
\r
**/\r
typedef EFI_STATUS\r
(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (\r
  IN CONST EFI_SPI_HC_PROTOCOL  *This,\r
  IN EFI_SPI_BUS_TRANSACTION    *BusTransaction\r
  );\r
\r
///\r
/// Support a SPI data transaction between the SPI controller and a SPI chip.\r
///\r
struct _EFI_SPI_HC_PROTOCOL {\r
  ///\r
  /// Host control attributes, may have zero or more of the following set:\r
  /// * HC_SUPPORTS_WRITE_ONLY_OPERATIONS\r
  /// * HC_SUPPORTS_READ_ONLY_OPERATIONS\r
  /// * HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS\r
  /// * HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS\r
  ///   - The SPI host controller requires the transmit frame to be in most\r
  ///     significant bits instead of least significant bits.The host driver\r
  ///     will adjust the frames if necessary.\r
  /// * HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS\r
  ///   - The SPI host controller places the receive frame to be in most\r
  ///     significant bits instead of least significant bits.The host driver\r
  ///     will adjust the frames to be in the least significant bits if\r
  ///     necessary.\r
  /// * HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH\r
  ///   - The SPI controller supports a 2 - bit data bus\r
  /// * HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH\r
  ///   - The SPI controller supports a 4 - bit data bus\r
  /// * HC_TRANSFER_SIZE_INCLUDES_OPCODE\r
  ///   - Transfer size includes the opcode byte\r
  /// * HC_TRANSFER_SIZE_INCLUDES_ADDRESS\r
  ///   - Transfer size includes the 3 address bytes\r
  /// The SPI host controller must support full - duplex (receive while\r
  /// sending) operation.The SPI host controller must support a 1 - bit bus\r
  /// width.\r
  ///\r
  UINT32                          Attributes;\r
\r
  ///\r
  /// Mask of frame sizes which the SPI host controller supports. Frame size of\r
  /// N-bits is supported when bit N-1 is set. The host controller must support\r
  /// a frame size of 8-bits.\r
  ///\r
  UINT32                          FrameSizeSupportMask;\r
\r
  ///\r
  /// Maximum transfer size in bytes: 1 - Oxffffffff\r
  ///\r
  UINT32                          MaximumTransferBytes;\r
\r
  ///\r
  /// Assert or deassert the SPI chip select.\r
  ///\r
  EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;\r
\r
  ///\r
  /// Set up the clock generator to produce the correct clock frequency, phase\r
  /// and polarity for a SPI chip.\r
  ///\r
  EFI_SPI_HC_PROTOCOL_CLOCK       Clock;\r
\r
  ///\r
  /// Perform the SPI transaction on the SPI peripheral using the SPI host\r
  /// controller.\r
  ///\r
  EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;\r
};\r
\r
extern EFI_GUID gEfiSpiHcProtocolGuid;\r
\r
#endif // __SPI_HC_PROTOCOL_H__\r
Commit	Line	Data
db04b706 MH	1	/** @file\r
	2	This file defines the SPI Host Controller Protocol.\r
	3	\r
	4	Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
9344f092	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
db04b706 MH	6	\r
	7	@par Revision Reference:\r
	8	This Protocol was introduced in UEFI PI Specification 1.6.\r
	9	\r
	10	**/\r
	11	\r
	12	#ifndef __SPI_HC_PROTOCOL_H__\r
	13	#define __SPI_HC_PROTOCOL_H__\r
	14	\r
	15	#include <Protocol/SpiConfiguration.h>\r
	16	#include <Protocol/SpiIo.h>\r
	17	\r
	18	///\r
	19	/// Global ID for the SPI Host Controller Protocol\r
	20	///\r
	21	#define EFI_SPI_HOST_GUID \\r
	22	{ 0xc74e5db2, 0xfa96, 0x4ae2, \\r
	23	{ 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }}\r
	24	\r
	25	///\r
	26	/// EDK2-style name\r
	27	///\r
	28	#define EFI_SPI_HC_PROTOCOL_GUID EFI_SPI_HOST_GUID\r
	29	\r
	30	typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL;\r
	31	\r
	32	/**\r
	33	Assert or deassert the SPI chip select.\r
	34	\r
	35	This routine is called at TPL_NOTIFY.\r
	36	Update the value of the chip select line for a SPI peripheral. The SPI bus\r
	37	layer calls this routine either in the board layer or in the SPI controller\r
	38	to manipulate the chip select pin at the start and end of a SPI transaction.\r
	39	\r
	40	@param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
	41	@param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure\r
	42	describing the SPI peripheral whose chip select pin\r
	43	is to be manipulated. The routine may access the\r
	44	ChipSelectParameter field to gain sufficient\r
	45	context to complete the operati on.\r
	46	@param[in] PinValue The value to be applied to the chip select line of\r
	47	the SPI peripheral.\r
	48	\r
	49	@retval EFI_SUCCESS The chip select was set as requested\r
	50	@retval EFI_NOT_READY Support for the chip select is not properly\r
	51	initialized\r
	52	@retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are\r
	53	invalid\r
	54	\r
	55	**/\r
	56	typedef EFI_STATUS\r
	57	(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (\r
	58	IN CONST EFI_SPI_HC_PROTOCOL *This,\r
	59	IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
	60	IN BOOLEAN PinValue\r
	61	);\r
	62	\r
	63	/**\r
	64	Set up the clock generator to produce the correct clock frequency, phase and\r
	65	polarity for a SPI chip.\r
	66	\r
	67	This routine is called at TPL_NOTIFY.\r
	68	This routine updates the clock generator to generate the correct frequency\r
	69	and polarity for the SPI clock.\r
70	\r
71	@param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
72	@param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from\r
73	which the routine can access the ClockParameter,\r
74	ClockPhase and ClockPolarity fields. The routine\r
75	also has access to the names for the SPI bus and\r
76	chip which can be used during debugging.\r
77	@param[in] ClockHz Pointer to the requested clock frequency. The SPI\r
78	host controller will choose a supported clock\r
79	frequency which is less then or equal to this\r
80	value. Specify zero to turn the clock generator\r
81	off. The actual clock frequency supported by the\r
82	SPI host controller will be returned.\r
83	\r
84	@retval EFI_SUCCESS The clock was set up successfully\r
85	@retval EFI_UNSUPPORTED The SPI controller was not able to support the\r
86	frequency requested by ClockHz\r
87	\r
88	**/\r
89	typedef EFI_STATUS\r
90	(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (\r
91	IN CONST EFI_SPI_HC_PROTOCOL *This,\r
92	IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
93	IN UINT32 *ClockHz\r
94	);\r
95	\r
96	/**\r
97	Perform the SPI transaction on the SPI peripheral using the SPI host\r
98	controller.\r
99	\r
100	This routine is called at TPL_NOTIFY.\r
101	This routine synchronously returns EFI_SUCCESS indicating that the\r
102	asynchronous SPI transaction was started. The routine then waits for\r
103	completion of the SPI transaction prior to returning the final transaction\r
104	status.\r
105	\r
106	@param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure.\r
107	@param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing\r
108	the description of the SPI transaction to perform.\r
109	\r
110	@retval EFI_SUCCESS The transaction completed successfully\r
111	@retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid,\r
112	or the BusTransaction->ReadinBytes value is\r
113	invalid\r
114	@retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is\r
115	unsupported\r
116	\r
117	**/\r
118	typedef EFI_STATUS\r
119	(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (\r
120	IN CONST EFI_SPI_HC_PROTOCOL *This,\r
121	IN EFI_SPI_BUS_TRANSACTION *BusTransaction\r
122	);\r
123	\r
124	///\r
125	/// Support a SPI data transaction between the SPI controller and a SPI chip.\r
126	///\r
127	struct _EFI_SPI_HC_PROTOCOL {\r
128	///\r
129	/// Host control attributes, may have zero or more of the following set:\r
130	/// * HC_SUPPORTS_WRITE_ONLY_OPERATIONS\r
131	/// * HC_SUPPORTS_READ_ONLY_OPERATIONS\r
132	/// * HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS\r
133	/// * HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS\r
134	/// - The SPI host controller requires the transmit frame to be in most\r
135	/// significant bits instead of least significant bits.The host driver\r
136	/// will adjust the frames if necessary.\r
137	/// * HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS\r
138	/// - The SPI host controller places the receive frame to be in most\r
139	/// significant bits instead of least significant bits.The host driver\r
140	/// will adjust the frames to be in the least significant bits if\r
141	/// necessary.\r
142	/// * HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH\r
143	/// - The SPI controller supports a 2 - bit data bus\r
144	/// * HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH\r
145	/// - The SPI controller supports a 4 - bit data bus\r
146	/// * HC_TRANSFER_SIZE_INCLUDES_OPCODE\r
147	/// - Transfer size includes the opcode byte\r
148	/// * HC_TRANSFER_SIZE_INCLUDES_ADDRESS\r
149	/// - Transfer size includes the 3 address bytes\r
150	/// The SPI host controller must support full - duplex (receive while\r
151	/// sending) operation.The SPI host controller must support a 1 - bit bus\r
152	/// width.\r
153	///\r
154	UINT32 Attributes;\r
155	\r
156	///\r
157	/// Mask of frame sizes which the SPI host controller supports. Frame size of\r
158	/// N-bits is supported when bit N-1 is set. The host controller must support\r
159	/// a frame size of 8-bits.\r
160	///\r
161	UINT32 FrameSizeSupportMask;\r
162	\r
163	///\r
164	/// Maximum transfer size in bytes: 1 - Oxffffffff\r
165	///\r
166	UINT32 MaximumTransferBytes;\r
167	\r
168	///\r
169	/// Assert or deassert the SPI chip select.\r
170	///\r
171	EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;\r
172	\r
173	///\r
174	/// Set up the clock generator to produce the correct clock frequency, phase\r
175	/// and polarity for a SPI chip.\r
176	///\r
177	EFI_SPI_HC_PROTOCOL_CLOCK Clock;\r
178	\r
179	///\r
180	/// Perform the SPI transaction on the SPI peripheral using the SPI host\r
181	/// controller.\r
182	///\r
183	EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;\r
184	};\r
185	\r
186	extern EFI_GUID gEfiSpiHcProtocolGuid;\r
187	\r
188	#endif // __SPI_HC_PROTOCOL_H__\r