Initial import.
[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / Ipf / Cpu.s
CommitLineData
878ddf1f 1//++\r
2// Copyright (c) 2006, Intel Corporation \r
3// All rights reserved. This program and the accompanying materials \r
4// are licensed and made available under the terms and conditions of the BSD License \r
5// which accompanies this distribution. The full text of the license may be found at \r
6// http://opensource.org/licenses/bsd-license.php \r
7// \r
8// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
9// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
10// \r
11// Module Name:\r
12//\r
13// Cpu.s \r
14//\r
15// Abstract:\r
16//\r
17//\r
18// Revision History:\r
19//\r
20//--\r
21\r
22 .file "Cpu.s"\r
23 .radix D\r
24 .section .text, "ax", "progbits"\r
25 .align 32\r
26 .section .pdata, "a", "progbits"\r
27 .align 4\r
28 .section .xdata, "a", "progbits"\r
29 .align 8\r
30 .section .data, "wa", "progbits"\r
31 .align 16\r
32 .section .rdata, "a", "progbits"\r
33 .align 16\r
34 .section .bss, "wa", "nobits"\r
35 .align 16\r
36 .section .tls$, "was", "progbits"\r
37 .align 16\r
38 .section .sdata, "was", "progbits"\r
39 .align 16\r
40 .section .sbss, "was", "nobits"\r
41 .align 16\r
42 .section .srdata, "as", "progbits"\r
43 .align 16\r
44 .section .rdata, "a", "progbits"\r
45 .align 16\r
46 .section .rtcode, "ax", "progbits"\r
47 .align 32\r
48 .type InvalidateInstructionCacheRange# ,@function \r
49 .global InvalidateInstructionCacheRange#\r
50// Function compile flags: /Ogsy\r
51 .section .rtcode\r
52\r
53// Begin code for function: InvalidateInstructionCacheRange:\r
54 .proc InvalidateInstructionCacheRange#\r
55 .align 32\r
56InvalidateInstructionCacheRange: \r
57// File e:\tmp\pioflush.c\r
58 { .mii //R-Addr: 0X00 \r
59 alloc r3=2, 0, 0, 0 //11, 00000002H\r
60 cmp4.leu p0,p6=32, r33;; //15, 00000020H\r
61 (p6) mov r33=32;; //16, 00000020H\r
62 }\r
63 { .mii //R-Addr: 0X010 \r
64 nop.m 0\r
65 zxt4 r29=r33;; //21\r
66 dep.z r30=r29, 0, 5;; //21, 00000005H\r
67 }\r
68 { .mii //R-Addr: 0X020 \r
69 cmp4.eq p0,p7=r0, r30 //21\r
70 shr.u r28=r29, 5;; //19, 00000005H\r
71 (p7) adds r28=1, r28;; //22, 00000001H\r
72 }\r
73 { .mii //R-Addr: 0X030 \r
74 nop.m 0\r
75 shl r27=r28, 5;; //25, 00000005H\r
76 zxt4 r26=r27;; //25\r
77 }\r
78 { .mfb //R-Addr: 0X040 \r
79 add r31=r26, r32 //25\r
80 nop.f 0\r
81 nop.b 0\r
82 }\r
83$L143:\r
84 { .mii //R-Addr: 0X050 \r
85 fc r32 //27\r
86 adds r32=32, r32;; //28, 00000020H\r
87 cmp.ltu p14,p15=r32, r31 //29\r
88 }\r
89 { .mfb //R-Addr: 0X060 \r
90 nop.m 0\r
91 nop.f 0\r
92 (p14) br.cond.dptk.few $L143#;; //29, 880000/120000\r
93 }\r
94 { .mmi\r
95 sync.i;;\r
96 srlz.i\r
97 nop.i 0;;\r
98 }\r
99 { .mfb //R-Addr: 0X070 \r
100 nop.m 0\r
101 nop.f 0\r
102 br.ret.sptk.few b0;; //31\r
103 }\r
104// End code for function:\r
105 .endp InvalidateInstructionCacheRange#\r
106// END\r