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e1f414b6 | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
e1f414b6 | 6 | \r |
e1f414b6 | 7 | \r |
8 | **/\r | |
9 | \r | |
f734a10a A |
10 | #include <Base.h>\r |
11 | #include <Library/BaseLib.h>\r | |
12 | #include <Library/DebugLib.h>\r | |
e1f414b6 | 13 | \r |
e1f414b6 | 14 | /**\r |
15 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
16 | calling CPU.\r | |
17 | \r | |
e1f414b6 | 18 | **/\r |
19 | VOID\r | |
20 | EFIAPI\r | |
21 | InvalidateInstructionCache (\r | |
22 | VOID\r | |
23 | )\r | |
24 | {\r | |
25 | }\r | |
26 | \r | |
27 | /**\r | |
28 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
29 | of the calling CPU.\r | |
30 | \r | |
31 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
32 | Address is not aligned on a cache line boundary, then entire instruction\r | |
33 | cache line containing Address is invalidated. If Address + Length is not\r | |
34 | aligned on a cache line boundary, then the entire instruction cache line\r | |
35 | containing Address + Length -1 is invalidated. This function may choose to\r | |
36 | invalidate the entire instruction cache if that is more efficient than\r | |
35a17154 | 37 | invalidating the specified range. If Length is 0, then no instruction cache\r |
e1f414b6 | 38 | lines are invalidated. Address is returned.\r |
39 | \r | |
40 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
41 | \r | |
42 | @param Address The base address of the instruction cache lines to\r | |
43 | invalidate. If the CPU is in a physical addressing mode, then\r | |
44 | Address is a physical address. If the CPU is in a virtual\r | |
45 | addressing mode, then Address is a virtual address.\r | |
46 | \r | |
47 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
48 | \r | |
eb1c78db | 49 | @return Address.\r |
e1f414b6 | 50 | \r |
51 | **/\r | |
52 | VOID *\r | |
53 | EFIAPI\r | |
54 | InvalidateInstructionCacheRange (\r | |
55 | IN VOID *Address,\r | |
56 | IN UINTN Length\r | |
57 | )\r | |
58 | {\r | |
351d6e7f LG |
59 | if (Length == 0) {\r |
60 | return Address;\r | |
61 | }\r | |
62 | \r | |
63 | ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));\r | |
e1f414b6 | 64 | return Address;\r |
65 | }\r | |
66 | \r | |
67 | /**\r | |
35a17154 | 68 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 69 | of the calling CPU.\r |
70 | \r | |
35a17154 | 71 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 72 | of the calling CPU. This function guarantees that all dirty cache lines are\r |
73 | written back to system memory, and also invalidates all the data cache lines\r | |
74 | in the cache coherency domain of the calling CPU.\r | |
75 | \r | |
76 | **/\r | |
77 | VOID\r | |
78 | EFIAPI\r | |
79 | WriteBackInvalidateDataCache (\r | |
80 | VOID\r | |
81 | )\r | |
82 | {\r | |
83 | AsmWbinvd ();\r | |
84 | }\r | |
85 | \r | |
86 | /**\r | |
35a17154 | 87 | Writes back and invalidates a range of data cache lines in the cache\r |
e1f414b6 | 88 | coherency domain of the calling CPU.\r |
89 | \r | |
35a17154 | 90 | Writes back and invalidates the data cache lines specified by Address and\r |
e1f414b6 | 91 | Length. If Address is not aligned on a cache line boundary, then entire data\r |
92 | cache line containing Address is written back and invalidated. If Address +\r | |
93 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
94 | line containing Address + Length -1 is written back and invalidated. This\r | |
95 | function may choose to write back and invalidate the entire data cache if\r | |
96 | that is more efficient than writing back and invalidating the specified\r | |
35a17154 | 97 | range. If Length is 0, then no data cache lines are written back and\r |
e1f414b6 | 98 | invalidated. Address is returned.\r |
99 | \r | |
100 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
101 | \r | |
102 | @param Address The base address of the data cache lines to write back and\r | |
103 | invalidate. If the CPU is in a physical addressing mode, then\r | |
104 | Address is a physical address. If the CPU is in a virtual\r | |
105 | addressing mode, then Address is a virtual address.\r | |
106 | @param Length The number of bytes to write back and invalidate from the\r | |
107 | data cache.\r | |
108 | \r | |
38bbd3d9 | 109 | @return Address of cache invalidation.\r |
e1f414b6 | 110 | \r |
111 | **/\r | |
112 | VOID *\r | |
113 | EFIAPI\r | |
114 | WriteBackInvalidateDataCacheRange (\r | |
115 | IN VOID *Address,\r | |
116 | IN UINTN Length\r | |
117 | )\r | |
118 | {\r | |
d2660fe3 MK |
119 | UINT32 RegEbx;\r |
120 | UINT32 RegEdx;\r | |
121 | UINTN CacheLineSize;\r | |
ad400b07 | 122 | UINTN Start;\r |
123 | UINTN End;\r | |
e1f414b6 | 124 | \r |
e1f414b6 | 125 | if (Length == 0) {\r |
126 | return Address;\r | |
127 | }\r | |
128 | \r | |
351d6e7f LG |
129 | ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));\r |
130 | \r | |
d2660fe3 | 131 | //\r |
9095d37b | 132 | // If the CPU does not support CLFLUSH instruction,\r |
d2660fe3 MK |
133 | // then promote flush range to flush entire cache.\r |
134 | //\r | |
135 | AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);\r | |
136 | if ((RegEdx & BIT19) == 0) {\r | |
137 | AsmWbinvd ();\r | |
138 | return Address;\r | |
139 | }\r | |
140 | \r | |
141 | //\r | |
142 | // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H\r | |
143 | //\r | |
144 | CacheLineSize = (RegEbx & 0xff00) >> 5;\r | |
145 | \r | |
e1f414b6 | 146 | Start = (UINTN)Address;\r |
38bbd3d9 | 147 | //\r |
148 | // Calculate the cache line alignment\r | |
d2660fe3 MK |
149 | //\r |
150 | End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);\r | |
151 | Start &= ~((UINTN)CacheLineSize - 1);\r | |
e1f414b6 | 152 | \r |
153 | do {\r | |
d2660fe3 | 154 | Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CacheLineSize;\r |
e1f414b6 | 155 | } while (Start != End);\r |
156 | return Address;\r | |
157 | }\r | |
158 | \r | |
159 | /**\r | |
35a17154 | 160 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 161 | CPU.\r |
162 | \r | |
35a17154 | 163 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 164 | CPU. This function guarantees that all dirty cache lines are written back to\r |
165 | system memory. This function may also invalidate all the data cache lines in\r | |
166 | the cache coherency domain of the calling CPU.\r | |
167 | \r | |
168 | **/\r | |
169 | VOID\r | |
170 | EFIAPI\r | |
171 | WriteBackDataCache (\r | |
172 | VOID\r | |
173 | )\r | |
174 | {\r | |
175 | WriteBackInvalidateDataCache ();\r | |
176 | }\r | |
177 | \r | |
178 | /**\r | |
35a17154 | 179 | Writes back a range of data cache lines in the cache coherency domain of the\r |
e1f414b6 | 180 | calling CPU.\r |
181 | \r | |
35a17154 | 182 | Writes back the data cache lines specified by Address and Length. If Address\r |
e1f414b6 | 183 | is not aligned on a cache line boundary, then entire data cache line\r |
184 | containing Address is written back. If Address + Length is not aligned on a\r | |
185 | cache line boundary, then the entire data cache line containing Address +\r | |
186 | Length -1 is written back. This function may choose to write back the entire\r | |
187 | data cache if that is more efficient than writing back the specified range.\r | |
35a17154 | 188 | If Length is 0, then no data cache lines are written back. This function may\r |
e1f414b6 | 189 | also invalidate all the data cache lines in the specified range of the cache\r |
190 | coherency domain of the calling CPU. Address is returned.\r | |
191 | \r | |
192 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
193 | \r | |
194 | @param Address The base address of the data cache lines to write back. If\r | |
195 | the CPU is in a physical addressing mode, then Address is a\r | |
196 | physical address. If the CPU is in a virtual addressing\r | |
197 | mode, then Address is a virtual address.\r | |
198 | @param Length The number of bytes to write back from the data cache.\r | |
199 | \r | |
ad400b07 | 200 | @return Address of cache written in main memory.\r |
e1f414b6 | 201 | \r |
202 | **/\r | |
203 | VOID *\r | |
204 | EFIAPI\r | |
205 | WriteBackDataCacheRange (\r | |
206 | IN VOID *Address,\r | |
207 | IN UINTN Length\r | |
208 | )\r | |
209 | {\r | |
210 | return WriteBackInvalidateDataCacheRange (Address, Length);\r | |
211 | }\r | |
212 | \r | |
213 | /**\r | |
214 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
215 | CPU.\r | |
216 | \r | |
217 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
218 | CPU. This function must be used with care because dirty cache lines are not\r | |
219 | written back to system memory. It is typically used for cache diagnostics. If\r | |
220 | the CPU does not support invalidation of the entire data cache, then a write\r | |
221 | back and invalidate operation should be performed on the entire data cache.\r | |
222 | \r | |
223 | **/\r | |
224 | VOID\r | |
225 | EFIAPI\r | |
226 | InvalidateDataCache (\r | |
227 | VOID\r | |
228 | )\r | |
229 | {\r | |
230 | AsmInvd ();\r | |
231 | }\r | |
232 | \r | |
233 | /**\r | |
234 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
235 | calling CPU.\r | |
236 | \r | |
237 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
238 | is not aligned on a cache line boundary, then entire data cache line\r | |
239 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
240 | cache line boundary, then the entire data cache line containing Address +\r | |
241 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
35a17154 | 242 | outside the specified range. If Length is 0, then no data cache lines are\r |
e1f414b6 | 243 | invalidated. Address is returned. This function must be used with care\r |
244 | because dirty cache lines are not written back to system memory. It is\r | |
245 | typically used for cache diagnostics. If the CPU does not support\r | |
246 | invalidation of a data cache range, then a write back and invalidate\r | |
247 | operation should be performed on the data cache range.\r | |
248 | \r | |
249 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
250 | \r | |
251 | @param Address The base address of the data cache lines to invalidate. If\r | |
252 | the CPU is in a physical addressing mode, then Address is a\r | |
253 | physical address. If the CPU is in a virtual addressing mode,\r | |
254 | then Address is a virtual address.\r | |
255 | @param Length The number of bytes to invalidate from the data cache.\r | |
256 | \r | |
eb1c78db | 257 | @return Address.\r |
e1f414b6 | 258 | \r |
259 | **/\r | |
260 | VOID *\r | |
261 | EFIAPI\r | |
262 | InvalidateDataCacheRange (\r | |
263 | IN VOID *Address,\r | |
264 | IN UINTN Length\r | |
265 | )\r | |
266 | {\r | |
ad400b07 | 267 | //\r |
268 | // Invalidation of a data cache range without writing back is not supported on\r | |
269 | // x86 architecture, so write back and invalidate operation is performed.\r | |
270 | //\r | |
e1f414b6 | 271 | return WriteBackInvalidateDataCacheRange (Address, Length);\r |
272 | }\r |