Removed duplicate PalCallStatic functions in different libraries. Moved ReadItc and...
[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / x86Cache.c
CommitLineData
878ddf1f 1/** @file\r
2 Cache Maintenance Functions.\r
3\r
4 Copyright (c) 2006, Intel Corporation<BR>\r
5 All rights reserved. This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13 Module Name: x86Cache.c\r
14\r
15**/\r
16\r
ed9610eb 17//\r
18// This size must be at or below the smallest cache size possible among all\r
19// supported processors\r
20//\r
21#define CACHE_LINE_SIZE 0x20\r
22\r
9f84a609 23/**\r
24 Invalidates the entire instruction cache in cache coherency domain of the\r
25 calling CPU.\r
26\r
27 Invalidates the entire instruction cache in cache coherency domain of the\r
28 calling CPU.\r
29\r
30**/\r
878ddf1f 31VOID\r
32EFIAPI\r
33InvalidateInstructionCache (\r
34 VOID\r
35 )\r
36{\r
878ddf1f 37}\r
38\r
9f84a609 39/**\r
40 Invalidates a range of instruction cache lines in the cache coherency domain\r
41 of the calling CPU.\r
42\r
43 Invalidates the instruction cache lines specified by Address and Length. If\r
44 Address is not aligned on a cache line boundary, then entire instruction\r
45 cache line containing Address is invalidated. If Address + Length is not\r
46 aligned on a cache line boundary, then the entire instruction cache line\r
47 containing Address + Length -1 is invalidated. This function may choose to\r
48 invalidate the entire instruction cache if that is more efficient than\r
49 invalidating the specified range. If Length is 0, the no instruction cache\r
50 lines are invalidated. Address is returned.\r
51\r
52 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
53\r
54 @param Address The base address of the instruction cache lines to\r
55 invalidate. If the CPU is in a physical addressing mode, then\r
56 Address is a physical address. If the CPU is in a virtual\r
57 addressing mode, then Address is a virtual address.\r
58\r
59 @param Length The number of bytes to invalidate from the instruction cache.\r
60\r
61 @return Address\r
62\r
63**/\r
878ddf1f 64VOID *\r
65EFIAPI\r
66InvalidateInstructionCacheRange (\r
67 IN VOID *Address,\r
68 IN UINTN Length\r
69 )\r
70{\r
9f84a609 71 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
878ddf1f 72 return Address;\r
73}\r
74\r
9f84a609 75/**\r
76 Writes Back and Invalidates the entire data cache in cache coherency domain\r
77 of the calling CPU.\r
78\r
79 Writes Back and Invalidates the entire data cache in cache coherency domain\r
80 of the calling CPU. This function guarantees that all dirty cache lines are\r
81 written back to system memory, and also invalidates all the data cache lines\r
82 in the cache coherency domain of the calling CPU.\r
83\r
84**/\r
878ddf1f 85VOID\r
86EFIAPI\r
87WriteBackInvalidateDataCache (\r
88 VOID\r
89 )\r
90{\r
91 AsmWbinvd ();\r
92}\r
93\r
9f84a609 94/**\r
95 Writes Back and Invalidates a range of data cache lines in the cache\r
96 coherency domain of the calling CPU.\r
97\r
98 Writes Back and Invalidate the data cache lines specified by Address and\r
99 Length. If Address is not aligned on a cache line boundary, then entire data\r
100 cache line containing Address is written back and invalidated. If Address +\r
101 Length is not aligned on a cache line boundary, then the entire data cache\r
102 line containing Address + Length -1 is written back and invalidated. This\r
103 function may choose to write back and invalidate the entire data cache if\r
104 that is more efficient than writing back and invalidating the specified\r
105 range. If Length is 0, the no data cache lines are written back and\r
106 invalidated. Address is returned.\r
107\r
108 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
109\r
110 @param Address The base address of the data cache lines to write back and\r
111 invalidate. If the CPU is in a physical addressing mode, then\r
112 Address is a physical address. If the CPU is in a virtual\r
113 addressing mode, then Address is a virtual address.\r
114 @param Length The number of bytes to write back and invalidate from the\r
115 data cache.\r
116\r
117 @return Address\r
118\r
119**/\r
878ddf1f 120VOID *\r
121EFIAPI\r
122WriteBackInvalidateDataCacheRange (\r
123 IN VOID *Address,\r
124 IN UINTN Length\r
125 )\r
126{\r
ed9610eb 127 UINTN Start, End;\r
9f84a609 128\r
129 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
130\r
ed9610eb 131 if (Length == 0) {\r
132 return Address;\r
878ddf1f 133 }\r
ed9610eb 134\r
135 Start = (UINTN)Address;\r
136 End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);\r
137 Start &= ~(CACHE_LINE_SIZE - 1);\r
138\r
139 do {\r
140 Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;\r
141 } while (Start != End);\r
878ddf1f 142 return Address;\r
143}\r
144\r
9f84a609 145/**\r
146 Writes Back the entire data cache in cache coherency domain of the calling\r
147 CPU.\r
148\r
149 Writes Back the entire data cache in cache coherency domain of the calling\r
150 CPU. This function guarantees that all dirty cache lines are written back to\r
151 system memory. This function may also invalidate all the data cache lines in\r
152 the cache coherency domain of the calling CPU.\r
153\r
154**/\r
878ddf1f 155VOID\r
156EFIAPI\r
157WriteBackDataCache (\r
158 VOID\r
159 )\r
160{\r
9f84a609 161 WriteBackInvalidateDataCache ();\r
878ddf1f 162}\r
163\r
9f84a609 164/**\r
165 Writes Back a range of data cache lines in the cache coherency domain of the\r
166 calling CPU.\r
167\r
168 Writes Back the data cache lines specified by Address and Length. If Address\r
169 is not aligned on a cache line boundary, then entire data cache line\r
170 containing Address is written back. If Address + Length is not aligned on a\r
171 cache line boundary, then the entire data cache line containing Address +\r
172 Length -1 is written back. This function may choose to write back the entire\r
173 data cache if that is more efficient than writing back the specified range.\r
174 If Length is 0, the no data cache lines are written back. This function may\r
175 also invalidate all the data cache lines in the specified range of the cache\r
176 coherency domain of the calling CPU. Address is returned.\r
177\r
178 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
179\r
180 @param Address The base address of the data cache lines to write back. If\r
181 the CPU is in a physical addressing mode, then Address is a\r
182 physical address. If the CPU is in a virtual addressing\r
183 mode, then Address is a virtual address.\r
184 @param Length The number of bytes to write back from the data cache.\r
185\r
186 @return Address\r
187\r
188**/\r
878ddf1f 189VOID *\r
190EFIAPI\r
191WriteBackDataCacheRange (\r
192 IN VOID *Address,\r
193 IN UINTN Length\r
194 )\r
195{\r
9f84a609 196 return WriteBackInvalidateDataCacheRange (Address, Length);\r
878ddf1f 197}\r
198\r
9f84a609 199/**\r
200 Invalidates the entire data cache in cache coherency domain of the calling\r
201 CPU.\r
202\r
203 Invalidates the entire data cache in cache coherency domain of the calling\r
204 CPU. This function must be used with care because dirty cache lines are not\r
205 written back to system memory. It is typically used for cache diagnostics. If\r
206 the CPU does not support invalidation of the entire data cache, then a write\r
207 back and invalidate operation should be performed on the entire data cache.\r
208\r
209**/\r
878ddf1f 210VOID\r
211EFIAPI\r
212InvalidateDataCache (\r
213 VOID\r
214 )\r
215{\r
216 AsmInvd ();\r
217}\r
218\r
9f84a609 219/**\r
220 Invalidates a range of data cache lines in the cache coherency domain of the\r
221 calling CPU.\r
222\r
223 Invalidates the data cache lines specified by Address and Length. If Address\r
224 is not aligned on a cache line boundary, then entire data cache line\r
225 containing Address is invalidated. If Address + Length is not aligned on a\r
226 cache line boundary, then the entire data cache line containing Address +\r
227 Length -1 is invalidated. This function must never invalidate any cache lines\r
228 outside the specified range. If Length is 0, the no data cache lines are\r
229 invalidated. Address is returned. This function must be used with care\r
230 because dirty cache lines are not written back to system memory. It is\r
231 typically used for cache diagnostics. If the CPU does not support\r
232 invalidation of a data cache range, then a write back and invalidate\r
233 operation should be performed on the data cache range.\r
234\r
235 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
236\r
237 @param Address The base address of the data cache lines to invalidate. If\r
238 the CPU is in a physical addressing mode, then Address is a\r
239 physical address. If the CPU is in a virtual addressing mode,\r
240 then Address is a virtual address.\r
241 @param Length The number of bytes to invalidate from the data cache.\r
242\r
243 @return Address\r
244\r
245**/\r
878ddf1f 246VOID *\r
247EFIAPI\r
248InvalidateDataCacheRange (\r
249 IN VOID *Address,\r
250 IN UINTN Length\r
251 )\r
252{\r
9f84a609 253 return WriteBackInvalidateDataCacheRange (Address, Length);\r
878ddf1f 254}\r