projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| e0337bfa | 1 | /** @file\r |
| 2 | Base Library CPU functions for Itanium\r | |
| 3 | \r | |
| de2d3419 HT |
4 | Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r |
| 5 | This program and the accompanying materials\r | |
| e0337bfa | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| fa73b3be | 15 | #include <Library/PalLib.h>\r |
| 44c0fd78 | 16 | #include <Library/BaseLib.h>\r |
| e0337bfa | 17 | \r |
| 18 | /**\r | |
| 19 | Places the CPU in a sleep state until an interrupt is received.\r | |
| 20 | \r | |
| 21 | Places the CPU in a sleep state until an interrupt is received. If interrupts\r | |
| 22 | are disabled prior to calling this function, then the CPU will be placed in a\r | |
| 23 | sleep state indefinitely.\r | |
| 24 | \r | |
| 25 | **/\r | |
| 26 | VOID\r | |
| 27 | EFIAPI\r | |
| 28 | CpuSleep (\r | |
| 29 | VOID\r | |
| 30 | )\r | |
| 31 | {\r | |
| 44c0fd78 | 32 | UINT64 Tpr;\r |
| 33 | \r | |
| 34 | //\r | |
| 35 | // It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state\r | |
| 36 | // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.\r | |
| 37 | // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.\r | |
| 38 | // If interrupts are enabled, then just use current TRP setting.\r | |
| 39 | //\r | |
| 40 | if (GetInterruptState ()) {\r | |
| 41 | //\r | |
| 42 | // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.\r | |
| 43 | //\r | |
| 44 | PalCall (PAL_HALT_LIGHT, 0, 0, 0);\r | |
| 45 | } else {\r | |
| 46 | //\r | |
| 47 | // If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.\r | |
| 48 | //\r | |
| 49 | \r | |
| 50 | //\r | |
| 51 | // Save TPR\r | |
| 52 | //\r | |
| 53 | Tpr = AsmReadTpr();\r | |
| 54 | //\r | |
| 55 | // Set TPR.mmi to mask all external interrupts\r | |
| 56 | //\r | |
| 57 | AsmWriteTpr (BIT16 | Tpr);\r | |
| 58 | \r | |
| 59 | PalCall (PAL_HALT_LIGHT, 0, 0, 0);\r | |
| 60 | \r | |
| 61 | //\r | |
| 62 | // Restore TPR\r | |
| 63 | //\r | |
| 64 | AsmWriteTpr (Tpr);\r | |
| 65 | }\r | |
| e0337bfa | 66 | }\r |