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1;------------------------------------------------------------------------------\r
2;\r
3; CpuBreakpoint() for AArch64\r
4;\r
5; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
6; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
7; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
9344f092 8; SPDX-License-Identifier: BSD-2-Clause-Patent\r
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9;\r
10;------------------------------------------------------------------------------\r
11\r
12\r
13 EXPORT CpuBreakpoint\r
14 AREA BaseLib_LowLevel, CODE, READONLY\r
15\r
16;/**\r
17; Generates a breakpoint on the CPU.\r
18;\r
19; Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
20; that code can resume normal execution after the breakpoint.\r
21;\r
22;**/\r
23;VOID\r
24;EFIAPI\r
25;CpuBreakpoint (\r
26; VOID\r
27; );\r
28;\r
29CpuBreakpoint\r
30 svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.\r
31 ret\r
32\r
33 END\r