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9095d37b 1;------------------------------------------------------------------------------\r
ebd04fc2 2;\r
3; CpuBreakpoint() for ARM\r
4;\r
9095d37b 5; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
bb817c56
HT
6; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
7; This program and the accompanying materials\r
ebd04fc2 8; are licensed and made available under the terms and conditions of the BSD License\r
9; which accompanies this distribution. The full text of the license may be found at\r
35a17154 10; http://opensource.org/licenses/bsd-license.php.\r
ebd04fc2 11;\r
12; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14;\r
15;------------------------------------------------------------------------------\r
16\r
17 EXPORT CpuBreakpoint\r
18\r
30939ff2
PB
19; Force ARM mode for this section, as MSFT assembler defaults to THUMB\r
20 AREA Cpu_Breakpoint, CODE, READONLY, ARM\r
21\r
22 ARM\r
ebd04fc2 23\r
24;/**\r
25; Generates a breakpoint on the CPU.\r
26;\r
27; Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
28; that code can resume normal execution after the breakpoint.\r
29;\r
30;**/\r
31;VOID\r
32;EFIAPI\r
33;CpuBreakpoint (\r
34; VOID\r
35; );\r
36;\r
37CpuBreakpoint\r
38 swi 0xdbdbdb\r
39 bx lr\r
9095d37b 40\r
ebd04fc2 41 END\r