projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 6bfbb5f0 | 1 | ## @file\r |
| 34b0820e | 2 | # Base Library implementation.\r |
| 85ea851e | 3 | #\r |
| 88a75d26 | 4 | # Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>\r |
| bb817c56 | 5 | # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 807e2604 | 6 | # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r |
| e1f414b6 | 7 | #\r |
| bb817c56 | 8 | # This program and the accompanying materials\r |
| e1f414b6 | 9 | # are licensed and made available under the terms and conditions of the BSD License\r |
| 10 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 127010dd | 11 | # http://opensource.org/licenses/bsd-license.php.\r |
| e1f414b6 | 12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 14 | #\r | |
| 15 | #\r | |
| 6bfbb5f0 | 16 | ##\r |
| e1f414b6 | 17 | \r |
| e1f414b6 | 18 | [Defines]\r |
| 19 | INF_VERSION = 0x00010005\r | |
| 20 | BASE_NAME = BaseLib\r | |
| c92c1790 | 21 | MODULE_UNI_FILE = BaseLib.uni\r |
| e1f414b6 | 22 | FILE_GUID = 27d67720-ea68-48ae-93da-a3a074c90e30\r |
| 23 | MODULE_TYPE = BASE\r | |
| 88a75d26 | 24 | VERSION_STRING = 1.1\r |
| e1f414b6 | 25 | LIBRARY_CLASS = BaseLib \r |
| e1f414b6 | 26 | \r |
| e1f414b6 | 27 | #\r |
| 807e2604 | 28 | # VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r |
| e1f414b6 | 29 | #\r |
| 30 | \r | |
| 6bfbb5f0 | 31 | [Sources]\r |
| e1f414b6 | 32 | CheckSum.c\r |
| 33 | SwitchStack.c\r | |
| 34 | SwapBytes64.c\r | |
| 35 | SwapBytes32.c\r | |
| 36 | SwapBytes16.c\r | |
| 37 | LongJump.c\r | |
| 38 | SetJump.c\r | |
| 39 | RShiftU64.c\r | |
| 40 | RRotU64.c\r | |
| 41 | RRotU32.c\r | |
| 42 | MultU64x64.c\r | |
| 43 | MultU64x32.c\r | |
| 44 | MultS64x64.c\r | |
| 45 | ModU64x32.c\r | |
| 46 | LShiftU64.c\r | |
| 47 | LRotU64.c\r | |
| 48 | LRotU32.c\r | |
| 49 | LowBitSet64.c\r | |
| 50 | LowBitSet32.c\r | |
| 51 | HighBitSet64.c\r | |
| 52 | HighBitSet32.c\r | |
| 53 | GetPowerOfTwo64.c\r | |
| 54 | GetPowerOfTwo32.c\r | |
| 55 | DivU64x64Remainder.c\r | |
| 56 | DivU64x32Remainder.c\r | |
| 57 | DivU64x32.c\r | |
| 58 | DivS64x64Remainder.c\r | |
| 59 | ARShiftU64.c\r | |
| 60 | BitField.c\r | |
| 61 | CpuDeadLoop.c\r | |
| 62 | Cpu.c\r | |
| 63 | LinkedList.c\r | |
| c058d59f | 64 | SafeString.c\r |
| e1f414b6 | 65 | String.c\r |
| ae591c14 | 66 | FilePaths.c\r |
| e1f414b6 | 67 | BaseLibInternals.h\r |
| e1f414b6 | 68 | \r |
| 69 | [Sources.Ia32]\r | |
| 6b4fe92a | 70 | Ia32/Wbinvd.c | MSFT \r |
| 71 | Ia32/WriteMm7.c | MSFT \r | |
| 72 | Ia32/WriteMm6.c | MSFT \r | |
| 73 | Ia32/WriteMm5.c | MSFT \r | |
| 74 | Ia32/WriteMm4.c | MSFT \r | |
| 75 | Ia32/WriteMm3.c | MSFT \r | |
| 76 | Ia32/WriteMm2.c | MSFT \r | |
| 77 | Ia32/WriteMm1.c | MSFT \r | |
| 78 | Ia32/WriteMm0.c | MSFT \r | |
| 79 | Ia32/WriteLdtr.c | MSFT \r | |
| 80 | Ia32/WriteIdtr.c | MSFT \r | |
| 81 | Ia32/WriteGdtr.c | MSFT \r | |
| 82 | Ia32/WriteDr7.c | MSFT \r | |
| 83 | Ia32/WriteDr6.c | MSFT \r | |
| 84 | Ia32/WriteDr5.c | MSFT \r | |
| 85 | Ia32/WriteDr4.c | MSFT \r | |
| 86 | Ia32/WriteDr3.c | MSFT \r | |
| 87 | Ia32/WriteDr2.c | MSFT \r | |
| 88 | Ia32/WriteDr1.c | MSFT \r | |
| 89 | Ia32/WriteDr0.c | MSFT \r | |
| 90 | Ia32/WriteCr4.c | MSFT \r | |
| 91 | Ia32/WriteCr3.c | MSFT \r | |
| 92 | Ia32/WriteCr2.c | MSFT \r | |
| 93 | Ia32/WriteCr0.c | MSFT \r | |
| 94 | Ia32/WriteMsr64.c | MSFT \r | |
| 6b4fe92a | 95 | Ia32/SwapBytes64.c | MSFT \r |
| 96 | Ia32/SetJump.c | MSFT \r | |
| 97 | Ia32/RRotU64.c | MSFT \r | |
| 98 | Ia32/RShiftU64.c | MSFT \r | |
| 99 | Ia32/ReadPmc.c | MSFT \r | |
| 100 | Ia32/ReadTsc.c | MSFT \r | |
| 101 | Ia32/ReadLdtr.c | MSFT \r | |
| 102 | Ia32/ReadIdtr.c | MSFT \r | |
| 103 | Ia32/ReadGdtr.c | MSFT \r | |
| 104 | Ia32/ReadTr.c | MSFT \r | |
| 105 | Ia32/ReadSs.c | MSFT \r | |
| 106 | Ia32/ReadGs.c | MSFT \r | |
| 107 | Ia32/ReadFs.c | MSFT \r | |
| 108 | Ia32/ReadEs.c | MSFT \r | |
| 109 | Ia32/ReadDs.c | MSFT \r | |
| 110 | Ia32/ReadCs.c | MSFT \r | |
| 111 | Ia32/ReadMsr64.c | MSFT \r | |
| 112 | Ia32/ReadMm7.c | MSFT \r | |
| 113 | Ia32/ReadMm6.c | MSFT \r | |
| 114 | Ia32/ReadMm5.c | MSFT \r | |
| 115 | Ia32/ReadMm4.c | MSFT \r | |
| 116 | Ia32/ReadMm3.c | MSFT \r | |
| 117 | Ia32/ReadMm2.c | MSFT \r | |
| 118 | Ia32/ReadMm1.c | MSFT \r | |
| 119 | Ia32/ReadMm0.c | MSFT \r | |
| 120 | Ia32/ReadEflags.c | MSFT \r | |
| 121 | Ia32/ReadDr7.c | MSFT \r | |
| 122 | Ia32/ReadDr6.c | MSFT \r | |
| 123 | Ia32/ReadDr5.c | MSFT \r | |
| 124 | Ia32/ReadDr4.c | MSFT \r | |
| 125 | Ia32/ReadDr3.c | MSFT \r | |
| 126 | Ia32/ReadDr2.c | MSFT \r | |
| 127 | Ia32/ReadDr1.c | MSFT \r | |
| 128 | Ia32/ReadDr0.c | MSFT \r | |
| 129 | Ia32/ReadCr4.c | MSFT \r | |
| 130 | Ia32/ReadCr3.c | MSFT \r | |
| 131 | Ia32/ReadCr2.c | MSFT \r | |
| 132 | Ia32/ReadCr0.c | MSFT \r | |
| 133 | Ia32/Mwait.c | MSFT \r | |
| 134 | Ia32/Monitor.c | MSFT \r | |
| 135 | Ia32/ModU64x32.c | MSFT \r | |
| 136 | Ia32/MultU64x64.c | MSFT \r | |
| 137 | Ia32/MultU64x32.c | MSFT \r | |
| 138 | Ia32/LShiftU64.c | MSFT \r | |
| 139 | Ia32/LRotU64.c | MSFT \r | |
| 140 | Ia32/LongJump.c | MSFT \r | |
| 141 | Ia32/Invd.c | MSFT \r | |
| 6b4fe92a | 142 | Ia32/FxRestore.c | MSFT \r |
| 143 | Ia32/FxSave.c | MSFT \r | |
| 144 | Ia32/FlushCacheLine.c | MSFT \r | |
| 6b4fe92a | 145 | Ia32/EnablePaging32.c | MSFT \r |
| 146 | Ia32/EnableInterrupts.c | MSFT \r | |
| 147 | Ia32/EnableDisableInterrupts.c | MSFT \r | |
| 41c7f551 | 148 | Ia32/DivU64x64Remainder.asm | MSFT \r |
| 6b4fe92a | 149 | Ia32/DivU64x32Remainder.c | MSFT \r |
| 150 | Ia32/DivU64x32.c | MSFT \r | |
| 151 | Ia32/DisablePaging32.c | MSFT \r | |
| 152 | Ia32/DisableInterrupts.c | MSFT \r | |
| 153 | Ia32/CpuPause.c | MSFT \r | |
| 154 | Ia32/CpuIdEx.c | MSFT \r | |
| 155 | Ia32/CpuId.c | MSFT \r | |
| 6b4fe92a | 156 | Ia32/CpuBreakpoint.c | MSFT \r |
| 157 | Ia32/ARShiftU64.c | MSFT \r | |
| b26978d3 | 158 | Ia32/Thunk16.asm | MSFT\r |
| 159 | Ia32/EnablePaging64.asm | MSFT\r | |
| 9f4f2f0e | 160 | Ia32/EnableCache.c | MSFT\r |
| 161 | Ia32/DisableCache.c | MSFT\r | |
| 3cfc7813 | 162 | Ia32/RdRand.asm | MSFT\r |
| d074a8e1 | 163 | \r |
| 164 | Ia32/Wbinvd.asm | INTEL \r | |
| 165 | Ia32/WriteMm7.asm | INTEL \r | |
| 166 | Ia32/WriteMm6.asm | INTEL \r | |
| 167 | Ia32/WriteMm5.asm | INTEL \r | |
| 168 | Ia32/WriteMm4.asm | INTEL \r | |
| 169 | Ia32/WriteMm3.asm | INTEL \r | |
| 170 | Ia32/WriteMm2.asm | INTEL \r | |
| 171 | Ia32/WriteMm1.asm | INTEL \r | |
| 172 | Ia32/WriteMm0.asm | INTEL \r | |
| 173 | Ia32/WriteLdtr.asm | INTEL \r | |
| 174 | Ia32/WriteIdtr.asm | INTEL \r | |
| 175 | Ia32/WriteGdtr.asm | INTEL \r | |
| 176 | Ia32/WriteDr7.asm | INTEL \r | |
| 177 | Ia32/WriteDr6.asm | INTEL \r | |
| 178 | Ia32/WriteDr5.asm | INTEL \r | |
| 179 | Ia32/WriteDr4.asm | INTEL \r | |
| 180 | Ia32/WriteDr3.asm | INTEL \r | |
| 181 | Ia32/WriteDr2.asm | INTEL \r | |
| 182 | Ia32/WriteDr1.asm | INTEL \r | |
| 183 | Ia32/WriteDr0.asm | INTEL \r | |
| 184 | Ia32/WriteCr4.asm | INTEL \r | |
| 185 | Ia32/WriteCr3.asm | INTEL \r | |
| 186 | Ia32/WriteCr2.asm | INTEL \r | |
| 187 | Ia32/WriteCr0.asm | INTEL \r | |
| 188 | Ia32/WriteMsr64.asm | INTEL \r | |
| 189 | Ia32/SwapBytes64.asm | INTEL \r | |
| 190 | Ia32/SetJump.asm | INTEL \r | |
| 191 | Ia32/RRotU64.asm | INTEL \r | |
| 192 | Ia32/RShiftU64.asm | INTEL \r | |
| 193 | Ia32/ReadPmc.asm | INTEL \r | |
| 194 | Ia32/ReadTsc.asm | INTEL \r | |
| 195 | Ia32/ReadLdtr.asm | INTEL \r | |
| 196 | Ia32/ReadIdtr.asm | INTEL \r | |
| 197 | Ia32/ReadGdtr.asm | INTEL \r | |
| 198 | Ia32/ReadTr.asm | INTEL \r | |
| 199 | Ia32/ReadSs.asm | INTEL \r | |
| 200 | Ia32/ReadGs.asm | INTEL \r | |
| 201 | Ia32/ReadFs.asm | INTEL \r | |
| 202 | Ia32/ReadEs.asm | INTEL \r | |
| 203 | Ia32/ReadDs.asm | INTEL \r | |
| 204 | Ia32/ReadCs.asm | INTEL \r | |
| 205 | Ia32/ReadMsr64.asm | INTEL \r | |
| 206 | Ia32/ReadMm7.asm | INTEL \r | |
| 207 | Ia32/ReadMm6.asm | INTEL \r | |
| 208 | Ia32/ReadMm5.asm | INTEL \r | |
| 209 | Ia32/ReadMm4.asm | INTEL \r | |
| 210 | Ia32/ReadMm3.asm | INTEL \r | |
| 211 | Ia32/ReadMm2.asm | INTEL \r | |
| 212 | Ia32/ReadMm1.asm | INTEL \r | |
| 213 | Ia32/ReadMm0.asm | INTEL \r | |
| 214 | Ia32/ReadEflags.asm | INTEL \r | |
| 215 | Ia32/ReadDr7.asm | INTEL \r | |
| 216 | Ia32/ReadDr6.asm | INTEL \r | |
| 217 | Ia32/ReadDr5.asm | INTEL \r | |
| 218 | Ia32/ReadDr4.asm | INTEL \r | |
| 219 | Ia32/ReadDr3.asm | INTEL \r | |
| 220 | Ia32/ReadDr2.asm | INTEL \r | |
| 221 | Ia32/ReadDr1.asm | INTEL \r | |
| 222 | Ia32/ReadDr0.asm | INTEL \r | |
| 223 | Ia32/ReadCr4.asm | INTEL \r | |
| 224 | Ia32/ReadCr3.asm | INTEL \r | |
| 225 | Ia32/ReadCr2.asm | INTEL \r | |
| 226 | Ia32/ReadCr0.asm | INTEL \r | |
| 227 | Ia32/Mwait.asm | INTEL \r | |
| 228 | Ia32/Monitor.asm | INTEL \r | |
| 229 | Ia32/ModU64x32.asm | INTEL \r | |
| 230 | Ia32/MultU64x64.asm | INTEL \r | |
| 231 | Ia32/MultU64x32.asm | INTEL \r | |
| 232 | Ia32/LShiftU64.asm | INTEL \r | |
| 233 | Ia32/LRotU64.asm | INTEL \r | |
| 234 | Ia32/LongJump.asm | INTEL \r | |
| 235 | Ia32/Invd.asm | INTEL \r | |
| d074a8e1 | 236 | Ia32/FxRestore.asm | INTEL \r |
| 237 | Ia32/FxSave.asm | INTEL \r | |
| 238 | Ia32/FlushCacheLine.asm | INTEL \r | |
| 239 | Ia32/EnablePaging32.asm | INTEL \r | |
| 240 | Ia32/EnableInterrupts.asm | INTEL \r | |
| 241 | Ia32/EnableDisableInterrupts.asm | INTEL \r | |
| 242 | Ia32/DivU64x64Remainder.asm | INTEL \r | |
| 243 | Ia32/DivU64x32Remainder.asm | INTEL \r | |
| 244 | Ia32/DivU64x32.asm | INTEL \r | |
| 245 | Ia32/DisablePaging32.asm | INTEL \r | |
| 246 | Ia32/DisableInterrupts.asm | INTEL \r | |
| 247 | Ia32/CpuPause.asm | INTEL \r | |
| 248 | Ia32/CpuIdEx.asm | INTEL \r | |
| 249 | Ia32/CpuId.asm | INTEL \r | |
| d074a8e1 | 250 | Ia32/CpuBreakpoint.asm | INTEL \r |
| 251 | Ia32/ARShiftU64.asm | INTEL \r | |
| b26978d3 | 252 | Ia32/Thunk16.asm | INTEL\r |
| 253 | Ia32/EnablePaging64.asm | INTEL\r | |
| 9f4f2f0e | 254 | Ia32/EnableCache.asm | INTEL\r |
| 255 | Ia32/DisableCache.asm | INTEL\r | |
| 3cfc7813 | 256 | Ia32/RdRand.asm | INTEL\r |
| d074a8e1 | 257 | \r |
| cf683fed | 258 | Ia32/GccInline.c | GCC\r |
| 6dab5c8a | 259 | Ia32/Thunk16.nasm | GCC \r |
| 9a12358c | 260 | Ia32/Thunk16.S | XCODE \r |
| 6b4fe92a | 261 | Ia32/EnableDisableInterrupts.S | GCC \r |
| 6b4fe92a | 262 | Ia32/EnablePaging64.S | GCC \r |
| 263 | Ia32/DisablePaging32.S | GCC \r | |
| 264 | Ia32/EnablePaging32.S | GCC \r | |
| 265 | Ia32/Mwait.S | GCC \r | |
| 266 | Ia32/Monitor.S | GCC \r | |
| 6b4fe92a | 267 | Ia32/CpuIdEx.S | GCC \r |
| 268 | Ia32/CpuId.S | GCC \r | |
| 269 | Ia32/LongJump.S | GCC \r | |
| 270 | Ia32/SetJump.S | GCC \r | |
| 271 | Ia32/SwapBytes64.S | GCC \r | |
| 272 | Ia32/DivU64x64Remainder.S | GCC \r | |
| 273 | Ia32/DivU64x32Remainder.S | GCC \r | |
| 274 | Ia32/ModU64x32.S | GCC \r | |
| 275 | Ia32/DivU64x32.S | GCC \r | |
| 276 | Ia32/MultU64x64.S | GCC \r | |
| 277 | Ia32/MultU64x32.S | GCC \r | |
| 278 | Ia32/RRotU64.S | GCC \r | |
| 279 | Ia32/LRotU64.S | GCC \r | |
| 280 | Ia32/ARShiftU64.S | GCC \r | |
| 281 | Ia32/RShiftU64.S | GCC \r | |
| 282 | Ia32/LShiftU64.S | GCC \r | |
| 9f4f2f0e | 283 | Ia32/EnableCache.S | GCC\r |
| 284 | Ia32/DisableCache.S | GCC\r | |
| 3cfc7813 | 285 | Ia32/RdRand.S | GCC\r |
| d074a8e1 | 286 | \r |
| bb40027d | 287 | Ia32/DivS64x64Remainder.c\r |
| bab427db | 288 | Ia32/InternalSwitchStack.c | MSFT\r |
| 289 | Ia32/InternalSwitchStack.c | INTEL\r | |
| 290 | Ia32/InternalSwitchStack.S | GCC\r | |
| e1f414b6 | 291 | Ia32/Non-existing.c\r |
| 292 | Unaligned.c\r | |
| b26978d3 | 293 | X86WriteIdtr.c\r |
| 294 | X86WriteGdtr.c\r | |
| 295 | X86Thunk.c\r | |
| 296 | X86ReadIdtr.c\r | |
| 297 | X86ReadGdtr.c\r | |
| 298 | X86Msr.c\r | |
| c756ce80 | 299 | X86MemoryFence.c | MSFT\r |
| 300 | X86MemoryFence.c | INTEL\r | |
| b26978d3 | 301 | X86GetInterruptState.c\r |
| 302 | X86FxSave.c\r | |
| 303 | X86FxRestore.c\r | |
| 304 | X86EnablePaging64.c\r | |
| 305 | X86EnablePaging32.c\r | |
| 306 | X86DisablePaging64.c\r | |
| 307 | X86DisablePaging32.c\r | |
| e1f414b6 | 308 | \r |
| 309 | [Sources.X64]\r | |
| 310 | X64/Thunk16.asm\r | |
| e1f414b6 | 311 | X64/CpuPause.asm\r |
| e1f414b6 | 312 | X64/EnableDisableInterrupts.asm\r |
| 313 | X64/DisableInterrupts.asm\r | |
| 314 | X64/EnableInterrupts.asm\r | |
| e1f414b6 | 315 | X64/FlushCacheLine.asm\r |
| 316 | X64/Invd.asm\r | |
| 317 | X64/Wbinvd.asm\r | |
| 318 | X64/DisablePaging64.asm\r | |
| e1f414b6 | 319 | X64/Mwait.asm\r |
| 320 | X64/Monitor.asm\r | |
| 321 | X64/ReadPmc.asm\r | |
| 322 | X64/ReadTsc.asm\r | |
| 323 | X64/WriteMm7.asm\r | |
| 324 | X64/WriteMm6.asm\r | |
| 325 | X64/WriteMm5.asm\r | |
| 326 | X64/WriteMm4.asm\r | |
| 327 | X64/WriteMm3.asm\r | |
| 328 | X64/WriteMm2.asm\r | |
| 329 | X64/WriteMm1.asm\r | |
| 330 | X64/WriteMm0.asm\r | |
| 331 | X64/ReadMm7.asm\r | |
| 332 | X64/ReadMm6.asm\r | |
| 333 | X64/ReadMm5.asm\r | |
| 334 | X64/ReadMm4.asm\r | |
| 335 | X64/ReadMm3.asm\r | |
| 336 | X64/ReadMm2.asm\r | |
| 337 | X64/ReadMm1.asm\r | |
| 338 | X64/ReadMm0.asm\r | |
| 339 | X64/FxRestore.asm\r | |
| 340 | X64/FxSave.asm\r | |
| 341 | X64/WriteLdtr.asm\r | |
| 342 | X64/ReadLdtr.asm\r | |
| 343 | X64/WriteIdtr.asm\r | |
| 344 | X64/ReadIdtr.asm\r | |
| 345 | X64/WriteGdtr.asm\r | |
| 346 | X64/ReadGdtr.asm\r | |
| 347 | X64/ReadTr.asm\r | |
| 348 | X64/ReadSs.asm\r | |
| 349 | X64/ReadGs.asm\r | |
| 350 | X64/ReadFs.asm\r | |
| 351 | X64/ReadEs.asm\r | |
| 352 | X64/ReadDs.asm\r | |
| 353 | X64/ReadCs.asm\r | |
| 354 | X64/WriteDr7.asm\r | |
| 355 | X64/WriteDr6.asm\r | |
| 356 | X64/WriteDr5.asm\r | |
| 357 | X64/WriteDr4.asm\r | |
| 358 | X64/WriteDr3.asm\r | |
| 359 | X64/WriteDr2.asm\r | |
| 360 | X64/WriteDr1.asm\r | |
| 361 | X64/WriteDr0.asm\r | |
| 362 | X64/ReadDr7.asm\r | |
| 363 | X64/ReadDr6.asm\r | |
| 364 | X64/ReadDr5.asm\r | |
| 365 | X64/ReadDr4.asm\r | |
| 366 | X64/ReadDr3.asm\r | |
| 367 | X64/ReadDr2.asm\r | |
| 368 | X64/ReadDr1.asm\r | |
| 369 | X64/ReadDr0.asm\r | |
| 370 | X64/WriteCr4.asm\r | |
| 371 | X64/WriteCr3.asm\r | |
| 372 | X64/WriteCr2.asm\r | |
| 373 | X64/WriteCr0.asm\r | |
| 374 | X64/ReadCr4.asm\r | |
| 375 | X64/ReadCr3.asm\r | |
| 376 | X64/ReadCr2.asm\r | |
| 377 | X64/ReadCr0.asm\r | |
| e1f414b6 | 378 | X64/ReadEflags.asm\r |
| 379 | X64/CpuIdEx.asm\r | |
| 380 | X64/CpuId.asm\r | |
| 381 | X64/LongJump.asm\r | |
| 382 | X64/SetJump.asm\r | |
| 383 | X64/SwitchStack.asm\r | |
| 9f4f2f0e | 384 | X64/EnableCache.asm\r |
| 385 | X64/DisableCache.asm\r | |
| d074a8e1 | 386 | \r |
| d074a8e1 | 387 | X64/CpuBreakpoint.c | MSFT \r |
| 388 | X64/WriteMsr64.c | MSFT \r | |
| 389 | X64/ReadMsr64.c | MSFT \r | |
| 3cfc7813 | 390 | X64/RdRand.asm | MSFT\r |
| d074a8e1 | 391 | \r |
| d074a8e1 | 392 | X64/CpuBreakpoint.asm | INTEL \r |
| 393 | X64/WriteMsr64.asm | INTEL \r | |
| 394 | X64/ReadMsr64.asm | INTEL \r | |
| 3cfc7813 | 395 | X64/RdRand.asm | INTEL\r |
| d074a8e1 | 396 | \r |
| e1f414b6 | 397 | X64/Non-existing.c\r |
| 398 | Math64.c\r | |
| 399 | Unaligned.c\r | |
| b26978d3 | 400 | X86WriteIdtr.c\r |
| 401 | X86WriteGdtr.c\r | |
| 402 | X86Thunk.c\r | |
| 403 | X86ReadIdtr.c\r | |
| 404 | X86ReadGdtr.c\r | |
| 405 | X86Msr.c\r | |
| 2653bb43 | 406 | X86MemoryFence.c | MSFT\r |
| 407 | X86MemoryFence.c | INTEL\r | |
| b26978d3 | 408 | X86GetInterruptState.c\r |
| 409 | X86FxSave.c\r | |
| 410 | X86FxRestore.c\r | |
| 411 | X86EnablePaging64.c\r | |
| 412 | X86EnablePaging32.c\r | |
| 413 | X86DisablePaging64.c\r | |
| 414 | X86DisablePaging32.c\r | |
| cf683fed | 415 | X64/GccInline.c | GCC\r |
| fbb5393c | 416 | X64/Thunk16.nasm | GCC \r |
| 9a12358c | 417 | X64/Thunk16.S | XCODE \r |
| 6b4fe92a | 418 | X64/SwitchStack.S | GCC \r |
| 419 | X64/SetJump.S | GCC \r | |
| 6b4fe92a | 420 | X64/LongJump.S | GCC \r |
| 6b4fe92a | 421 | X64/EnableDisableInterrupts.S | GCC \r |
| 422 | X64/DisablePaging64.S | GCC \r | |
| 6b4fe92a | 423 | X64/CpuId.S | GCC \r |
| 424 | X64/CpuIdEx.S | GCC \r | |
| 9f4f2f0e | 425 | X64/EnableCache.S | GCC\r |
| 426 | X64/DisableCache.S | GCC\r | |
| 3cfc7813 | 427 | X64/RdRand.S | GCC\r |
| a21f46e4 | 428 | ChkStkGcc.c | GCC \r |
| e1f414b6 | 429 | \r |
| 430 | [Sources.IPF]\r | |
| 431 | Ipf/AccessGp.s\r | |
| 432 | Ipf/ReadCpuid.s\r | |
| 433 | Ipf/ExecFc.s\r | |
| 434 | Ipf/AsmPalCall.s\r | |
| 435 | Ipf/AccessPsr.s\r | |
| 436 | Ipf/AccessPmr.s\r | |
| 437 | Ipf/AccessKr.s\r | |
| 8facd18f | 438 | Ipf/AccessKr7.s\r |
| e1f414b6 | 439 | Ipf/AccessGcr.s\r |
| 440 | Ipf/AccessEicr.s\r | |
| 441 | Ipf/AccessDbr.s\r | |
| 59e0bb0c | 442 | Ipf/AccessMsr.s | INTEL\r |
| 4e16d2cd | 443 | Ipf/AccessMsr.s | GCC\r |
| 444 | Ipf/AccessMsrDb.s | MSFT\r | |
| 287f4f47 | 445 | Ipf/InternalFlushCacheRange.s\r |
| 446 | Ipf/FlushCacheRange.c\r | |
| e1f414b6 | 447 | Ipf/InternalSwitchStack.c\r |
| 448 | Ipf/GetInterruptState.s\r | |
| e1f414b6 | 449 | Ipf/CpuPause.s\r |
| 878afe6b | 450 | Ipf/CpuBreakpoint.c | INTEL\r |
| 451 | Ipf/CpuBreakpointMsc.c | MSFT\r | |
| 59e0bb0c | 452 | Ipf/AsmCpuMisc.s | GCC\r |
| e1f414b6 | 453 | Ipf/Unaligned.c\r |
| 454 | Ipf/SwitchStack.s\r | |
| 572b6b1a | 455 | Ipf/LongJmp.s\r |
| 456 | Ipf/SetJmp.s\r | |
| aad6137d | 457 | Ipf/ReadCr.s\r |
| aad6137d | 458 | Ipf/ReadAr.s\r |
| 572b6b1a | 459 | Ipf/Ia64gen.h\r |
| 460 | Ipf/Asm.h\r | |
| e1f414b6 | 461 | Math64.c\r |
| e1f414b6 | 462 | \r |
| 463 | [Sources.EBC]\r | |
| e1f414b6 | 464 | Ebc/CpuBreakpoint.c\r |
| 465 | Ebc/SetJumpLongJump.c\r | |
| 466 | Ebc/SwitchStack.c\r | |
| 467 | Unaligned.c\r | |
| 468 | Math64.c\r | |
| 469 | \r | |
| 4b5f371b | 470 | [Sources.ARM]\r |
| 471 | Arm/InternalSwitchStack.c\r | |
| 472 | Arm/Unaligned.c\r | |
| 703f1d09 | 473 | Math64.c | RVCT \r |
| 4b5f371b | 474 | \r |
| 475 | Arm/SwitchStack.asm | RVCT\r | |
| 476 | Arm/SetJumpLongJump.asm | RVCT\r | |
| 477 | Arm/DisableInterrupts.asm | RVCT\r | |
| 478 | Arm/EnableInterrupts.asm | RVCT\r | |
| 479 | Arm/GetInterruptsState.asm | RVCT\r | |
| 480 | Arm/CpuPause.asm | RVCT\r | |
| 703f1d09 | 481 | Arm/CpuBreakpoint.asm | RVCT\r |
| 8c1e7951 | 482 | Arm/MemoryFence.asm | RVCT\r |
| 4b5f371b | 483 | \r |
| 703f1d09 | 484 | Arm/Math64.S | GCC\r |
| 08068159 | 485 | Arm/SwitchStack.S | GCC\r |
| 4b5f371b | 486 | Arm/EnableInterrupts.S | GCC\r |
| 487 | Arm/DisableInterrupts.S | GCC\r | |
| 7f22d351 | 488 | Arm/GetInterruptsState.S | GCC\r |
| 4b5f371b | 489 | Arm/SetJumpLongJump.S | GCC\r |
| 490 | Arm/CpuBreakpoint.S | GCC\r | |
| 8c1e7951 | 491 | Arm/MemoryFence.S | GCC\r |
| 4b5f371b | 492 | \r |
| 807e2604 HL |
493 | [Sources.AARCH64]\r |
| 494 | Arm/InternalSwitchStack.c\r | |
| 495 | Arm/Unaligned.c\r | |
| 496 | Math64.c\r | |
| 497 | \r | |
| 8c1e7951 | 498 | AArch64/MemoryFence.S | GCC\r |
| 807e2604 HL |
499 | AArch64/SwitchStack.S | GCC\r |
| 500 | AArch64/EnableInterrupts.S | GCC\r | |
| 501 | AArch64/DisableInterrupts.S | GCC\r | |
| 502 | AArch64/GetInterruptsState.S | GCC\r | |
| 503 | AArch64/SetJumpLongJump.S | GCC\r | |
| 504 | AArch64/CpuBreakpoint.S | GCC\r | |
| 505 | \r | |
| e1f414b6 | 506 | [Packages]\r |
| 507 | MdePkg/MdePkg.dec\r | |
| 508 | \r | |
| e1f414b6 | 509 | [LibraryClasses]\r |
| 510 | PcdLib\r | |
| e1f414b6 | 511 | DebugLib\r |
| 512 | BaseMemoryLib\r | |
| 513 | \r | |
| 1081f624 | 514 | [Pcd]\r |
| c92c1790 LG |
515 | gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES\r |
| 516 | gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES\r | |
| 517 | gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES\r | |
| c058d59f | 518 | gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask ## SOMETIMES_CONSUMES\r |
| da03183c LE |
519 | \r |
| 520 | [FeaturePcd]\r | |
| c92c1790 | 521 | gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES\r |