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1 | /** @file\r |
| 2 | Base Library CPU Functions for EBC\r |
| 3 | \r |
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4 | Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r |
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5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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6 | \r |
| 7 | **/\r |
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8 | \r |
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9 | #include "BaseLibInternals.h"\r |
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10 | \r |
| 11 | extern\r |
| 12 | UINT64\r |
| 13 | _break (\r |
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14 | CHAR8 BreakCode\r |
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15 | );\r |
| 16 | \r |
| 17 | /**\r |
| 18 | Generates a breakpoint on the CPU.\r |
| 19 | \r |
| 20 | Generates a breakpoint on the CPU. The breakpoint must be implemented such\r |
| 21 | that code can resume normal execution after the breakpoint.\r |
| 22 | \r |
| 23 | **/\r |
| 24 | VOID\r |
| 25 | EFIAPI\r |
| 26 | CpuBreakpoint (\r |
| 27 | VOID\r |
| 28 | )\r |
| 29 | {\r |
| 30 | _break (3);\r |
| 31 | }\r |
| 32 | \r |
| 33 | /**\r |
| 34 | Used to serialize load and store operations.\r |
| 35 | \r |
| 36 | All loads and stores that proceed calls to this function are guaranteed to be\r |
| 37 | globally visible when this function returns.\r |
| 38 | \r |
| 39 | **/\r |
| 40 | VOID\r |
| 41 | EFIAPI\r |
| 42 | MemoryFence (\r |
| 43 | VOID\r |
| 44 | )\r |
| 45 | {\r |
| 46 | }\r |
| 47 | \r |
| 48 | /**\r |
| 49 | Disables CPU interrupts.\r |
| 50 | \r |
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51 | **/\r |
| 52 | VOID\r |
| 53 | EFIAPI\r |
| 54 | DisableInterrupts (\r |
| 55 | VOID\r |
| 56 | )\r |
| 57 | {\r |
| 58 | ASSERT (FALSE);\r |
| 59 | }\r |
| 60 | \r |
| 61 | /**\r |
| 62 | Enables CPU interrupts.\r |
| 63 | \r |
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64 | **/\r |
| 65 | VOID\r |
| 66 | EFIAPI\r |
| 67 | EnableInterrupts (\r |
| 68 | VOID\r |
| 69 | )\r |
| 70 | {\r |
| 71 | ASSERT (FALSE);\r |
| 72 | }\r |
| 73 | \r |
| 74 | /**\r |
| 75 | Retrieves the current CPU interrupt state.\r |
| 76 | \r |
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77 | Returns TRUE means interrupts are currently enabled. Otherwise,\r |
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78 | returns FALSE.\r |
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79 | \r |
| 80 | @retval TRUE CPU interrupts are enabled.\r |
| 81 | @retval FALSE CPU interrupts are disabled.\r |
| 82 | \r |
| 83 | **/\r |
| 84 | BOOLEAN\r |
| 85 | EFIAPI\r |
| 86 | GetInterruptState (\r |
| 87 | VOID\r |
| 88 | )\r |
| 89 | {\r |
| 90 | ASSERT (FALSE);\r |
| 91 | return FALSE;\r |
| 92 | }\r |
| 93 | \r |
| 94 | /**\r |
| 95 | Enables CPU interrupts for the smallest window required to capture any\r |
| 96 | pending interrupts.\r |
| 97 | \r |
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98 | **/\r |
| 99 | VOID\r |
| 100 | EFIAPI\r |
| 101 | EnableDisableInterrupts (\r |
| 102 | VOID\r |
| 103 | )\r |
| 104 | {\r |
| 105 | EnableInterrupts ();\r |
| 106 | DisableInterrupts ();\r |
| 107 | }\r |
| 108 | \r |
| 109 | /**\r |
| 110 | Requests CPU to pause for a short period of time.\r |
| 111 | \r |
| 112 | Requests CPU to pause for a short period of time. Typically used in MP\r |
| 113 | systems to prevent memory starvation while waiting for a spin lock.\r |
| 114 | \r |
| 115 | **/\r |
| 116 | VOID\r |
| 117 | EFIAPI\r |
| 118 | CpuPause (\r |
| 119 | VOID\r |
| 120 | )\r |
| 121 | {\r |
| 122 | }\r |
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