MdePkg/BaseLib: Support IA32 processors without CLFLUSH
[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / FlushCacheLine.c
CommitLineData
e1f414b6 1/** @file\r
2 AsmFlushCacheLine function\r
3\r
881813d7 4 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
bb817c56 5 This program and the accompanying materials\r
e1f414b6 6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
35a17154 8 http://opensource.org/licenses/bsd-license.php.\r
e1f414b6 9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
1efcc4ae 15\r
f734a10a 16\r
e1f414b6 17\r
42eedea9 18/**\r
19 Flushes a cache line from all the instruction and data caches within the\r
20 coherency domain of the CPU.\r
21\r
22 Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
030cd1a2 23 This function is only available on IA-32 and x64.\r
42eedea9 24\r
25 @param LinearAddress The address of the cache line to flush. If the CPU is\r
26 in a physical addressing mode, then LinearAddress is a\r
27 physical address. If the CPU is in a virtual\r
28 addressing mode, then LinearAddress is a virtual\r
29 address.\r
30\r
31 @return LinearAddress\r
32**/\r
e1f414b6 33VOID *\r
34EFIAPI\r
35AsmFlushCacheLine (\r
36 IN VOID *LinearAddress\r
37 )\r
38{\r
881813d7
MK
39 //\r
40 // If the CPU does not support CLFLUSH instruction, \r
41 // then promote flush range to flush entire cache.\r
42 //\r
e1f414b6 43 _asm {\r
881813d7
MK
44 mov eax, 1\r
45 cpuid\r
46 test edx, BIT19\r
47 jz NoClflush\r
48 mov eax, [esp + 4]\r
e1f414b6 49 clflush [eax]\r
881813d7
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50 jmp Done\r
51NoClflush:\r
52 wbinvd\r
53Done:\r
e1f414b6 54 }\r
881813d7
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55 \r
56 return LinearAddress;\r
e1f414b6 57}\r
58\r