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c1d82295 JJ |
1 | ;------------------------------------------------------------------------------\r |
2 | ;\r | |
3 | ; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 4 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
c1d82295 JJ |
5 | ;\r |
6 | ; Module Name:\r | |
7 | ;\r | |
8 | ; DisableCache.Asm\r | |
9 | ;\r | |
10 | ; Abstract:\r | |
11 | ;\r | |
12 | ; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r | |
13 | ; WBINVD instruction.\r | |
14 | ;\r | |
15 | ; Notes:\r | |
16 | ;\r | |
17 | ;------------------------------------------------------------------------------\r | |
18 | \r | |
19 | DEFAULT REL\r | |
20 | SECTION .text\r | |
21 | \r | |
22 | ;------------------------------------------------------------------------------\r | |
23 | ; VOID\r | |
24 | ; EFIAPI\r | |
25 | ; AsmDisableCache (\r | |
26 | ; VOID\r | |
27 | ; );\r | |
28 | ;------------------------------------------------------------------------------\r | |
29 | global ASM_PFX(AsmDisableCache)\r | |
30 | ASM_PFX(AsmDisableCache):\r | |
31 | mov rax, cr0\r | |
32 | bts rax, 30\r | |
33 | btr rax, 29\r | |
34 | mov cr0, rax\r | |
35 | wbinvd\r | |
36 | ret\r | |
37 | \r |