projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a91d8309 JJ |
1 | ;------------------------------------------------------------------------------\r |
| 2 | ;\r | |
| 3 | ; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r | |
| 9344f092 | 4 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| a91d8309 JJ |
5 | ;\r |
| 6 | ; Module Name:\r | |
| 7 | ;\r | |
| 8 | ; EnableCache.Asm\r | |
| 9 | ;\r | |
| 10 | ; Abstract:\r | |
| 11 | ;\r | |
| 12 | ; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear\r | |
| 13 | ; the NW bit of CR0 to 0\r | |
| 14 | ;\r | |
| 15 | ; Notes:\r | |
| 16 | ;\r | |
| 17 | ;------------------------------------------------------------------------------\r | |
| 18 | \r | |
| 19 | DEFAULT REL\r | |
| 20 | SECTION .text\r | |
| 21 | \r | |
| 22 | ;------------------------------------------------------------------------------\r | |
| 23 | ; VOID\r | |
| 24 | ; EFIAPI\r | |
| 25 | ; AsmEnableCache (\r | |
| 26 | ; VOID\r | |
| 27 | ; );\r | |
| 28 | ;------------------------------------------------------------------------------\r | |
| 29 | global ASM_PFX(AsmEnableCache)\r | |
| 30 | ASM_PFX(AsmEnableCache):\r | |
| 31 | wbinvd\r | |
| 32 | mov rax, cr0\r | |
| 33 | btr rax, 29\r | |
| 34 | btr rax, 30\r | |
| 35 | mov cr0, rax\r | |
| 36 | ret\r | |
| 37 | \r |