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878ddf1f | 1 | ;------------------------------------------------------------------------------\r |
2 | ;\r | |
3 | ; Copyright (c) 2006, Intel Corporation\r | |
4 | ; All rights reserved. This program and the accompanying materials\r | |
5 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
6 | ; which accompanies this distribution. The full text of the license may be found at\r | |
7 | ; http://opensource.org/licenses/bsd-license.php\r | |
8 | ;\r | |
9 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | ;\r | |
12 | ; Module Name:\r | |
13 | ;\r | |
14 | ; Thunk.asm\r | |
15 | ;\r | |
16 | ; Abstract:\r | |
17 | ;\r | |
18 | ; Real mode thunk\r | |
19 | ;\r | |
20 | ;------------------------------------------------------------------------------\r | |
21 | \r | |
22 | .data\r | |
23 | \r | |
24 | NullSegSel DQ 0\r | |
25 | _16CsSegSel LABEL QWORD\r | |
26 | DW -1\r | |
27 | DW 0\r | |
28 | DB 0\r | |
29 | DB 9bh\r | |
30 | DB 8fh ; 16-bit segment\r | |
31 | DB 0\r | |
32 | _16BitDsSel LABEL QWORD\r | |
33 | DW -1\r | |
34 | DW 0\r | |
35 | DB 0\r | |
36 | DB 93h\r | |
37 | DB 8fh ; 16-bit segment\r | |
38 | DB 0\r | |
39 | GdtEnd LABEL QWORD\r | |
40 | \r | |
41 | .const\r | |
42 | \r | |
43 | _16Gdtr LABEL FWORD\r | |
44 | DW offset GdtEnd - offset NullSegSel - 1\r | |
45 | DQ offset NullSegSel\r | |
46 | \r | |
47 | _16Idtr FWORD (1 SHL 10) - 1\r | |
48 | \r | |
49 | .code\r | |
50 | \r | |
51 | IA32_REGS STRUC 4t\r | |
52 | _EDI DD ?\r | |
53 | _ESI DD ?\r | |
54 | _EBP DD ?\r | |
55 | _ESP DD ?\r | |
56 | _EBX DD ?\r | |
57 | _EDX DD ?\r | |
58 | _ECX DD ?\r | |
59 | _EAX DD ?\r | |
60 | _DS DW ?\r | |
61 | _ES DW ?\r | |
62 | _FS DW ?\r | |
63 | _GS DW ?\r | |
64 | _RFLAGS DQ ?\r | |
65 | _EIP DD ?\r | |
66 | _CS DW ?\r | |
67 | _SS DW ?\r | |
68 | IA32_REGS ENDS\r | |
69 | \r | |
70 | InternalAsmThunk16 PROC USES rbp rbx rsi rdi r12 r13 r14 r15\r | |
71 | mov eax, ds\r | |
72 | push rax\r | |
73 | mov eax, es\r | |
74 | push rax\r | |
75 | push fs\r | |
76 | push gs\r | |
77 | mov rsi, rcx ; rsi <- RegSet\r | |
78 | push sizeof (IA32_REGS)\r | |
79 | pop rcx\r | |
80 | movzx r8, (IA32_REGS ptr [rsi])._SS\r | |
81 | xor rdi, rdi\r | |
82 | mov edi, (IA32_REGS ptr [rsi])._ESP\r | |
83 | sub rdi, rcx ; reserve space on realmode stack\r | |
84 | push rdi ; save stack offset\r | |
85 | imul rax, r8, 16\r | |
86 | add rdi, rax ; rdi <- linear address of 16-bit stack\r | |
87 | rep movsb ; copy RegSet\r | |
88 | mov rsi, r8 ; si <- 16-bit stack segment\r | |
89 | pop rbx ; rbx <- 16-bit stack offset\r | |
90 | mov rdi, rdx ; rdi <- realmode patch\r | |
91 | lea eax, @BackToThunk ; rax <- address to back from real mode\r | |
92 | push rax ; use in a far return\r | |
93 | mov eax, cs\r | |
94 | mov [rsp + 4], eax ; save CS\r | |
95 | lea eax, @16Return ; thus @Return must < 4GB\r | |
96 | stosd ; set ret address offset\r | |
97 | xor eax, eax\r | |
98 | stosw ; set ret CS base to 0\r | |
99 | mov eax, esp\r | |
100 | stosd ; rsp must < 4GB\r | |
101 | mov eax, ss\r | |
102 | stosd\r | |
103 | mov rax, cr0\r | |
104 | mov ecx, eax ; ecx <- CR0\r | |
105 | and ecx, 7ffffffeh ; clear PE, PG bits\r | |
106 | stosd\r | |
107 | mov rax, cr4\r | |
108 | mov ebp, eax\r | |
109 | and ebp, 300h ; clear all but PCE and OSFXSR bits\r | |
110 | stosd\r | |
111 | sidt fword ptr [rsp + 70h] ; use parameter space to save IDTR\r | |
112 | sgdt fword ptr [rdi]\r | |
113 | lea edi, _16Idtr\r | |
114 | lea eax, @16Start ; rax <- seg:offset of @16Start\r | |
115 | push rax\r | |
116 | mov dword ptr [rsp + 4], 8\r | |
117 | push 10h\r | |
118 | pop rax ; rax <- 10h as dataseg selector\r | |
119 | lgdt _16Gdtr\r | |
120 | retf\r | |
121 | @16Start: ; 16-bit starts here\r | |
122 | mov ss, eax ; set SS to be a 16-bit segment\r | |
123 | mov cr0, rcx ; disable protected mode\r | |
124 | mov cr4, rbp\r | |
125 | DB 66h\r | |
126 | mov ecx, 0c0000080h\r | |
127 | rdmsr\r | |
128 | and ah, NOT 1 ; clear LME\r | |
129 | wrmsr\r | |
130 | mov ss, esi ; set up 16-bit stack\r | |
131 | mov sp, bx ; mov esp, ebx actually\r | |
132 | lidt fword ptr [edi]\r | |
133 | DB 66h, 61h ; popad\r | |
134 | DB 1fh ; pop ds\r | |
135 | DB 7 ; pop es\r | |
136 | pop fs\r | |
137 | pop gs\r | |
138 | add sp, 8 ; skip _RFLAGS\r | |
139 | DB 66h\r | |
140 | retf ; transfer control to 16-bit code\r | |
141 | @16Return:\r | |
142 | DB 66h\r | |
143 | push 0 ; high order 32 bits of rflags\r | |
144 | pushf ; pushfd actually\r | |
145 | push gs\r | |
146 | push fs\r | |
147 | DB 6 ; push es\r | |
148 | DB 1eh ; push ds\r | |
149 | DB 66h, 60h ; pushad\r | |
150 | DB 67h, 66h, 0c5h, 74h, 24h, 30h ; lds esi, [esp + 12*4]\r | |
151 | DB 66h\r | |
152 | mov eax, [esi + 12]\r | |
153 | mov cr4, rax ; restore CR4\r | |
154 | DB 66h\r | |
155 | lgdt fword ptr [esi + 16]\r | |
156 | DB 66h\r | |
157 | mov ecx, 0c0000080h\r | |
158 | rdmsr\r | |
159 | or ah, 1 ; set LME\r | |
160 | wrmsr\r | |
161 | DB 66h\r | |
162 | mov eax, [esi + 8]\r | |
163 | mov cr0, rax ; restore CR0\r | |
164 | xor ax, ax ; xor eax, eax actually\r | |
165 | mov eax, ss\r | |
166 | mov dword ptr (IA32_REGS ptr [esp])._SS, eax\r | |
167 | shl ax, 4 ; shl eax, 4 actually\r | |
168 | add ax, sp ; add eax, esp actually\r | |
169 | add sp, sizeof (IA32_REGS) ; add esp, sizeof (IA32_REGS)\r | |
170 | DB 66h\r | |
171 | mov dword ptr (IA32_REGS ptr [esp - sizeof (IA32_REGS)])._ESP, esp\r | |
172 | DB 66h\r | |
173 | lss esp, fword ptr [esi] ; restore protected mode stack\r | |
174 | DB 66h\r | |
175 | retf ; go back to protected mode\r | |
176 | @BackToThunk:\r | |
177 | lidt fword ptr [rsp + 68h] ; restore protected mode IDTR\r | |
178 | shl rax, 32\r | |
179 | shr rax, 32 ; clear high order 32 bits of RAX\r | |
180 | pop gs\r | |
181 | pop fs\r | |
182 | pop rcx\r | |
183 | mov es, ecx\r | |
184 | pop rcx\r | |
185 | mov ds, ecx\r | |
186 | ret\r | |
187 | InternalAsmThunk16 ENDP\r | |
188 | \r | |
189 | END\r |