878ddf1f |
1 | /** @file\r |
2 | IA-32/x64 specific functions.\r |
3 | \r |
4 | Copyright (c) 2006, Intel Corporation<BR>\r |
5 | All rights reserved. This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r |
8 | http://opensource.org/licenses/bsd-license.php\r |
9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
12 | \r |
13 | Module Name: x86LowLevel.c\r |
14 | \r |
15 | **/\r |
16 | \r |
17 | #include "BaseLibInternals.h"\r |
18 | \r |
19 | //\r |
20 | // Bit-wise MSR operations\r |
21 | //\r |
22 | \r |
23 | /**\r |
24 | Reads a 64-bit MSR, performs a bitwise inclusive OR on the lower 32-bits, and\r |
25 | writes the result back to the 64-bit MSR.\r |
26 | \r |
27 | Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r |
28 | between the lower 32-bits of the read result and the value specified by\r |
29 | OrData, and writes the result to the 64-bit MSR specified by Index. The lower\r |
30 | 32-bits of the value written to the MSR is returned. No parameter checking is\r |
31 | performed on Index or OrData, and some of these may cause CPU exceptions. The\r |
32 | caller must either guarantee that Index and OrData are valid, or the caller\r |
33 | must establish proper exception handlers. This function is only available on\r |
34 | IA-32 and X64.\r |
35 | \r |
36 | @param Index The 32-bit MSR index to write.\r |
37 | @param OrData The value to OR with the read value from the MSR.\r |
38 | \r |
39 | @return The lower 32-bit value written to the MSR.\r |
40 | \r |
41 | **/\r |
42 | UINT32\r |
43 | EFIAPI\r |
44 | AsmMsrOr32 (\r |
45 | IN UINT32 Index,\r |
46 | IN UINT32 OrData\r |
47 | )\r |
48 | {\r |
49 | return (UINT32)AsmMsrOr64 (Index, OrData);\r |
50 | }\r |
51 | \r |
52 | /**\r |
53 | Reads a 64-bit MSR, performs a bitwise AND on the lower 32-bits, and writes\r |
54 | the result back to the 64-bit MSR.\r |
55 | \r |
56 | Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r |
57 | lower 32-bits of the read result and the value specified by AndData, and\r |
58 | writes the result to the 64-bit MSR specified by Index. The lower 32-bits of\r |
59 | the value written to the MSR is returned. No parameter checking is performed\r |
60 | on Index or AndData, and some of these may cause CPU exceptions. The caller\r |
61 | must either guarantee that Index and AndData are valid, or the caller must\r |
62 | establish proper exception handlers. This function is only available on IA-32\r |
63 | and X64.\r |
64 | \r |
65 | @param Index The 32-bit MSR index to write.\r |
66 | @param AndData The value to AND with the read value from the MSR.\r |
67 | \r |
68 | @return The lower 32-bit value written to the MSR.\r |
69 | \r |
70 | **/\r |
71 | UINT32\r |
72 | EFIAPI\r |
73 | AsmMsrAnd32 (\r |
74 | IN UINT32 Index,\r |
75 | IN UINT32 AndData\r |
76 | )\r |
77 | {\r |
78 | return (UINT32)AsmMsrAnd64 (Index, AndData);\r |
79 | }\r |
80 | \r |
81 | /**\r |
82 | Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive OR\r |
83 | on the lower 32-bits, and writes the result back to the 64-bit MSR.\r |
84 | \r |
85 | Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r |
86 | lower 32-bits of the read result and the value specified by AndData\r |
87 | preserving the upper 32-bits, performs a bitwise inclusive OR between the\r |
88 | result of the AND operation and the value specified by OrData, and writes the\r |
89 | result to the 64-bit MSR specified by Address. The lower 32-bits of the value\r |
90 | written to the MSR is returned. No parameter checking is performed on Index,\r |
91 | AndData, or OrData, and some of these may cause CPU exceptions. The caller\r |
92 | must either guarantee that Index, AndData, and OrData are valid, or the\r |
93 | caller must establish proper exception handlers. This function is only\r |
94 | available on IA-32 and X64.\r |
95 | \r |
96 | @param Index The 32-bit MSR index to write.\r |
97 | @param AndData The value to AND with the read value from the MSR.\r |
98 | @param OrData The value to OR with the result of the AND operation.\r |
99 | \r |
100 | @return The lower 32-bit value written to the MSR.\r |
101 | \r |
102 | **/\r |
103 | UINT32\r |
104 | EFIAPI\r |
105 | AsmMsrAndThenOr32 (\r |
106 | IN UINT32 Index,\r |
107 | IN UINT32 AndData,\r |
108 | IN UINT32 OrData\r |
109 | )\r |
110 | {\r |
111 | return (UINT32)AsmMsrAndThenOr64 (Index, AndData, OrData);\r |
112 | }\r |
113 | \r |
114 | /**\r |
115 | Reads a bit field of an MSR.\r |
116 | \r |
117 | Reads the bit field in the lower 32-bits of a 64-bit MSR. The bit field is\r |
118 | specified by the StartBit and the EndBit. The value of the bit field is\r |
119 | returned. The caller must either guarantee that Index is valid, or the caller\r |
120 | must set up exception handlers to catch the exceptions. This function is only\r |
121 | available on IA-32 and X64.\r |
122 | \r |
123 | If StartBit is greater than 31, then ASSERT().\r |
124 | If EndBit is greater than 31, then ASSERT().\r |
125 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
126 | \r |
127 | @param Index The 32-bit MSR index to read.\r |
128 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
129 | Range 0..31.\r |
130 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
131 | Range 0..31.\r |
132 | \r |
133 | @return The bit field read from the MSR.\r |
134 | \r |
135 | **/\r |
136 | UINT32\r |
137 | EFIAPI\r |
138 | AsmMsrBitFieldRead32 (\r |
139 | IN UINT32 Index,\r |
140 | IN UINTN StartBit,\r |
141 | IN UINTN EndBit\r |
142 | )\r |
143 | {\r |
144 | return BitFieldRead32 (AsmReadMsr32 (Index), StartBit, EndBit);\r |
145 | }\r |
146 | \r |
147 | /**\r |
148 | Writes a bit field to an MSR.\r |
149 | \r |
150 | Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit\r |
151 | field is specified by the StartBit and the EndBit. All other bits in the\r |
152 | destination MSR are preserved. The lower 32-bits of the MSR written is\r |
153 | returned. Extra left bits in Value are stripped. The caller must either\r |
154 | guarantee that Index and the data written is valid, or the caller must set up\r |
155 | exception handlers to catch the exceptions. This function is only available\r |
156 | on IA-32 and X64.\r |
157 | \r |
158 | If StartBit is greater than 31, then ASSERT().\r |
159 | If EndBit is greater than 31, then ASSERT().\r |
160 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
161 | \r |
162 | @param Index The 32-bit MSR index to write.\r |
163 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
164 | Range 0..31.\r |
165 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
166 | Range 0..31.\r |
167 | @param Value New value of the bit field.\r |
168 | \r |
169 | @return The lower 32-bit of the value written to the MSR.\r |
170 | \r |
171 | **/\r |
172 | UINT32\r |
173 | EFIAPI\r |
174 | AsmMsrBitFieldWrite32 (\r |
175 | IN UINT32 Index,\r |
176 | IN UINTN StartBit,\r |
177 | IN UINTN EndBit,\r |
178 | IN UINT32 Value\r |
179 | )\r |
180 | {\r |
181 | ASSERT (EndBit < sizeof (Value) * 8);\r |
182 | ASSERT (StartBit <= EndBit);\r |
183 | return (UINT32)AsmMsrBitFieldWrite64 (Index, StartBit, EndBit, Value);\r |
184 | }\r |
185 | \r |
186 | /**\r |
187 | Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the\r |
188 | result back to the bit field in the 64-bit MSR.\r |
189 | \r |
190 | Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r |
191 | between the read result and the value specified by OrData, and writes the\r |
192 | result to the 64-bit MSR specified by Index. The lower 32-bits of the value\r |
193 | written to the MSR are returned. Extra left bits in OrData are stripped. The\r |
194 | caller must either guarantee that Index and the data written is valid, or\r |
195 | the caller must set up exception handlers to catch the exceptions. This\r |
196 | function is only available on IA-32 and X64.\r |
197 | \r |
198 | If StartBit is greater than 31, then ASSERT().\r |
199 | If EndBit is greater than 31, then ASSERT().\r |
200 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
201 | \r |
202 | @param Index The 32-bit MSR index to write.\r |
203 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
204 | Range 0..31.\r |
205 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
206 | Range 0..31.\r |
207 | @param OrData The value to OR with the read value from the MSR.\r |
208 | \r |
209 | @return The lower 32-bit of the value written to the MSR.\r |
210 | \r |
211 | **/\r |
212 | UINT32\r |
213 | EFIAPI\r |
214 | AsmMsrBitFieldOr32 (\r |
215 | IN UINT32 Index,\r |
216 | IN UINTN StartBit,\r |
217 | IN UINTN EndBit,\r |
218 | IN UINT32 OrData\r |
219 | )\r |
220 | {\r |
221 | ASSERT (EndBit < sizeof (OrData) * 8);\r |
222 | ASSERT (StartBit <= EndBit);\r |
223 | return (UINT32)AsmMsrBitFieldOr64 (Index, StartBit, EndBit, OrData);\r |
224 | }\r |
225 | \r |
226 | /**\r |
227 | Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the\r |
228 | result back to the bit field in the 64-bit MSR.\r |
229 | \r |
230 | Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r |
231 | read result and the value specified by AndData, and writes the result to the\r |
232 | 64-bit MSR specified by Index. The lower 32-bits of the value written to the\r |
233 | MSR are returned. Extra left bits in AndData are stripped. The caller must\r |
234 | either guarantee that Index and the data written is valid, or the caller must\r |
235 | set up exception handlers to catch the exceptions. This function is only\r |
236 | available on IA-32 and X64.\r |
237 | \r |
238 | If StartBit is greater than 31, then ASSERT().\r |
239 | If EndBit is greater than 31, then ASSERT().\r |
240 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
241 | \r |
242 | @param Index The 32-bit MSR index to write.\r |
243 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
244 | Range 0..31.\r |
245 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
246 | Range 0..31.\r |
247 | @param AndData The value to AND with the read value from the MSR.\r |
248 | \r |
249 | @return The lower 32-bit of the value written to the MSR.\r |
250 | \r |
251 | **/\r |
252 | UINT32\r |
253 | EFIAPI\r |
254 | AsmMsrBitFieldAnd32 (\r |
255 | IN UINT32 Index,\r |
256 | IN UINTN StartBit,\r |
257 | IN UINTN EndBit,\r |
258 | IN UINT32 AndData\r |
259 | )\r |
260 | {\r |
261 | ASSERT (EndBit < sizeof (AndData) * 8);\r |
262 | ASSERT (StartBit <= EndBit);\r |
263 | return (UINT32)AsmMsrBitFieldAnd64 (Index, StartBit, EndBit, AndData);\r |
264 | }\r |
265 | \r |
266 | /**\r |
267 | Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r |
268 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
269 | 64-bit MSR.\r |
270 | \r |
271 | Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a\r |
272 | bitwise inclusive OR between the read result and the value specified by\r |
273 | AndData, and writes the result to the 64-bit MSR specified by Index. The\r |
274 | lower 32-bits of the value written to the MSR are returned. Extra left bits\r |
275 | in both AndData and OrData are stripped. The caller must either guarantee\r |
276 | that Index and the data written is valid, or the caller must set up exception\r |
277 | handlers to catch the exceptions. This function is only available on IA-32\r |
278 | and X64.\r |
279 | \r |
280 | If StartBit is greater than 31, then ASSERT().\r |
281 | If EndBit is greater than 31, then ASSERT().\r |
282 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
283 | \r |
284 | @param Index The 32-bit MSR index to write.\r |
285 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
286 | Range 0..31.\r |
287 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
288 | Range 0..31.\r |
289 | @param AndData The value to AND with the read value from the MSR.\r |
290 | @param OrData The value to OR with the result of the AND operation.\r |
291 | \r |
292 | @return The lower 32-bit of the value written to the MSR.\r |
293 | \r |
294 | **/\r |
295 | UINT32\r |
296 | EFIAPI\r |
297 | AsmMsrBitFieldAndThenOr32 (\r |
298 | IN UINT32 Index,\r |
299 | IN UINTN StartBit,\r |
300 | IN UINTN EndBit,\r |
301 | IN UINT32 AndData,\r |
302 | IN UINT32 OrData\r |
303 | )\r |
304 | {\r |
305 | ASSERT (EndBit < sizeof (AndData) * 8);\r |
306 | ASSERT (StartBit <= EndBit);\r |
307 | return (UINT32)AsmMsrBitFieldAndThenOr64 (\r |
308 | Index,\r |
309 | StartBit,\r |
310 | EndBit,\r |
311 | AndData,\r |
312 | OrData\r |
313 | );\r |
314 | }\r |
315 | \r |
316 | /**\r |
317 | Reads a 64-bit MSR, performs a bitwise inclusive OR, and writes the result\r |
318 | back to the 64-bit MSR.\r |
319 | \r |
320 | Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r |
321 | between the read result and the value specified by OrData, and writes the\r |
322 | result to the 64-bit MSR specified by Index. The value written to the MSR is\r |
323 | returned. No parameter checking is performed on Index or OrData, and some of\r |
324 | these may cause CPU exceptions. The caller must either guarantee that Index\r |
325 | and OrData are valid, or the caller must establish proper exception handlers.\r |
326 | This function is only available on IA-32 and X64.\r |
327 | \r |
328 | @param Index The 32-bit MSR index to write.\r |
329 | @param OrData The value to OR with the read value from the MSR.\r |
330 | \r |
331 | @return The value written back to the MSR.\r |
332 | \r |
333 | **/\r |
334 | UINT64\r |
335 | EFIAPI\r |
336 | AsmMsrOr64 (\r |
337 | IN UINT32 Index,\r |
338 | IN UINT64 OrData\r |
339 | )\r |
340 | {\r |
341 | return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) | OrData);\r |
342 | }\r |
343 | \r |
344 | /**\r |
345 | Reads a 64-bit MSR, performs a bitwise AND, and writes the result back to the\r |
346 | 64-bit MSR.\r |
347 | \r |
348 | Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r |
349 | read result and the value specified by OrData, and writes the result to the\r |
350 | 64-bit MSR specified by Index. The value written to the MSR is returned. No\r |
351 | parameter checking is performed on Index or OrData, and some of these may\r |
352 | cause CPU exceptions. The caller must either guarantee that Index and OrData\r |
353 | are valid, or the caller must establish proper exception handlers. This\r |
354 | function is only available on IA-32 and X64.\r |
355 | \r |
356 | @param Index The 32-bit MSR index to write.\r |
357 | @param AndData The value to AND with the read value from the MSR.\r |
358 | \r |
359 | @return The value written back to the MSR.\r |
360 | \r |
361 | **/\r |
362 | UINT64\r |
363 | EFIAPI\r |
364 | AsmMsrAnd64 (\r |
365 | IN UINT32 Index,\r |
366 | IN UINT64 AndData\r |
367 | )\r |
368 | {\r |
369 | return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) & AndData);\r |
370 | }\r |
371 | \r |
372 | /**\r |
373 | Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive\r |
374 | OR, and writes the result back to the 64-bit MSR.\r |
375 | \r |
376 | Reads the 64-bit MSR specified by Index, performs a bitwise AND between read\r |
377 | result and the value specified by AndData, performs a bitwise inclusive OR\r |
378 | between the result of the AND operation and the value specified by OrData,\r |
379 | and writes the result to the 64-bit MSR specified by Index. The value written\r |
380 | to the MSR is returned. No parameter checking is performed on Index, AndData,\r |
381 | or OrData, and some of these may cause CPU exceptions. The caller must either\r |
382 | guarantee that Index, AndData, and OrData are valid, or the caller must\r |
383 | establish proper exception handlers. This function is only available on IA-32\r |
384 | and X64.\r |
385 | \r |
386 | @param Index The 32-bit MSR index to write.\r |
387 | @param AndData The value to AND with the read value from the MSR.\r |
388 | @param OrData The value to OR with the result of the AND operation.\r |
389 | \r |
390 | @return The value written back to the MSR.\r |
391 | \r |
392 | **/\r |
393 | UINT64\r |
394 | EFIAPI\r |
395 | AsmMsrAndThenOr64 (\r |
396 | IN UINT32 Index,\r |
397 | IN UINT64 AndData,\r |
398 | IN UINT64 OrData\r |
399 | )\r |
400 | {\r |
401 | return AsmWriteMsr64 (Index, (AsmReadMsr64 (Index) & AndData) | OrData);\r |
402 | }\r |
403 | \r |
404 | /**\r |
405 | Reads a bit field of an MSR.\r |
406 | \r |
407 | Reads the bit field in the 64-bit MSR. The bit field is specified by the\r |
408 | StartBit and the EndBit. The value of the bit field is returned. The caller\r |
409 | must either guarantee that Index is valid, or the caller must set up\r |
410 | exception handlers to catch the exceptions. This function is only available\r |
411 | on IA-32 and X64.\r |
412 | \r |
413 | If StartBit is greater than 63, then ASSERT().\r |
414 | If EndBit is greater than 63, then ASSERT().\r |
415 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
416 | \r |
417 | @param Index The 32-bit MSR index to read.\r |
418 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
419 | Range 0..63.\r |
420 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
421 | Range 0..63.\r |
422 | \r |
423 | @return The value written back to the MSR.\r |
424 | \r |
425 | **/\r |
426 | UINT64\r |
427 | EFIAPI\r |
428 | AsmMsrBitFieldRead64 (\r |
429 | IN UINT32 Index,\r |
430 | IN UINTN StartBit,\r |
431 | IN UINTN EndBit\r |
432 | )\r |
433 | {\r |
434 | return BitFieldRead64 (AsmReadMsr64 (Index), StartBit, EndBit);\r |
435 | }\r |
436 | \r |
437 | /**\r |
438 | Writes a bit field to an MSR.\r |
439 | \r |
440 | Writes Value to a bit field in a 64-bit MSR. The bit field is specified by\r |
441 | the StartBit and the EndBit. All other bits in the destination MSR are\r |
442 | preserved. The MSR written is returned. Extra left bits in Value are\r |
443 | stripped. The caller must either guarantee that Index and the data written is\r |
444 | valid, or the caller must set up exception handlers to catch the exceptions.\r |
445 | This function is only available on IA-32 and X64.\r |
446 | \r |
447 | If StartBit is greater than 63, then ASSERT().\r |
448 | If EndBit is greater than 63, then ASSERT().\r |
449 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
450 | \r |
451 | @param Index The 32-bit MSR index to write.\r |
452 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
453 | Range 0..63.\r |
454 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
455 | Range 0..63.\r |
456 | @param Value New value of the bit field.\r |
457 | \r |
458 | @return The value written back to the MSR.\r |
459 | \r |
460 | **/\r |
461 | UINT64\r |
462 | EFIAPI\r |
463 | AsmMsrBitFieldWrite64 (\r |
464 | IN UINT32 Index,\r |
465 | IN UINTN StartBit,\r |
466 | IN UINTN EndBit,\r |
467 | IN UINT64 Value\r |
468 | )\r |
469 | {\r |
470 | return AsmWriteMsr64 (\r |
471 | Index,\r |
472 | BitFieldWrite64 (AsmReadMsr64 (Index), StartBit, EndBit, Value)\r |
473 | );\r |
474 | }\r |
475 | \r |
476 | /**\r |
477 | Reads a bit field in a 64-bit MSR, performs a bitwise inclusive OR, and\r |
478 | writes the result back to the bit field in the 64-bit MSR.\r |
479 | \r |
480 | Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR\r |
481 | between the read result and the value specified by OrData, and writes the\r |
482 | result to the 64-bit MSR specified by Index. The value written to the MSR is\r |
483 | returned. Extra left bits in OrData are stripped. The caller must either\r |
484 | guarantee that Index and the data written is valid, or the caller must set up\r |
485 | exception handlers to catch the exceptions. This function is only available\r |
486 | on IA-32 and X64.\r |
487 | \r |
488 | If StartBit is greater than 63, then ASSERT().\r |
489 | If EndBit is greater than 63, then ASSERT().\r |
490 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
491 | \r |
492 | @param Index The 32-bit MSR index to write.\r |
493 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
494 | Range 0..63.\r |
495 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
496 | Range 0..63.\r |
497 | @param OrData The value to OR with the read value from the bit field.\r |
498 | \r |
499 | @return The value written back to the MSR.\r |
500 | \r |
501 | **/\r |
502 | UINT64\r |
503 | EFIAPI\r |
504 | AsmMsrBitFieldOr64 (\r |
505 | IN UINT32 Index,\r |
506 | IN UINTN StartBit,\r |
507 | IN UINTN EndBit,\r |
508 | IN UINT64 OrData\r |
509 | )\r |
510 | {\r |
511 | return AsmWriteMsr64 (\r |
512 | Index,\r |
513 | BitFieldOr64 (AsmReadMsr64 (Index), StartBit, EndBit, OrData)\r |
514 | );\r |
515 | }\r |
516 | \r |
517 | /**\r |
518 | Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the\r |
519 | result back to the bit field in the 64-bit MSR.\r |
520 | \r |
521 | Reads the 64-bit MSR specified by Index, performs a bitwise AND between the\r |
522 | read result and the value specified by AndData, and writes the result to the\r |
523 | 64-bit MSR specified by Index. The value written to the MSR is returned.\r |
524 | Extra left bits in AndData are stripped. The caller must either guarantee\r |
525 | that Index and the data written is valid, or the caller must set up exception\r |
526 | handlers to catch the exceptions. This function is only available on IA-32\r |
527 | and X64.\r |
528 | \r |
529 | If StartBit is greater than 63, then ASSERT().\r |
530 | If EndBit is greater than 63, then ASSERT().\r |
531 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
532 | \r |
533 | @param Index The 32-bit MSR index to write.\r |
534 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
535 | Range 0..63.\r |
536 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
537 | Range 0..63.\r |
538 | @param AndData The value to AND with the read value from the bit field.\r |
539 | \r |
540 | @return The value written back to the MSR.\r |
541 | \r |
542 | **/\r |
543 | UINT64\r |
544 | EFIAPI\r |
545 | AsmMsrBitFieldAnd64 (\r |
546 | IN UINT32 Index,\r |
547 | IN UINTN StartBit,\r |
548 | IN UINTN EndBit,\r |
549 | IN UINT64 AndData\r |
550 | )\r |
551 | {\r |
552 | return AsmWriteMsr64 (\r |
553 | Index,\r |
554 | BitFieldAnd64 (AsmReadMsr64 (Index), StartBit, EndBit, AndData)\r |
555 | );\r |
556 | }\r |
557 | \r |
558 | /**\r |
559 | Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r |
560 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
561 | 64-bit MSR.\r |
562 | \r |
563 | Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by\r |
564 | a bitwise inclusive OR between the read result and the value specified by\r |
565 | AndData, and writes the result to the 64-bit MSR specified by Index. The\r |
566 | value written to the MSR is returned. Extra left bits in both AndData and\r |
567 | OrData are stripped. The caller must either guarantee that Index and the data\r |
568 | written is valid, or the caller must set up exception handlers to catch the\r |
569 | exceptions. This function is only available on IA-32 and X64.\r |
570 | \r |
571 | If StartBit is greater than 63, then ASSERT().\r |
572 | If EndBit is greater than 63, then ASSERT().\r |
573 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
574 | \r |
575 | @param Index The 32-bit MSR index to write.\r |
576 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
577 | Range 0..63.\r |
578 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
579 | Range 0..63.\r |
580 | @param AndData The value to AND with the read value from the bit field.\r |
581 | @param OrData The value to OR with the result of the AND operation.\r |
582 | \r |
583 | @return The value written back to the MSR.\r |
584 | \r |
585 | **/\r |
586 | UINT64\r |
587 | EFIAPI\r |
588 | AsmMsrBitFieldAndThenOr64 (\r |
589 | IN UINT32 Index,\r |
590 | IN UINTN StartBit,\r |
591 | IN UINTN EndBit,\r |
592 | IN UINT64 AndData,\r |
593 | IN UINT64 OrData\r |
594 | )\r |
595 | {\r |
596 | return AsmWriteMsr64 (\r |
597 | Index,\r |
598 | BitFieldAndThenOr64 (\r |
599 | AsmReadMsr64 (Index),\r |
600 | StartBit,\r |
601 | EndBit,\r |
602 | AndData,\r |
603 | OrData\r |
604 | )\r |
605 | );\r |
606 | }\r |
607 | \r |
608 | //\r |
609 | // Base Library CPU Functions\r |
610 | //\r |
611 | \r |
612 | /**\r |
613 | Retrieves the current CPU interrupt state.\r |
614 | \r |
615 | Retrieves the current CPU interrupt state. Returns TRUE is interrupts are\r |
616 | currently enabled. Otherwise returns FALSE.\r |
617 | \r |
618 | @retval TRUE CPU interrupts are enabled.\r |
619 | @retval FALSE CPU interrupts are disabled.\r |
620 | \r |
621 | **/\r |
622 | BOOLEAN\r |
623 | EFIAPI\r |
624 | GetInterruptState (\r |
625 | VOID\r |
626 | )\r |
627 | {\r |
628 | IA32_EFLAGS32 EFlags;\r |
629 | \r |
630 | EFlags.UintN = AsmReadEflags ();\r |
631 | return (BOOLEAN)(EFlags.Bits.IF == 1);\r |
632 | }\r |
633 | \r |
634 | //\r |
635 | // Ia32 and x64 specific functions\r |
636 | //\r |
637 | \r |
638 | /**\r |
639 | Reads the current Global Descriptor Table Register(GDTR) descriptor.\r |
640 | \r |
641 | Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r |
642 | function is only available on IA-32 and X64.\r |
643 | \r |
644 | If Gdtr is NULL, then ASSERT().\r |
645 | \r |
646 | @param Gdtr Pointer to a GDTR descriptor.\r |
647 | \r |
648 | **/\r |
649 | VOID\r |
650 | EFIAPI\r |
651 | AsmReadGdtr (\r |
652 | OUT IA32_DESCRIPTOR *Gdtr\r |
653 | )\r |
654 | {\r |
655 | ASSERT (Gdtr != NULL);\r |
656 | InternalX86ReadGdtr (Gdtr);\r |
657 | }\r |
658 | \r |
659 | /**\r |
660 | Writes the current Global Descriptor Table Register (GDTR) descriptor.\r |
661 | \r |
662 | Writes and the current GDTR descriptor specified by Gdtr. This function is\r |
663 | only available on IA-32 and X64.\r |
664 | \r |
665 | If Gdtr is NULL, then ASSERT().\r |
666 | \r |
667 | @param Gdtr Pointer to a GDTR descriptor.\r |
668 | \r |
669 | **/\r |
670 | VOID\r |
671 | EFIAPI\r |
672 | AsmWriteGdtr (\r |
673 | IN CONST IA32_DESCRIPTOR *Gdtr\r |
674 | )\r |
675 | {\r |
676 | ASSERT (Gdtr != NULL);\r |
677 | InternalX86WriteGdtr (Gdtr);\r |
678 | }\r |
679 | \r |
680 | /**\r |
681 | Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r |
682 | \r |
683 | Reads and returns the current IDTR descriptor and returns it in Idtr. This\r |
684 | function is only available on IA-32 and X64.\r |
685 | \r |
686 | If Idtr is NULL, then ASSERT().\r |
687 | \r |
688 | @param Idtr Pointer to a IDTR descriptor.\r |
689 | \r |
690 | **/\r |
691 | VOID\r |
692 | EFIAPI\r |
693 | AsmReadIdtr (\r |
694 | OUT IA32_DESCRIPTOR *Idtr\r |
695 | )\r |
696 | {\r |
697 | ASSERT (Idtr != NULL);\r |
698 | InternalX86ReadIdtr (Idtr);\r |
699 | }\r |
700 | \r |
701 | /**\r |
702 | Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.\r |
703 | \r |
704 | Writes the current IDTR descriptor and returns it in Idtr. This function is\r |
705 | only available on IA-32 and X64.\r |
706 | \r |
707 | If Idtr is NULL, then ASSERT().\r |
708 | \r |
709 | @param Idtr Pointer to a IDTR descriptor.\r |
710 | \r |
711 | **/\r |
712 | VOID\r |
713 | EFIAPI\r |
714 | AsmWriteIdtr (\r |
715 | IN CONST IA32_DESCRIPTOR *Idtr\r |
716 | )\r |
717 | {\r |
718 | ASSERT (Idtr != NULL);\r |
719 | InternalX86WriteIdtr (Idtr);\r |
720 | }\r |
721 | \r |
722 | /**\r |
723 | Save the current floating point/SSE/SSE2 context to a buffer.\r |
724 | \r |
725 | Saves the current floating point/SSE/SSE2 state to the buffer specified by\r |
726 | Buffer. Buffer must be aligned on a 16-byte boundary. This function is only\r |
727 | available on IA-32 and X64.\r |
728 | \r |
729 | If Buffer is NULL, then ASSERT().\r |
730 | If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r |
731 | \r |
732 | @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.\r |
733 | \r |
734 | **/\r |
735 | VOID\r |
736 | EFIAPI\r |
737 | AsmFxSave (\r |
738 | OUT IA32_FX_BUFFER *Buffer\r |
739 | )\r |
740 | {\r |
741 | ASSERT (Buffer != NULL);\r |
742 | ASSERT (((UINTN)Buffer & 0xf) == 0);\r |
743 | InternalX86FxSave (Buffer);\r |
744 | }\r |
745 | \r |
746 | /**\r |
747 | Restores the current floating point/SSE/SSE2 context from a buffer.\r |
748 | \r |
749 | Restores the current floating point/SSE/SSE2 state from the buffer specified\r |
750 | by Buffer. Buffer must be aligned on a 16-byte boundary. This function is\r |
751 | only available on IA-32 and X64.\r |
752 | \r |
753 | If Buffer is NULL, then ASSERT().\r |
754 | If Buffer is not aligned on a 16-byte boundary, then ASSERT().\r |
755 | If Buffer was not saved with AsmFxSave(), then ASSERT().\r |
756 | \r |
757 | @param Buffer Pointer to a buffer to save the floating point/SSE/SSE2 context.\r |
758 | \r |
759 | **/\r |
760 | VOID\r |
761 | EFIAPI\r |
762 | AsmFxRestore (\r |
763 | IN CONST IA32_FX_BUFFER *Buffer\r |
764 | )\r |
765 | {\r |
766 | ASSERT (Buffer != NULL);\r |
767 | ASSERT (((UINTN)Buffer & 0xf) == 0);\r |
768 | InternalX86FxRestore (Buffer);\r |
769 | }\r |
770 | \r |
771 | /**\r |
772 | Enables the 32-bit paging mode on the CPU.\r |
773 | \r |
774 | Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r |
775 | must be properly initialized prior to calling this service. This function\r |
776 | assumes the current execution mode is 32-bit protected mode. This function is\r |
777 | only available on IA-32. After the 32-bit paging mode is enabled, control is\r |
778 | transferred to the function specified by EntryPoint using the new stack\r |
779 | specified by NewStack and passing in the parameters specified by Context1 and\r |
780 | Context2. Context1 and Context2 are optional and may be NULL. The function\r |
781 | EntryPoint must never return.\r |
782 | \r |
783 | If the current execution mode is not 32-bit protected mode, then ASSERT().\r |
784 | If EntryPoint is NULL, then ASSERT().\r |
785 | If NewStack is NULL, then ASSERT().\r |
786 | \r |
787 | There are a number of constraints that must be followed before calling this\r |
788 | function:\r |
789 | 1) Interrupts must be disabled.\r |
790 | 2) The caller must be in 32-bit protected mode with flat descriptors. This\r |
791 | means all descriptors must have a base of 0 and a limit of 4GB.\r |
792 | 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r |
793 | descriptors.\r |
794 | 4) CR3 must point to valid page tables that will be used once the transition\r |
795 | is complete, and those page tables must guarantee that the pages for this\r |
796 | function and the stack are identity mapped.\r |
797 | \r |
798 | @param EntryPoint A pointer to function to call with the new stack after\r |
799 | paging is enabled.\r |
800 | @param Context1 A pointer to the context to pass into the EntryPoint\r |
801 | function as the first parameter after paging is enabled.\r |
802 | @param Context2 A pointer to the context to pass into the EntryPoint\r |
803 | function as the second parameter after paging is enabled.\r |
804 | @param NewStack A pointer to the new stack to use for the EntryPoint\r |
805 | function after paging is enabled.\r |
806 | \r |
807 | **/\r |
808 | VOID\r |
809 | EFIAPI\r |
810 | AsmEnablePaging32 (\r |
811 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r |
812 | IN VOID *Context1, OPTIONAL\r |
813 | IN VOID *Context2, OPTIONAL\r |
814 | IN VOID *NewStack\r |
815 | )\r |
816 | {\r |
817 | ASSERT (EntryPoint != NULL);\r |
818 | ASSERT (NewStack != NULL);\r |
819 | InternalX86EnablePaging32 (EntryPoint, Context1, Context2, NewStack);\r |
820 | }\r |
821 | \r |
822 | /**\r |
823 | Disables the 32-bit paging mode on the CPU.\r |
824 | \r |
825 | Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r |
826 | mode. This function assumes the current execution mode is 32-paged protected\r |
827 | mode. This function is only available on IA-32. After the 32-bit paging mode\r |
828 | is disabled, control is transferred to the function specified by EntryPoint\r |
829 | using the new stack specified by NewStack and passing in the parameters\r |
830 | specified by Context1 and Context2. Context1 and Context2 are optional and\r |
831 | may be NULL. The function EntryPoint must never return.\r |
832 | \r |
833 | If the current execution mode is not 32-bit paged mode, then ASSERT().\r |
834 | If EntryPoint is NULL, then ASSERT().\r |
835 | If NewStack is NULL, then ASSERT().\r |
836 | \r |
837 | There are a number of constraints that must be followed before calling this\r |
838 | function:\r |
839 | 1) Interrupts must be disabled.\r |
840 | 2) The caller must be in 32-bit paged mode.\r |
841 | 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r |
842 | 4) CR3 must point to valid page tables that guarantee that the pages for\r |
843 | this function and the stack are identity mapped.\r |
844 | \r |
845 | @param EntryPoint A pointer to function to call with the new stack after\r |
846 | paging is disabled.\r |
847 | @param Context1 A pointer to the context to pass into the EntryPoint\r |
848 | function as the first parameter after paging is disabled.\r |
849 | @param Context2 A pointer to the context to pass into the EntryPoint\r |
850 | function as the second parameter after paging is\r |
851 | disabled.\r |
852 | @param NewStack A pointer to the new stack to use for the EntryPoint\r |
853 | function after paging is disabled.\r |
854 | \r |
855 | **/\r |
856 | VOID\r |
857 | EFIAPI\r |
858 | AsmDisablePaging32 (\r |
859 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r |
860 | IN VOID *Context1, OPTIONAL\r |
861 | IN VOID *Context2, OPTIONAL\r |
862 | IN VOID *NewStack\r |
863 | )\r |
864 | {\r |
865 | ASSERT (EntryPoint != NULL);\r |
866 | ASSERT (NewStack != NULL);\r |
867 | InternalX86DisablePaging32 (EntryPoint, Context1, Context2, NewStack);\r |
868 | }\r |
869 | \r |
870 | /**\r |
871 | Enables the 64-bit paging mode on the CPU.\r |
872 | \r |
873 | Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r |
874 | must be properly initialized prior to calling this service. This function\r |
875 | assumes the current execution mode is 32-bit protected mode with flat\r |
876 | descriptors. This function is only available on IA-32. After the 64-bit\r |
877 | paging mode is enabled, control is transferred to the function specified by\r |
878 | EntryPoint using the new stack specified by NewStack and passing in the\r |
879 | parameters specified by Context1 and Context2. Context1 and Context2 are\r |
880 | optional and may be 0. The function EntryPoint must never return.\r |
881 | \r |
882 | If the current execution mode is not 32-bit protected mode with flat\r |
883 | descriptors, then ASSERT().\r |
884 | If EntryPoint is 0, then ASSERT().\r |
885 | If NewStack is 0, then ASSERT().\r |
886 | \r |
887 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r |
888 | is called. The descriptor in the GDT that this selector\r |
889 | references must be setup for long mode.\r |
890 | @param EntryPoint The 64-bit virtual address of the function to call with\r |
891 | the new stack after paging is enabled.\r |
892 | @param Context1 The 64-bit virtual address of the context to pass into\r |
893 | the EntryPoint function as the first parameter after\r |
894 | paging is enabled.\r |
895 | @param Context2 The 64-bit virtual address of the context to pass into\r |
896 | the EntryPoint function as the second parameter after\r |
897 | paging is enabled.\r |
898 | @param NewStack The 64-bit virtual address of the new stack to use for\r |
899 | the EntryPoint function after paging is enabled.\r |
900 | \r |
901 | **/\r |
902 | VOID\r |
903 | EFIAPI\r |
904 | AsmEnablePaging64 (\r |
905 | IN UINT16 Cs,\r |
906 | IN UINT64 EntryPoint,\r |
907 | IN UINT64 Context1, OPTIONAL\r |
908 | IN UINT64 Context2, OPTIONAL\r |
909 | IN UINT64 NewStack\r |
910 | )\r |
911 | {\r |
912 | ASSERT (EntryPoint != 0);\r |
913 | ASSERT (NewStack != 0);\r |
914 | InternalX86EnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r |
915 | }\r |
916 | \r |
917 | /**\r |
918 | Disables the 64-bit paging mode on the CPU.\r |
919 | \r |
920 | Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r |
921 | mode. This function assumes the current execution mode is 64-paging mode.\r |
922 | This function is only available on X64. After the 64-bit paging mode is\r |
923 | disabled, control is transferred to the function specified by EntryPoint\r |
924 | using the new stack specified by NewStack and passing in the parameters\r |
925 | specified by Context1 and Context2. Context1 and Context2 are optional and\r |
926 | may be 0. The function EntryPoint must never return.\r |
927 | \r |
928 | If the current execution mode is not 64-bit paged mode, then ASSERT().\r |
929 | If EntryPoint is 0, then ASSERT().\r |
930 | If NewStack is 0, then ASSERT().\r |
931 | \r |
932 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r |
933 | is called. The descriptor in the GDT that this selector\r |
934 | references must be setup for 32-bit protected mode.\r |
935 | @param EntryPoint The 64-bit virtual address of the function to call with\r |
936 | the new stack after paging is disabled.\r |
937 | @param Context1 The 64-bit virtual address of the context to pass into\r |
938 | the EntryPoint function as the first parameter after\r |
939 | paging is disabled.\r |
940 | @param Context2 The 64-bit virtual address of the context to pass into\r |
941 | the EntryPoint function as the second parameter after\r |
942 | paging is disabled.\r |
943 | @param NewStack The 64-bit virtual address of the new stack to use for\r |
944 | the EntryPoint function after paging is disabled.\r |
945 | \r |
946 | **/\r |
947 | VOID\r |
948 | EFIAPI\r |
949 | AsmDisablePaging64 (\r |
950 | IN UINT16 Cs,\r |
951 | IN UINT32 EntryPoint,\r |
952 | IN UINT32 Context1, OPTIONAL\r |
953 | IN UINT32 Context2, OPTIONAL\r |
954 | IN UINT32 NewStack\r |
955 | )\r |
956 | {\r |
957 | ASSERT (EntryPoint != 0);\r |
958 | ASSERT (NewStack != 0);\r |
959 | InternalX86DisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r |
960 | }\r |
961 | \r |
962 | //\r |
963 | // x86 version of MemoryFence()\r |
964 | //\r |
965 | \r |
966 | /**\r |
967 | Used to serialize load and store operations.\r |
968 | \r |
969 | All loads and stores that proceed calls to this function are guaranteed to be\r |
970 | globally visible when this function returns.\r |
971 | \r |
972 | **/\r |
973 | VOID\r |
974 | EFIAPI\r |
975 | MemoryFence (\r |
976 | VOID\r |
977 | )\r |
978 | {\r |
979 | }\r |