878ddf1f |
1 | /** @file\r |
2 | PCI Library.\r |
3 | \r |
4 | Functions in this library instance make use of MMIO functions in IoLib to\r |
5 | access memory mapped PCI configuration space.\r |
6 | \r |
7 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r |
8 | Library.\r |
9 | \r |
10 | Copyright (c) 2006, Intel Corporation<BR>\r |
11 | All rights reserved. This program and the accompanying materials\r |
12 | are licensed and made available under the terms and conditions of the BSD License\r |
13 | which accompanies this distribution. The full text of the license may be found at\r |
14 | http://opensource.org/licenses/bsd-license.php\r |
15 | \r |
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
17 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
18 | \r |
19 | Module Name: PciLib.c\r |
20 | \r |
21 | **/\r |
22 | \r |
23 | /**\r |
24 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r |
25 | only in the low 28 bits.\r |
26 | \r |
27 | @param A The address to validate.\r |
28 | \r |
29 | **/\r |
30 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r |
31 | ASSERT (((A) & ~0xfffffff) == 0)\r |
32 | \r |
33 | \r |
34 | UINTN\r |
35 | EFIAPI\r |
36 | GetPciExpressBaseAddress (\r |
37 | VOID\r |
38 | )\r |
39 | {\r |
40 | /// @bug Change this to a PCD Get call to retrieve the PCI-E Base Address\r |
41 | return 0xc0000000;\r |
42 | }\r |
43 | \r |
44 | /**\r |
45 | Reads an 8-bit PCI configuration register.\r |
46 | \r |
47 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
48 | This function must guarantee that all PCI read and write operations are\r |
49 | serialized.\r |
50 | \r |
51 | If Address > 0x0FFFFFFF, then ASSERT().\r |
52 | \r |
53 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
54 | Register.\r |
55 | \r |
56 | @return The read value from the PCI configuration register.\r |
57 | \r |
58 | **/\r |
59 | UINT8\r |
60 | EFIAPI\r |
61 | PciExpressRead8 (\r |
62 | IN UINTN Address\r |
63 | )\r |
64 | {\r |
65 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
66 | return MmioRead8 (GetPciExpressBaseAddress () + Address);\r |
67 | }\r |
68 | \r |
69 | /**\r |
70 | Writes an 8-bit PCI configuration register.\r |
71 | \r |
72 | Writes the 8-bit PCI configuration register specified by Address with the\r |
73 | value specified by Value. Value is returned. This function must guarantee\r |
74 | that all PCI read and write operations are serialized.\r |
75 | \r |
76 | If Address > 0x0FFFFFFF, then ASSERT().\r |
77 | \r |
78 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
79 | Register.\r |
80 | @param Value The value to write.\r |
81 | \r |
82 | @return The value written to the PCI configuration register.\r |
83 | \r |
84 | **/\r |
85 | UINT8\r |
86 | EFIAPI\r |
87 | PciExpressWrite8 (\r |
88 | IN UINTN Address,\r |
89 | IN UINT8 Value\r |
90 | )\r |
91 | {\r |
92 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
93 | return MmioWrite8 (GetPciExpressBaseAddress () + Address, Value);\r |
94 | }\r |
95 | \r |
96 | /**\r |
97 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
98 | an 8-bit value.\r |
99 | \r |
100 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
101 | bitwise inclusive OR between the read result and the value specified by\r |
102 | OrData, and writes the result to the 8-bit PCI configuration register\r |
103 | specified by Address. The value written to the PCI configuration register is\r |
104 | returned. This function must guarantee that all PCI read and write operations\r |
105 | are serialized.\r |
106 | \r |
107 | If Address > 0x0FFFFFFF, then ASSERT().\r |
108 | \r |
109 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
110 | Register.\r |
111 | @param OrData The value to OR with the PCI configuration register.\r |
112 | \r |
113 | @return The value written back to the PCI configuration register.\r |
114 | \r |
115 | **/\r |
116 | UINT8\r |
117 | EFIAPI\r |
118 | PciExpressOr8 (\r |
119 | IN UINTN Address,\r |
120 | IN UINT8 OrData\r |
121 | )\r |
122 | {\r |
123 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
124 | return MmioOr8 (GetPciExpressBaseAddress () + Address, OrData);\r |
125 | }\r |
126 | \r |
127 | /**\r |
128 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
129 | value.\r |
130 | \r |
131 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
132 | bitwise AND between the read result and the value specified by AndData, and\r |
133 | writes the result to the 8-bit PCI configuration register specified by\r |
134 | Address. The value written to the PCI configuration register is returned.\r |
135 | This function must guarantee that all PCI read and write operations are\r |
136 | serialized.\r |
137 | \r |
138 | If Address > 0x0FFFFFFF, then ASSERT().\r |
139 | \r |
140 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
141 | Register.\r |
142 | @param AndData The value to AND with the PCI configuration register.\r |
143 | \r |
144 | @return The value written back to the PCI configuration register.\r |
145 | \r |
146 | **/\r |
147 | UINT8\r |
148 | EFIAPI\r |
149 | PciExpressAnd8 (\r |
150 | IN UINTN Address,\r |
151 | IN UINT8 AndData\r |
152 | )\r |
153 | {\r |
154 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
155 | return MmioAnd8 (GetPciExpressBaseAddress () + Address, AndData);\r |
156 | }\r |
157 | \r |
158 | /**\r |
159 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
160 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
161 | \r |
162 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
163 | bitwise AND between the read result and the value specified by AndData,\r |
164 | performs a bitwise inclusive OR between the result of the AND operation and\r |
165 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
166 | configuration register specified by Address. The value written to the PCI\r |
167 | configuration register is returned. This function must guarantee that all PCI\r |
168 | read and write operations are serialized.\r |
169 | \r |
170 | If Address > 0x0FFFFFFF, then ASSERT().\r |
171 | \r |
172 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
173 | Register.\r |
174 | @param AndData The value to AND with the PCI configuration register.\r |
175 | @param OrData The value to OR with the result of the AND operation.\r |
176 | \r |
177 | @return The value written back to the PCI configuration register.\r |
178 | \r |
179 | **/\r |
180 | UINT8\r |
181 | EFIAPI\r |
182 | PciExpressAndThenOr8 (\r |
183 | IN UINTN Address,\r |
184 | IN UINT8 AndData,\r |
185 | IN UINT8 OrData\r |
186 | )\r |
187 | {\r |
188 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
189 | return MmioAndThenOr8 (\r |
190 | GetPciExpressBaseAddress () + Address,\r |
191 | AndData,\r |
192 | OrData\r |
193 | );\r |
194 | }\r |
195 | \r |
196 | /**\r |
197 | Reads a bit field of a PCI configuration register.\r |
198 | \r |
199 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
200 | specified by the StartBit and the EndBit. The value of the bit field is\r |
201 | returned.\r |
202 | \r |
203 | If Address > 0x0FFFFFFF, then ASSERT().\r |
204 | If StartBit is greater than 7, then ASSERT().\r |
205 | If EndBit is greater than 7, then ASSERT().\r |
206 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
207 | \r |
208 | @param Address PCI configuration register to read.\r |
209 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
210 | Range 0..7.\r |
211 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
212 | Range 0..7.\r |
213 | \r |
214 | @return The value of the bit field read from the PCI configuration register.\r |
215 | \r |
216 | **/\r |
217 | UINT8\r |
218 | EFIAPI\r |
219 | PciExpressBitFieldRead8 (\r |
220 | IN UINTN Address,\r |
221 | IN UINTN StartBit,\r |
222 | IN UINTN EndBit\r |
223 | )\r |
224 | {\r |
225 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
226 | return MmioBitFieldRead8 (\r |
227 | GetPciExpressBaseAddress () + Address,\r |
228 | StartBit,\r |
229 | EndBit\r |
230 | );\r |
231 | }\r |
232 | \r |
233 | /**\r |
234 | Writes a bit field to a PCI configuration register.\r |
235 | \r |
236 | Writes Value to the bit field of the PCI configuration register. The bit\r |
237 | field is specified by the StartBit and the EndBit. All other bits in the\r |
238 | destination PCI configuration register are preserved. The new value of the\r |
239 | 8-bit register is returned.\r |
240 | \r |
241 | If Address > 0x0FFFFFFF, then ASSERT().\r |
242 | If StartBit is greater than 7, then ASSERT().\r |
243 | If EndBit is greater than 7, then ASSERT().\r |
244 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
245 | \r |
246 | @param Address PCI configuration register to write.\r |
247 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
248 | Range 0..7.\r |
249 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
250 | Range 0..7.\r |
251 | @param Value New value of the bit field.\r |
252 | \r |
253 | @return The value written back to the PCI configuration register.\r |
254 | \r |
255 | **/\r |
256 | UINT8\r |
257 | EFIAPI\r |
258 | PciExpressBitFieldWrite8 (\r |
259 | IN UINTN Address,\r |
260 | IN UINTN StartBit,\r |
261 | IN UINTN EndBit,\r |
262 | IN UINT8 Value\r |
263 | )\r |
264 | {\r |
265 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
266 | return MmioBitFieldWrite8 (\r |
267 | GetPciExpressBaseAddress () + Address,\r |
268 | StartBit,\r |
269 | EndBit,\r |
270 | Value\r |
271 | );\r |
272 | }\r |
273 | \r |
274 | /**\r |
275 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
276 | writes the result back to the bit field in the 8-bit port.\r |
277 | \r |
278 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
279 | bitwise inclusive OR between the read result and the value specified by\r |
280 | OrData, and writes the result to the 8-bit PCI configuration register\r |
281 | specified by Address. The value written to the PCI configuration register is\r |
282 | returned. This function must guarantee that all PCI read and write operations\r |
283 | are serialized. Extra left bits in OrData are stripped.\r |
284 | \r |
285 | If Address > 0x0FFFFFFF, then ASSERT().\r |
286 | If StartBit is greater than 7, then ASSERT().\r |
287 | If EndBit is greater than 7, then ASSERT().\r |
288 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
289 | \r |
290 | @param Address PCI configuration register to write.\r |
291 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
292 | Range 0..7.\r |
293 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
294 | Range 0..7.\r |
295 | @param OrData The value to OR with the PCI configuration register.\r |
296 | \r |
297 | @return The value written back to the PCI configuration register.\r |
298 | \r |
299 | **/\r |
300 | UINT8\r |
301 | EFIAPI\r |
302 | PciExpressBitFieldOr8 (\r |
303 | IN UINTN Address,\r |
304 | IN UINTN StartBit,\r |
305 | IN UINTN EndBit,\r |
306 | IN UINT8 OrData\r |
307 | )\r |
308 | {\r |
309 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
310 | return MmioBitFieldOr8 (\r |
311 | GetPciExpressBaseAddress () + Address,\r |
312 | StartBit,\r |
313 | EndBit,\r |
314 | OrData\r |
315 | );\r |
316 | }\r |
317 | \r |
318 | /**\r |
319 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
320 | AND, and writes the result back to the bit field in the 8-bit register.\r |
321 | \r |
322 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
323 | bitwise AND between the read result and the value specified by AndData, and\r |
324 | writes the result to the 8-bit PCI configuration register specified by\r |
325 | Address. The value written to the PCI configuration register is returned.\r |
326 | This function must guarantee that all PCI read and write operations are\r |
327 | serialized. Extra left bits in AndData are stripped.\r |
328 | \r |
329 | If Address > 0x0FFFFFFF, then ASSERT().\r |
330 | If StartBit is greater than 7, then ASSERT().\r |
331 | If EndBit is greater than 7, then ASSERT().\r |
332 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
333 | \r |
334 | @param Address PCI configuration register to write.\r |
335 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
336 | Range 0..7.\r |
337 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
338 | Range 0..7.\r |
339 | @param AndData The value to AND with the PCI configuration register.\r |
340 | \r |
341 | @return The value written back to the PCI configuration register.\r |
342 | \r |
343 | **/\r |
344 | UINT8\r |
345 | EFIAPI\r |
346 | PciExpressBitFieldAnd8 (\r |
347 | IN UINTN Address,\r |
348 | IN UINTN StartBit,\r |
349 | IN UINTN EndBit,\r |
350 | IN UINT8 AndData\r |
351 | )\r |
352 | {\r |
353 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
354 | return MmioBitFieldAnd8 (\r |
355 | GetPciExpressBaseAddress () + Address,\r |
356 | StartBit,\r |
357 | EndBit,\r |
358 | AndData\r |
359 | );\r |
360 | }\r |
361 | \r |
362 | /**\r |
363 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
364 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
365 | 8-bit port.\r |
366 | \r |
367 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
368 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
369 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
370 | configuration register specified by Address. The value written to the PCI\r |
371 | configuration register is returned. This function must guarantee that all PCI\r |
372 | read and write operations are serialized. Extra left bits in both AndData and\r |
373 | OrData are stripped.\r |
374 | \r |
375 | If Address > 0x0FFFFFFF, then ASSERT().\r |
376 | If StartBit is greater than 7, then ASSERT().\r |
377 | If EndBit is greater than 7, then ASSERT().\r |
378 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
379 | \r |
380 | @param Address PCI configuration register to write.\r |
381 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
382 | Range 0..7.\r |
383 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
384 | Range 0..7.\r |
385 | @param AndData The value to AND with the PCI configuration register.\r |
386 | @param OrData The value to OR with the result of the AND operation.\r |
387 | \r |
388 | @return The value written back to the PCI configuration register.\r |
389 | \r |
390 | **/\r |
391 | UINT8\r |
392 | EFIAPI\r |
393 | PciExpressBitFieldAndThenOr8 (\r |
394 | IN UINTN Address,\r |
395 | IN UINTN StartBit,\r |
396 | IN UINTN EndBit,\r |
397 | IN UINT8 AndData,\r |
398 | IN UINT8 OrData\r |
399 | )\r |
400 | {\r |
401 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
402 | return MmioBitFieldAndThenOr8 (\r |
403 | GetPciExpressBaseAddress () + Address,\r |
404 | StartBit,\r |
405 | EndBit,\r |
406 | AndData,\r |
407 | OrData\r |
408 | );\r |
409 | }\r |
410 | \r |
411 | /**\r |
412 | Reads a 16-bit PCI configuration register.\r |
413 | \r |
414 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
415 | This function must guarantee that all PCI read and write operations are\r |
416 | serialized.\r |
417 | \r |
418 | If Address > 0x0FFFFFFF, then ASSERT().\r |
419 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
420 | \r |
421 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
422 | Register.\r |
423 | \r |
424 | @return The read value from the PCI configuration register.\r |
425 | \r |
426 | **/\r |
427 | UINT16\r |
428 | EFIAPI\r |
429 | PciExpressRead16 (\r |
430 | IN UINTN Address\r |
431 | )\r |
432 | {\r |
433 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
434 | return MmioRead16 (GetPciExpressBaseAddress () + Address);\r |
435 | }\r |
436 | \r |
437 | /**\r |
438 | Writes a 16-bit PCI configuration register.\r |
439 | \r |
440 | Writes the 16-bit PCI configuration register specified by Address with the\r |
441 | value specified by Value. Value is returned. This function must guarantee\r |
442 | that all PCI read and write operations are serialized.\r |
443 | \r |
444 | If Address > 0x0FFFFFFF, then ASSERT().\r |
445 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
446 | \r |
447 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
448 | Register.\r |
449 | @param Value The value to write.\r |
450 | \r |
451 | @return The value written to the PCI configuration register.\r |
452 | \r |
453 | **/\r |
454 | UINT16\r |
455 | EFIAPI\r |
456 | PciExpressWrite16 (\r |
457 | IN UINTN Address,\r |
458 | IN UINT16 Value\r |
459 | )\r |
460 | {\r |
461 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
462 | return MmioWrite16 (GetPciExpressBaseAddress () + Address, Value);\r |
463 | }\r |
464 | \r |
465 | /**\r |
466 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
467 | a 16-bit value.\r |
468 | \r |
469 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
470 | bitwise inclusive OR between the read result and the value specified by\r |
471 | OrData, and writes the result to the 16-bit PCI configuration register\r |
472 | specified by Address. The value written to the PCI configuration register is\r |
473 | returned. This function must guarantee that all PCI read and write operations\r |
474 | are serialized.\r |
475 | \r |
476 | If Address > 0x0FFFFFFF, then ASSERT().\r |
477 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
478 | \r |
479 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
480 | Register.\r |
481 | @param OrData The value to OR with the PCI configuration register.\r |
482 | \r |
483 | @return The value written back to the PCI configuration register.\r |
484 | \r |
485 | **/\r |
486 | UINT16\r |
487 | EFIAPI\r |
488 | PciExpressOr16 (\r |
489 | IN UINTN Address,\r |
490 | IN UINT16 OrData\r |
491 | )\r |
492 | {\r |
493 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
494 | return MmioOr16 (GetPciExpressBaseAddress () + Address, OrData);\r |
495 | }\r |
496 | \r |
497 | /**\r |
498 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
499 | value.\r |
500 | \r |
501 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
502 | bitwise AND between the read result and the value specified by AndData, and\r |
503 | writes the result to the 16-bit PCI configuration register specified by\r |
504 | Address. The value written to the PCI configuration register is returned.\r |
505 | This function must guarantee that all PCI read and write operations are\r |
506 | serialized.\r |
507 | \r |
508 | If Address > 0x0FFFFFFF, then ASSERT().\r |
509 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
510 | \r |
511 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
512 | Register.\r |
513 | @param AndData The value to AND with the PCI configuration register.\r |
514 | \r |
515 | @return The value written back to the PCI configuration register.\r |
516 | \r |
517 | **/\r |
518 | UINT16\r |
519 | EFIAPI\r |
520 | PciExpressAnd16 (\r |
521 | IN UINTN Address,\r |
522 | IN UINT16 AndData\r |
523 | )\r |
524 | {\r |
525 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
526 | return MmioAnd16 (GetPciExpressBaseAddress () + Address, AndData);\r |
527 | }\r |
528 | \r |
529 | /**\r |
530 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
531 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
532 | \r |
533 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
534 | bitwise AND between the read result and the value specified by AndData,\r |
535 | performs a bitwise inclusive OR between the result of the AND operation and\r |
536 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
537 | configuration register specified by Address. The value written to the PCI\r |
538 | configuration register is returned. This function must guarantee that all PCI\r |
539 | read and write operations are serialized.\r |
540 | \r |
541 | If Address > 0x0FFFFFFF, then ASSERT().\r |
542 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
543 | \r |
544 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
545 | Register.\r |
546 | @param AndData The value to AND with the PCI configuration register.\r |
547 | @param OrData The value to OR with the result of the AND operation.\r |
548 | \r |
549 | @return The value written back to the PCI configuration register.\r |
550 | \r |
551 | **/\r |
552 | UINT16\r |
553 | EFIAPI\r |
554 | PciExpressAndThenOr16 (\r |
555 | IN UINTN Address,\r |
556 | IN UINT16 AndData,\r |
557 | IN UINT16 OrData\r |
558 | )\r |
559 | {\r |
560 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
561 | return MmioAndThenOr16 (\r |
562 | GetPciExpressBaseAddress () + Address,\r |
563 | AndData,\r |
564 | OrData\r |
565 | );\r |
566 | }\r |
567 | \r |
568 | /**\r |
569 | Reads a bit field of a PCI configuration register.\r |
570 | \r |
571 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
572 | specified by the StartBit and the EndBit. The value of the bit field is\r |
573 | returned.\r |
574 | \r |
575 | If Address > 0x0FFFFFFF, then ASSERT().\r |
576 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
577 | If StartBit is greater than 15, then ASSERT().\r |
578 | If EndBit is greater than 15, then ASSERT().\r |
579 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
580 | \r |
581 | @param Address PCI configuration register to read.\r |
582 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
583 | Range 0..15.\r |
584 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
585 | Range 0..15.\r |
586 | \r |
587 | @return The value of the bit field read from the PCI configuration register.\r |
588 | \r |
589 | **/\r |
590 | UINT16\r |
591 | EFIAPI\r |
592 | PciExpressBitFieldRead16 (\r |
593 | IN UINTN Address,\r |
594 | IN UINTN StartBit,\r |
595 | IN UINTN EndBit\r |
596 | )\r |
597 | {\r |
598 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
599 | return MmioBitFieldRead16 (\r |
600 | GetPciExpressBaseAddress () + Address,\r |
601 | StartBit,\r |
602 | EndBit\r |
603 | );\r |
604 | }\r |
605 | \r |
606 | /**\r |
607 | Writes a bit field to a PCI configuration register.\r |
608 | \r |
609 | Writes Value to the bit field of the PCI configuration register. The bit\r |
610 | field is specified by the StartBit and the EndBit. All other bits in the\r |
611 | destination PCI configuration register are preserved. The new value of the\r |
612 | 16-bit register is returned.\r |
613 | \r |
614 | If Address > 0x0FFFFFFF, then ASSERT().\r |
615 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
616 | If StartBit is greater than 15, then ASSERT().\r |
617 | If EndBit is greater than 15, then ASSERT().\r |
618 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
619 | \r |
620 | @param Address PCI configuration register to write.\r |
621 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
622 | Range 0..15.\r |
623 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
624 | Range 0..15.\r |
625 | @param Value New value of the bit field.\r |
626 | \r |
627 | @return The value written back to the PCI configuration register.\r |
628 | \r |
629 | **/\r |
630 | UINT16\r |
631 | EFIAPI\r |
632 | PciExpressBitFieldWrite16 (\r |
633 | IN UINTN Address,\r |
634 | IN UINTN StartBit,\r |
635 | IN UINTN EndBit,\r |
636 | IN UINT16 Value\r |
637 | )\r |
638 | {\r |
639 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
640 | return MmioBitFieldWrite16 (\r |
641 | GetPciExpressBaseAddress () + Address,\r |
642 | StartBit,\r |
643 | EndBit,\r |
644 | Value\r |
645 | );\r |
646 | }\r |
647 | \r |
648 | /**\r |
649 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
650 | writes the result back to the bit field in the 16-bit port.\r |
651 | \r |
652 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
653 | bitwise inclusive OR between the read result and the value specified by\r |
654 | OrData, and writes the result to the 16-bit PCI configuration register\r |
655 | specified by Address. The value written to the PCI configuration register is\r |
656 | returned. This function must guarantee that all PCI read and write operations\r |
657 | are serialized. Extra left bits in OrData are stripped.\r |
658 | \r |
659 | If Address > 0x0FFFFFFF, then ASSERT().\r |
660 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
661 | If StartBit is greater than 15, then ASSERT().\r |
662 | If EndBit is greater than 15, then ASSERT().\r |
663 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
664 | \r |
665 | @param Address PCI configuration register to write.\r |
666 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
667 | Range 0..15.\r |
668 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
669 | Range 0..15.\r |
670 | @param OrData The value to OR with the PCI configuration register.\r |
671 | \r |
672 | @return The value written back to the PCI configuration register.\r |
673 | \r |
674 | **/\r |
675 | UINT16\r |
676 | EFIAPI\r |
677 | PciExpressBitFieldOr16 (\r |
678 | IN UINTN Address,\r |
679 | IN UINTN StartBit,\r |
680 | IN UINTN EndBit,\r |
681 | IN UINT16 OrData\r |
682 | )\r |
683 | {\r |
684 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
685 | return MmioBitFieldOr16 (\r |
686 | GetPciExpressBaseAddress () + Address,\r |
687 | StartBit,\r |
688 | EndBit,\r |
689 | OrData\r |
690 | );\r |
691 | }\r |
692 | \r |
693 | /**\r |
694 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
695 | AND, and writes the result back to the bit field in the 16-bit register.\r |
696 | \r |
697 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
698 | bitwise AND between the read result and the value specified by AndData, and\r |
699 | writes the result to the 16-bit PCI configuration register specified by\r |
700 | Address. The value written to the PCI configuration register is returned.\r |
701 | This function must guarantee that all PCI read and write operations are\r |
702 | serialized. Extra left bits in AndData are stripped.\r |
703 | \r |
704 | If Address > 0x0FFFFFFF, then ASSERT().\r |
705 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
706 | If StartBit is greater than 15, then ASSERT().\r |
707 | If EndBit is greater than 15, then ASSERT().\r |
708 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
709 | \r |
710 | @param Address PCI configuration register to write.\r |
711 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
712 | Range 0..15.\r |
713 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
714 | Range 0..15.\r |
715 | @param AndData The value to AND with the PCI configuration register.\r |
716 | \r |
717 | @return The value written back to the PCI configuration register.\r |
718 | \r |
719 | **/\r |
720 | UINT16\r |
721 | EFIAPI\r |
722 | PciExpressBitFieldAnd16 (\r |
723 | IN UINTN Address,\r |
724 | IN UINTN StartBit,\r |
725 | IN UINTN EndBit,\r |
726 | IN UINT16 AndData\r |
727 | )\r |
728 | {\r |
729 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
730 | return MmioBitFieldAnd16 (\r |
731 | GetPciExpressBaseAddress () + Address,\r |
732 | StartBit,\r |
733 | EndBit,\r |
734 | AndData\r |
735 | );\r |
736 | }\r |
737 | \r |
738 | /**\r |
739 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
740 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
741 | 16-bit port.\r |
742 | \r |
743 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
744 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
745 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
746 | configuration register specified by Address. The value written to the PCI\r |
747 | configuration register is returned. This function must guarantee that all PCI\r |
748 | read and write operations are serialized. Extra left bits in both AndData and\r |
749 | OrData are stripped.\r |
750 | \r |
751 | If Address > 0x0FFFFFFF, then ASSERT().\r |
752 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
753 | If StartBit is greater than 15, then ASSERT().\r |
754 | If EndBit is greater than 15, then ASSERT().\r |
755 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
756 | \r |
757 | @param Address PCI configuration register to write.\r |
758 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
759 | Range 0..15.\r |
760 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
761 | Range 0..15.\r |
762 | @param AndData The value to AND with the PCI configuration register.\r |
763 | @param OrData The value to OR with the result of the AND operation.\r |
764 | \r |
765 | @return The value written back to the PCI configuration register.\r |
766 | \r |
767 | **/\r |
768 | UINT16\r |
769 | EFIAPI\r |
770 | PciExpressBitFieldAndThenOr16 (\r |
771 | IN UINTN Address,\r |
772 | IN UINTN StartBit,\r |
773 | IN UINTN EndBit,\r |
774 | IN UINT16 AndData,\r |
775 | IN UINT16 OrData\r |
776 | )\r |
777 | {\r |
778 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
779 | return MmioBitFieldAndThenOr16 (\r |
780 | GetPciExpressBaseAddress () + Address,\r |
781 | StartBit,\r |
782 | EndBit,\r |
783 | AndData,\r |
784 | OrData\r |
785 | );\r |
786 | }\r |
787 | \r |
788 | /**\r |
789 | Reads a 32-bit PCI configuration register.\r |
790 | \r |
791 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
792 | This function must guarantee that all PCI read and write operations are\r |
793 | serialized.\r |
794 | \r |
795 | If Address > 0x0FFFFFFF, then ASSERT().\r |
796 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
797 | \r |
798 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
799 | Register.\r |
800 | \r |
801 | @return The read value from the PCI configuration register.\r |
802 | \r |
803 | **/\r |
804 | UINT32\r |
805 | EFIAPI\r |
806 | PciExpressRead32 (\r |
807 | IN UINTN Address\r |
808 | )\r |
809 | {\r |
810 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
811 | return MmioRead32 (GetPciExpressBaseAddress () + Address);\r |
812 | }\r |
813 | \r |
814 | /**\r |
815 | Writes a 32-bit PCI configuration register.\r |
816 | \r |
817 | Writes the 32-bit PCI configuration register specified by Address with the\r |
818 | value specified by Value. Value is returned. This function must guarantee\r |
819 | that all PCI read and write operations are serialized.\r |
820 | \r |
821 | If Address > 0x0FFFFFFF, then ASSERT().\r |
822 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
823 | \r |
824 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
825 | Register.\r |
826 | @param Value The value to write.\r |
827 | \r |
828 | @return The value written to the PCI configuration register.\r |
829 | \r |
830 | **/\r |
831 | UINT32\r |
832 | EFIAPI\r |
833 | PciExpressWrite32 (\r |
834 | IN UINTN Address,\r |
835 | IN UINT32 Value\r |
836 | )\r |
837 | {\r |
838 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
839 | return MmioWrite32 (GetPciExpressBaseAddress () + Address, Value);\r |
840 | }\r |
841 | \r |
842 | /**\r |
843 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
844 | a 32-bit value.\r |
845 | \r |
846 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
847 | bitwise inclusive OR between the read result and the value specified by\r |
848 | OrData, and writes the result to the 32-bit PCI configuration register\r |
849 | specified by Address. The value written to the PCI configuration register is\r |
850 | returned. This function must guarantee that all PCI read and write operations\r |
851 | are serialized.\r |
852 | \r |
853 | If Address > 0x0FFFFFFF, then ASSERT().\r |
854 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
855 | \r |
856 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
857 | Register.\r |
858 | @param OrData The value to OR with the PCI configuration register.\r |
859 | \r |
860 | @return The value written back to the PCI configuration register.\r |
861 | \r |
862 | **/\r |
863 | UINT32\r |
864 | EFIAPI\r |
865 | PciExpressOr32 (\r |
866 | IN UINTN Address,\r |
867 | IN UINT32 OrData\r |
868 | )\r |
869 | {\r |
870 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
871 | return MmioOr32 (GetPciExpressBaseAddress () + Address, OrData);\r |
872 | }\r |
873 | \r |
874 | /**\r |
875 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
876 | value.\r |
877 | \r |
878 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
879 | bitwise AND between the read result and the value specified by AndData, and\r |
880 | writes the result to the 32-bit PCI configuration register specified by\r |
881 | Address. The value written to the PCI configuration register is returned.\r |
882 | This function must guarantee that all PCI read and write operations are\r |
883 | serialized.\r |
884 | \r |
885 | If Address > 0x0FFFFFFF, then ASSERT().\r |
886 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
887 | \r |
888 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
889 | Register.\r |
890 | @param AndData The value to AND with the PCI configuration register.\r |
891 | \r |
892 | @return The value written back to the PCI configuration register.\r |
893 | \r |
894 | **/\r |
895 | UINT32\r |
896 | EFIAPI\r |
897 | PciExpressAnd32 (\r |
898 | IN UINTN Address,\r |
899 | IN UINT32 AndData\r |
900 | )\r |
901 | {\r |
902 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
903 | return MmioAnd32 (GetPciExpressBaseAddress () + Address, AndData);\r |
904 | }\r |
905 | \r |
906 | /**\r |
907 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
908 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
909 | \r |
910 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
911 | bitwise AND between the read result and the value specified by AndData,\r |
912 | performs a bitwise inclusive OR between the result of the AND operation and\r |
913 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
914 | configuration register specified by Address. The value written to the PCI\r |
915 | configuration register is returned. This function must guarantee that all PCI\r |
916 | read and write operations are serialized.\r |
917 | \r |
918 | If Address > 0x0FFFFFFF, then ASSERT().\r |
919 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
920 | \r |
921 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
922 | Register.\r |
923 | @param AndData The value to AND with the PCI configuration register.\r |
924 | @param OrData The value to OR with the result of the AND operation.\r |
925 | \r |
926 | @return The value written back to the PCI configuration register.\r |
927 | \r |
928 | **/\r |
929 | UINT32\r |
930 | EFIAPI\r |
931 | PciExpressAndThenOr32 (\r |
932 | IN UINTN Address,\r |
933 | IN UINT32 AndData,\r |
934 | IN UINT32 OrData\r |
935 | )\r |
936 | {\r |
937 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
938 | return MmioAndThenOr32 (\r |
939 | GetPciExpressBaseAddress () + Address,\r |
940 | AndData,\r |
941 | OrData\r |
942 | );\r |
943 | }\r |
944 | \r |
945 | /**\r |
946 | Reads a bit field of a PCI configuration register.\r |
947 | \r |
948 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
949 | specified by the StartBit and the EndBit. The value of the bit field is\r |
950 | returned.\r |
951 | \r |
952 | If Address > 0x0FFFFFFF, then ASSERT().\r |
953 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
954 | If StartBit is greater than 31, then ASSERT().\r |
955 | If EndBit is greater than 31, then ASSERT().\r |
956 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
957 | \r |
958 | @param Address PCI configuration register to read.\r |
959 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
960 | Range 0..31.\r |
961 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
962 | Range 0..31.\r |
963 | \r |
964 | @return The value of the bit field read from the PCI configuration register.\r |
965 | \r |
966 | **/\r |
967 | UINT32\r |
968 | EFIAPI\r |
969 | PciExpressBitFieldRead32 (\r |
970 | IN UINTN Address,\r |
971 | IN UINTN StartBit,\r |
972 | IN UINTN EndBit\r |
973 | )\r |
974 | {\r |
975 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
976 | return MmioBitFieldRead32 (\r |
977 | GetPciExpressBaseAddress () + Address,\r |
978 | StartBit,\r |
979 | EndBit\r |
980 | );\r |
981 | }\r |
982 | \r |
983 | /**\r |
984 | Writes a bit field to a PCI configuration register.\r |
985 | \r |
986 | Writes Value to the bit field of the PCI configuration register. The bit\r |
987 | field is specified by the StartBit and the EndBit. All other bits in the\r |
988 | destination PCI configuration register are preserved. The new value of the\r |
989 | 32-bit register is returned.\r |
990 | \r |
991 | If Address > 0x0FFFFFFF, then ASSERT().\r |
992 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
993 | If StartBit is greater than 31, then ASSERT().\r |
994 | If EndBit is greater than 31, then ASSERT().\r |
995 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
996 | \r |
997 | @param Address PCI configuration register to write.\r |
998 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
999 | Range 0..31.\r |
1000 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
1001 | Range 0..31.\r |
1002 | @param Value New value of the bit field.\r |
1003 | \r |
1004 | @return The value written back to the PCI configuration register.\r |
1005 | \r |
1006 | **/\r |
1007 | UINT32\r |
1008 | EFIAPI\r |
1009 | PciExpressBitFieldWrite32 (\r |
1010 | IN UINTN Address,\r |
1011 | IN UINTN StartBit,\r |
1012 | IN UINTN EndBit,\r |
1013 | IN UINT32 Value\r |
1014 | )\r |
1015 | {\r |
1016 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
1017 | return MmioBitFieldWrite32 (\r |
1018 | GetPciExpressBaseAddress () + Address,\r |
1019 | StartBit,\r |
1020 | EndBit,\r |
1021 | Value\r |
1022 | );\r |
1023 | }\r |
1024 | \r |
1025 | /**\r |
1026 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
1027 | writes the result back to the bit field in the 32-bit port.\r |
1028 | \r |
1029 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
1030 | bitwise inclusive OR between the read result and the value specified by\r |
1031 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1032 | specified by Address. The value written to the PCI configuration register is\r |
1033 | returned. This function must guarantee that all PCI read and write operations\r |
1034 | are serialized. Extra left bits in OrData are stripped.\r |
1035 | \r |
1036 | If Address > 0x0FFFFFFF, then ASSERT().\r |
1037 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1038 | If StartBit is greater than 31, then ASSERT().\r |
1039 | If EndBit is greater than 31, then ASSERT().\r |
1040 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
1041 | \r |
1042 | @param Address PCI configuration register to write.\r |
1043 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1044 | Range 0..31.\r |
1045 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
1046 | Range 0..31.\r |
1047 | @param OrData The value to OR with the PCI configuration register.\r |
1048 | \r |
1049 | @return The value written back to the PCI configuration register.\r |
1050 | \r |
1051 | **/\r |
1052 | UINT32\r |
1053 | EFIAPI\r |
1054 | PciExpressBitFieldOr32 (\r |
1055 | IN UINTN Address,\r |
1056 | IN UINTN StartBit,\r |
1057 | IN UINTN EndBit,\r |
1058 | IN UINT32 OrData\r |
1059 | )\r |
1060 | {\r |
1061 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
1062 | return MmioBitFieldOr32 (\r |
1063 | GetPciExpressBaseAddress () + Address,\r |
1064 | StartBit,\r |
1065 | EndBit,\r |
1066 | OrData\r |
1067 | );\r |
1068 | }\r |
1069 | \r |
1070 | /**\r |
1071 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
1072 | AND, and writes the result back to the bit field in the 32-bit register.\r |
1073 | \r |
1074 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
1075 | bitwise AND between the read result and the value specified by AndData, and\r |
1076 | writes the result to the 32-bit PCI configuration register specified by\r |
1077 | Address. The value written to the PCI configuration register is returned.\r |
1078 | This function must guarantee that all PCI read and write operations are\r |
1079 | serialized. Extra left bits in AndData are stripped.\r |
1080 | \r |
1081 | If Address > 0x0FFFFFFF, then ASSERT().\r |
1082 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1083 | If StartBit is greater than 31, then ASSERT().\r |
1084 | If EndBit is greater than 31, then ASSERT().\r |
1085 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
1086 | \r |
1087 | @param Address PCI configuration register to write.\r |
1088 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1089 | Range 0..31.\r |
1090 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
1091 | Range 0..31.\r |
1092 | @param AndData The value to AND with the PCI configuration register.\r |
1093 | \r |
1094 | @return The value written back to the PCI configuration register.\r |
1095 | \r |
1096 | **/\r |
1097 | UINT32\r |
1098 | EFIAPI\r |
1099 | PciExpressBitFieldAnd32 (\r |
1100 | IN UINTN Address,\r |
1101 | IN UINTN StartBit,\r |
1102 | IN UINTN EndBit,\r |
1103 | IN UINT32 AndData\r |
1104 | )\r |
1105 | {\r |
1106 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
1107 | return MmioBitFieldAnd32 (\r |
1108 | GetPciExpressBaseAddress () + Address,\r |
1109 | StartBit,\r |
1110 | EndBit,\r |
1111 | AndData\r |
1112 | );\r |
1113 | }\r |
1114 | \r |
1115 | /**\r |
1116 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
1117 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
1118 | 32-bit port.\r |
1119 | \r |
1120 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
1121 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
1122 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1123 | configuration register specified by Address. The value written to the PCI\r |
1124 | configuration register is returned. This function must guarantee that all PCI\r |
1125 | read and write operations are serialized. Extra left bits in both AndData and\r |
1126 | OrData are stripped.\r |
1127 | \r |
1128 | If Address > 0x0FFFFFFF, then ASSERT().\r |
1129 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1130 | If StartBit is greater than 31, then ASSERT().\r |
1131 | If EndBit is greater than 31, then ASSERT().\r |
1132 | If EndBit is less than or equal to StartBit, then ASSERT().\r |
1133 | \r |
1134 | @param Address PCI configuration register to write.\r |
1135 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1136 | Range 0..31.\r |
1137 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
1138 | Range 0..31.\r |
1139 | @param AndData The value to AND with the PCI configuration register.\r |
1140 | @param OrData The value to OR with the result of the AND operation.\r |
1141 | \r |
1142 | @return The value written back to the PCI configuration register.\r |
1143 | \r |
1144 | **/\r |
1145 | UINT32\r |
1146 | EFIAPI\r |
1147 | PciExpressBitFieldAndThenOr32 (\r |
1148 | IN UINTN Address,\r |
1149 | IN UINTN StartBit,\r |
1150 | IN UINTN EndBit,\r |
1151 | IN UINT32 AndData,\r |
1152 | IN UINT32 OrData\r |
1153 | )\r |
1154 | {\r |
1155 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
1156 | return MmioBitFieldAndThenOr32 (\r |
1157 | GetPciExpressBaseAddress () + Address,\r |
1158 | StartBit,\r |
1159 | EndBit,\r |
1160 | AndData,\r |
1161 | OrData\r |
1162 | );\r |
1163 | }\r |
1164 | \r |
1165 | /**\r |
1166 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
1167 | \r |
1168 | Reads the range of PCI configuration registers specified by StartAddress and\r |
1169 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
1170 | configuration registers from a single PCI function to be read. Size is\r |
1171 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
1172 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
1173 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
1174 | end of the range.\r |
1175 | \r |
1176 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
1177 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
1178 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
1179 | If Buffer is NULL, then ASSERT().\r |
1180 | \r |
1181 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
1182 | Function and Register.\r |
1183 | @param Size Size in bytes of the transfer.\r |
1184 | @param Buffer Pointer to a buffer receiving the data read.\r |
1185 | \r |
1186 | @return Size\r |
1187 | \r |
1188 | **/\r |
1189 | UINTN\r |
1190 | EFIAPI\r |
1191 | PciExpressReadBuffer (\r |
1192 | IN UINTN StartAddress,\r |
1193 | IN UINTN Size,\r |
1194 | OUT VOID *Buffer\r |
1195 | )\r |
1196 | {\r |
1197 | UINTN EndAddress;\r |
1198 | \r |
1199 | EndAddress = StartAddress + Size;\r |
1200 | \r |
1201 | if (StartAddress < EndAddress && (StartAddress & 1)) {\r |
1202 | //\r |
1203 | // Read a byte if StartAddress is byte aligned\r |
1204 | //\r |
1205 | *(UINT8*)Buffer = PciExpressRead8 (StartAddress);\r |
1206 | StartAddress += sizeof (UINT8);\r |
1207 | Buffer = (UINT8*)Buffer + 1;\r |
1208 | }\r |
1209 | \r |
1210 | if (StartAddress < EndAddress && (StartAddress & 2)) {\r |
1211 | //\r |
1212 | // Read a word if StartAddress is word aligned\r |
1213 | //\r |
1214 | *(UINT16*)Buffer = PciExpressRead16 (StartAddress);\r |
1215 | StartAddress += sizeof (UINT16);\r |
1216 | Buffer = (UINT16*)Buffer + 1;\r |
1217 | }\r |
1218 | \r |
1219 | while (EndAddress - StartAddress >= 4) {\r |
1220 | //\r |
1221 | // Read as many double words as possible\r |
1222 | //\r |
1223 | *(UINT32*)Buffer = PciExpressRead32 (StartAddress);\r |
1224 | StartAddress += sizeof (UINT32);\r |
1225 | Buffer = (UINT32*)Buffer + 1;\r |
1226 | }\r |
1227 | \r |
1228 | if ((EndAddress & 2) != 0) {\r |
1229 | //\r |
1230 | // Read the last remaining word if exist\r |
1231 | //\r |
1232 | *(UINT16*)Buffer = PciExpressRead16 (StartAddress);\r |
1233 | StartAddress += sizeof (UINT16);\r |
1234 | Buffer = (UINT16*)Buffer + 1;\r |
1235 | }\r |
1236 | \r |
1237 | if (EndAddress & 1) {\r |
1238 | //\r |
1239 | // Read the last remaining byte if exist\r |
1240 | //\r |
1241 | *(UINT8*)Buffer = PciExpressRead8 (StartAddress);\r |
1242 | }\r |
1243 | \r |
1244 | return Size;\r |
1245 | }\r |
1246 | \r |
1247 | /**\r |
1248 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
1249 | configuration space.\r |
1250 | \r |
1251 | Writes the range of PCI configuration registers specified by StartAddress and\r |
1252 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
1253 | configuration registers from a single PCI function to be written. Size is\r |
1254 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
1255 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
1256 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
1257 | and the end of the range.\r |
1258 | \r |
1259 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
1260 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
1261 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r |
1262 | If Buffer is NULL, then ASSERT().\r |
1263 | \r |
1264 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
1265 | Function and Register.\r |
1266 | @param Size Size in bytes of the transfer.\r |
1267 | @param Buffer Pointer to a buffer containing the data to write.\r |
1268 | \r |
1269 | @return Size\r |
1270 | \r |
1271 | **/\r |
1272 | UINTN\r |
1273 | EFIAPI\r |
1274 | PciExpressWriteBuffer (\r |
1275 | IN UINTN StartAddress,\r |
1276 | IN UINTN Size,\r |
1277 | IN VOID *Buffer\r |
1278 | )\r |
1279 | {\r |
1280 | UINTN EndAddress;\r |
1281 | \r |
1282 | EndAddress = StartAddress + Size;\r |
1283 | \r |
1284 | if ((StartAddress < EndAddress) && ((StartAddress & 1)!= 0)) {\r |
1285 | //\r |
1286 | // Write a byte if StartAddress is byte aligned\r |
1287 | //\r |
1288 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r |
1289 | StartAddress += sizeof (UINT8);\r |
1290 | Buffer = (UINT8*)Buffer + 1;\r |
1291 | }\r |
1292 | \r |
1293 | if (StartAddress < EndAddress && (StartAddress & 2)) {\r |
1294 | //\r |
1295 | // Write a word if StartAddress is word aligned\r |
1296 | //\r |
1297 | PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);\r |
1298 | StartAddress += sizeof (UINT16);\r |
1299 | Buffer = (UINT16*)Buffer + 1;\r |
1300 | }\r |
1301 | \r |
1302 | while (EndAddress - StartAddress >= 4) {\r |
1303 | //\r |
1304 | // Write as many double words as possible\r |
1305 | //\r |
1306 | PciExpressWrite32 (StartAddress, *(UINT32*)Buffer);\r |
1307 | StartAddress += sizeof (UINT32);\r |
1308 | Buffer = (UINT32*)Buffer + 1;\r |
1309 | }\r |
1310 | \r |
1311 | if (EndAddress & 2) {\r |
1312 | //\r |
1313 | // Write the last remaining word if exist\r |
1314 | //\r |
1315 | PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);\r |
1316 | StartAddress += sizeof (UINT16);\r |
1317 | Buffer = (UINT16*)Buffer + 1;\r |
1318 | }\r |
1319 | \r |
1320 | if (EndAddress & 1) {\r |
1321 | //\r |
1322 | // Write the last remaining byte if exist\r |
1323 | //\r |
1324 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r |
1325 | }\r |
1326 | \r |
1327 | return Size;\r |
1328 | }\r |