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e1f414b6 | 1 | /** @file\r |
2 | PCI Library using PC Express access.\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
e1f414b6 | 13 | **/\r |
14 | \r | |
c892d846 | 15 | \r |
c7d265a9 | 16 | #include <Base.h>\r |
c892d846 | 17 | \r |
18 | \r | |
c7d265a9 | 19 | #include <Library/PciLib.h>\r |
20 | #include <Library/PciExpressLib.h>\r | |
e1f414b6 | 21 | \r |
22 | /**\r | |
23 | Reads an 8-bit PCI configuration register.\r | |
24 | \r | |
25 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
26 | This function must guarantee that all PCI read and write operations are\r | |
27 | serialized.\r | |
28 | \r | |
29 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
30 | \r | |
31 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
32 | Register.\r | |
33 | \r | |
34 | @return The read value from the PCI configuration register.\r | |
35 | \r | |
36 | **/\r | |
37 | UINT8\r | |
38 | EFIAPI\r | |
39 | PciRead8 (\r | |
40 | IN UINTN Address\r | |
41 | )\r | |
42 | {\r | |
43 | return PciExpressRead8 (Address);\r | |
44 | }\r | |
45 | \r | |
46 | /**\r | |
47 | Writes an 8-bit PCI configuration register.\r | |
48 | \r | |
49 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
50 | value specified by Value. Value is returned. This function must guarantee\r | |
51 | that all PCI read and write operations are serialized.\r | |
52 | \r | |
53 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
54 | \r | |
55 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
56 | Register.\r | |
57 | @param Value The value to write.\r | |
58 | \r | |
59 | @return The value written to the PCI configuration register.\r | |
60 | \r | |
61 | **/\r | |
62 | UINT8\r | |
63 | EFIAPI\r | |
64 | PciWrite8 (\r | |
65 | IN UINTN Address,\r | |
66 | IN UINT8 Data\r | |
67 | )\r | |
68 | {\r | |
69 | return PciExpressWrite8 (Address, Data);\r | |
70 | }\r | |
71 | \r | |
72 | /**\r | |
73 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
74 | an 8-bit value.\r | |
75 | \r | |
76 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
77 | bitwise inclusive OR between the read result and the value specified by\r | |
78 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
79 | specified by Address. The value written to the PCI configuration register is\r | |
80 | returned. This function must guarantee that all PCI read and write operations\r | |
81 | are serialized.\r | |
82 | \r | |
83 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
84 | \r | |
85 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
86 | Register.\r | |
87 | @param OrData The value to OR with the PCI configuration register.\r | |
88 | \r | |
89 | @return The value written back to the PCI configuration register.\r | |
90 | \r | |
91 | **/\r | |
92 | UINT8\r | |
93 | EFIAPI\r | |
94 | PciOr8 (\r | |
95 | IN UINTN Address,\r | |
96 | IN UINT8 OrData\r | |
97 | )\r | |
98 | {\r | |
99 | return PciExpressOr8 (Address, OrData);\r | |
100 | }\r | |
101 | \r | |
102 | /**\r | |
103 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
104 | value.\r | |
105 | \r | |
106 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
107 | bitwise AND between the read result and the value specified by AndData, and\r | |
108 | writes the result to the 8-bit PCI configuration register specified by\r | |
109 | Address. The value written to the PCI configuration register is returned.\r | |
110 | This function must guarantee that all PCI read and write operations are\r | |
111 | serialized.\r | |
112 | \r | |
113 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
114 | \r | |
115 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
116 | Register.\r | |
117 | @param AndData The value to AND with the PCI configuration register.\r | |
118 | \r | |
119 | @return The value written back to the PCI configuration register.\r | |
120 | \r | |
121 | **/\r | |
122 | UINT8\r | |
123 | EFIAPI\r | |
124 | PciAnd8 (\r | |
125 | IN UINTN Address,\r | |
126 | IN UINT8 AndData\r | |
127 | )\r | |
128 | {\r | |
129 | return PciExpressAnd8 (Address, AndData);\r | |
130 | }\r | |
131 | \r | |
132 | /**\r | |
133 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
134 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
135 | \r | |
136 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
137 | bitwise AND between the read result and the value specified by AndData,\r | |
138 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
139 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
140 | configuration register specified by Address. The value written to the PCI\r | |
141 | configuration register is returned. This function must guarantee that all PCI\r | |
142 | read and write operations are serialized.\r | |
143 | \r | |
144 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
145 | \r | |
146 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
147 | Register.\r | |
148 | @param AndData The value to AND with the PCI configuration register.\r | |
149 | @param OrData The value to OR with the result of the AND operation.\r | |
150 | \r | |
151 | @return The value written back to the PCI configuration register.\r | |
152 | \r | |
153 | **/\r | |
154 | UINT8\r | |
155 | EFIAPI\r | |
156 | PciAndThenOr8 (\r | |
157 | IN UINTN Address,\r | |
158 | IN UINT8 AndData,\r | |
159 | IN UINT8 OrData\r | |
160 | )\r | |
161 | {\r | |
162 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r | |
163 | }\r | |
164 | \r | |
165 | /**\r | |
166 | Reads a bit field of a PCI configuration register.\r | |
167 | \r | |
168 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
169 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
170 | returned.\r | |
171 | \r | |
172 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
173 | If StartBit is greater than 7, then ASSERT().\r | |
174 | If EndBit is greater than 7, then ASSERT().\r | |
175 | If EndBit is less than StartBit, then ASSERT().\r | |
176 | \r | |
177 | @param Address PCI configuration register to read.\r | |
178 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
179 | Range 0..7.\r | |
180 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
181 | Range 0..7.\r | |
182 | \r | |
183 | @return The value of the bit field read from the PCI configuration register.\r | |
184 | \r | |
185 | **/\r | |
186 | UINT8\r | |
187 | EFIAPI\r | |
188 | PciBitFieldRead8 (\r | |
189 | IN UINTN Address,\r | |
190 | IN UINTN StartBit,\r | |
191 | IN UINTN EndBit\r | |
192 | )\r | |
193 | {\r | |
194 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r | |
195 | }\r | |
196 | \r | |
197 | /**\r | |
198 | Writes a bit field to a PCI configuration register.\r | |
199 | \r | |
200 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
201 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
202 | destination PCI configuration register are preserved. The new value of the\r | |
203 | 8-bit register is returned.\r | |
204 | \r | |
205 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
206 | If StartBit is greater than 7, then ASSERT().\r | |
207 | If EndBit is greater than 7, then ASSERT().\r | |
208 | If EndBit is less than StartBit, then ASSERT().\r | |
209 | \r | |
210 | @param Address PCI configuration register to write.\r | |
211 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
212 | Range 0..7.\r | |
213 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
214 | Range 0..7.\r | |
215 | @param Value New value of the bit field.\r | |
216 | \r | |
217 | @return The value written back to the PCI configuration register.\r | |
218 | \r | |
219 | **/\r | |
220 | UINT8\r | |
221 | EFIAPI\r | |
222 | PciBitFieldWrite8 (\r | |
223 | IN UINTN Address,\r | |
224 | IN UINTN StartBit,\r | |
225 | IN UINTN EndBit,\r | |
226 | IN UINT8 Value\r | |
227 | )\r | |
228 | {\r | |
229 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
230 | }\r | |
231 | \r | |
232 | /**\r | |
233 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
234 | writes the result back to the bit field in the 8-bit port.\r | |
235 | \r | |
236 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
237 | bitwise inclusive OR between the read result and the value specified by\r | |
238 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
239 | specified by Address. The value written to the PCI configuration register is\r | |
240 | returned. This function must guarantee that all PCI read and write operations\r | |
241 | are serialized. Extra left bits in OrData are stripped.\r | |
242 | \r | |
243 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
244 | If StartBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is greater than 7, then ASSERT().\r | |
246 | If EndBit is less than StartBit, then ASSERT().\r | |
247 | \r | |
248 | @param Address PCI configuration register to write.\r | |
249 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
250 | Range 0..7.\r | |
251 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
252 | Range 0..7.\r | |
253 | @param OrData The value to OR with the PCI configuration register.\r | |
254 | \r | |
255 | @return The value written back to the PCI configuration register.\r | |
256 | \r | |
257 | **/\r | |
258 | UINT8\r | |
259 | EFIAPI\r | |
260 | PciBitFieldOr8 (\r | |
261 | IN UINTN Address,\r | |
262 | IN UINTN StartBit,\r | |
263 | IN UINTN EndBit,\r | |
264 | IN UINT8 OrData\r | |
265 | )\r | |
266 | {\r | |
267 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
268 | }\r | |
269 | \r | |
270 | /**\r | |
271 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
272 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
273 | \r | |
274 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
275 | bitwise AND between the read result and the value specified by AndData, and\r | |
276 | writes the result to the 8-bit PCI configuration register specified by\r | |
277 | Address. The value written to the PCI configuration register is returned.\r | |
278 | This function must guarantee that all PCI read and write operations are\r | |
279 | serialized. Extra left bits in AndData are stripped.\r | |
280 | \r | |
281 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
282 | If StartBit is greater than 7, then ASSERT().\r | |
283 | If EndBit is greater than 7, then ASSERT().\r | |
284 | If EndBit is less than StartBit, then ASSERT().\r | |
285 | \r | |
286 | @param Address PCI configuration register to write.\r | |
287 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
288 | Range 0..7.\r | |
289 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
290 | Range 0..7.\r | |
291 | @param AndData The value to AND with the PCI configuration register.\r | |
292 | \r | |
293 | @return The value written back to the PCI configuration register.\r | |
294 | \r | |
295 | **/\r | |
296 | UINT8\r | |
297 | EFIAPI\r | |
298 | PciBitFieldAnd8 (\r | |
299 | IN UINTN Address,\r | |
300 | IN UINTN StartBit,\r | |
301 | IN UINTN EndBit,\r | |
302 | IN UINT8 AndData\r | |
303 | )\r | |
304 | {\r | |
305 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
306 | }\r | |
307 | \r | |
308 | /**\r | |
309 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
310 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
311 | 8-bit port.\r | |
312 | \r | |
313 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
314 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
315 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
316 | configuration register specified by Address. The value written to the PCI\r | |
317 | configuration register is returned. This function must guarantee that all PCI\r | |
318 | read and write operations are serialized. Extra left bits in both AndData and\r | |
319 | OrData are stripped.\r | |
320 | \r | |
321 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
322 | If StartBit is greater than 7, then ASSERT().\r | |
323 | If EndBit is greater than 7, then ASSERT().\r | |
324 | If EndBit is less than StartBit, then ASSERT().\r | |
325 | \r | |
326 | @param Address PCI configuration register to write.\r | |
327 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
328 | Range 0..7.\r | |
329 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
330 | Range 0..7.\r | |
331 | @param AndData The value to AND with the PCI configuration register.\r | |
332 | @param OrData The value to OR with the result of the AND operation.\r | |
333 | \r | |
334 | @return The value written back to the PCI configuration register.\r | |
335 | \r | |
336 | **/\r | |
337 | UINT8\r | |
338 | EFIAPI\r | |
339 | PciBitFieldAndThenOr8 (\r | |
340 | IN UINTN Address,\r | |
341 | IN UINTN StartBit,\r | |
342 | IN UINTN EndBit,\r | |
343 | IN UINT8 AndData,\r | |
344 | IN UINT8 OrData\r | |
345 | )\r | |
346 | {\r | |
347 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
348 | }\r | |
349 | \r | |
350 | /**\r | |
351 | Reads a 16-bit PCI configuration register.\r | |
352 | \r | |
353 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
354 | This function must guarantee that all PCI read and write operations are\r | |
355 | serialized.\r | |
356 | \r | |
357 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
358 | \r | |
359 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
360 | Register.\r | |
361 | \r | |
362 | @return The read value from the PCI configuration register.\r | |
363 | \r | |
364 | **/\r | |
365 | UINT16\r | |
366 | EFIAPI\r | |
367 | PciRead16 (\r | |
368 | IN UINTN Address\r | |
369 | )\r | |
370 | {\r | |
371 | return PciExpressRead16 (Address);\r | |
372 | }\r | |
373 | \r | |
374 | /**\r | |
375 | Writes a 16-bit PCI configuration register.\r | |
376 | \r | |
377 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
378 | value specified by Value. Value is returned. This function must guarantee\r | |
379 | that all PCI read and write operations are serialized.\r | |
380 | \r | |
381 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
382 | \r | |
383 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
384 | Register.\r | |
385 | @param Value The value to write.\r | |
386 | \r | |
387 | @return The value written to the PCI configuration register.\r | |
388 | \r | |
389 | **/\r | |
390 | UINT16\r | |
391 | EFIAPI\r | |
392 | PciWrite16 (\r | |
393 | IN UINTN Address,\r | |
394 | IN UINT16 Data\r | |
395 | )\r | |
396 | {\r | |
397 | return PciExpressWrite16 (Address, Data);\r | |
398 | }\r | |
399 | \r | |
400 | /**\r | |
401 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
402 | a 16-bit value.\r | |
403 | \r | |
404 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
405 | bitwise inclusive OR between the read result and the value specified by\r | |
406 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
407 | specified by Address. The value written to the PCI configuration register is\r | |
408 | returned. This function must guarantee that all PCI read and write operations\r | |
409 | are serialized.\r | |
410 | \r | |
411 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
412 | \r | |
413 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
414 | Register.\r | |
415 | @param OrData The value to OR with the PCI configuration register.\r | |
416 | \r | |
417 | @return The value written back to the PCI configuration register.\r | |
418 | \r | |
419 | **/\r | |
420 | UINT16\r | |
421 | EFIAPI\r | |
422 | PciOr16 (\r | |
423 | IN UINTN Address,\r | |
424 | IN UINT16 OrData\r | |
425 | )\r | |
426 | {\r | |
427 | return PciExpressOr16 (Address, OrData);\r | |
428 | }\r | |
429 | \r | |
430 | /**\r | |
431 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
432 | value.\r | |
433 | \r | |
434 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
435 | bitwise AND between the read result and the value specified by AndData, and\r | |
436 | writes the result to the 16-bit PCI configuration register specified by\r | |
437 | Address. The value written to the PCI configuration register is returned.\r | |
438 | This function must guarantee that all PCI read and write operations are\r | |
439 | serialized.\r | |
440 | \r | |
441 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
442 | \r | |
443 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
444 | Register.\r | |
445 | @param AndData The value to AND with the PCI configuration register.\r | |
446 | \r | |
447 | @return The value written back to the PCI configuration register.\r | |
448 | \r | |
449 | **/\r | |
450 | UINT16\r | |
451 | EFIAPI\r | |
452 | PciAnd16 (\r | |
453 | IN UINTN Address,\r | |
454 | IN UINT16 AndData\r | |
455 | )\r | |
456 | {\r | |
457 | return PciExpressAnd16 (Address, AndData);\r | |
458 | }\r | |
459 | \r | |
460 | /**\r | |
461 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
462 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
463 | \r | |
464 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
465 | bitwise AND between the read result and the value specified by AndData,\r | |
466 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
467 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
468 | configuration register specified by Address. The value written to the PCI\r | |
469 | configuration register is returned. This function must guarantee that all PCI\r | |
470 | read and write operations are serialized.\r | |
471 | \r | |
472 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
473 | \r | |
474 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
475 | Register.\r | |
476 | @param AndData The value to AND with the PCI configuration register.\r | |
477 | @param OrData The value to OR with the result of the AND operation.\r | |
478 | \r | |
479 | @return The value written back to the PCI configuration register.\r | |
480 | \r | |
481 | **/\r | |
482 | UINT16\r | |
483 | EFIAPI\r | |
484 | PciAndThenOr16 (\r | |
485 | IN UINTN Address,\r | |
486 | IN UINT16 AndData,\r | |
487 | IN UINT16 OrData\r | |
488 | )\r | |
489 | {\r | |
490 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r | |
491 | }\r | |
492 | \r | |
493 | /**\r | |
494 | Reads a bit field of a PCI configuration register.\r | |
495 | \r | |
496 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
497 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
498 | returned.\r | |
499 | \r | |
500 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
501 | If StartBit is greater than 15, then ASSERT().\r | |
502 | If EndBit is greater than 15, then ASSERT().\r | |
503 | If EndBit is less than StartBit, then ASSERT().\r | |
504 | \r | |
505 | @param Address PCI configuration register to read.\r | |
506 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
507 | Range 0..15.\r | |
508 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
509 | Range 0..15.\r | |
510 | \r | |
511 | @return The value of the bit field read from the PCI configuration register.\r | |
512 | \r | |
513 | **/\r | |
514 | UINT16\r | |
515 | EFIAPI\r | |
516 | PciBitFieldRead16 (\r | |
517 | IN UINTN Address,\r | |
518 | IN UINTN StartBit,\r | |
519 | IN UINTN EndBit\r | |
520 | )\r | |
521 | {\r | |
522 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r | |
523 | }\r | |
524 | \r | |
525 | /**\r | |
526 | Writes a bit field to a PCI configuration register.\r | |
527 | \r | |
528 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
529 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
530 | destination PCI configuration register are preserved. The new value of the\r | |
531 | 16-bit register is returned.\r | |
532 | \r | |
533 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
534 | If StartBit is greater than 15, then ASSERT().\r | |
535 | If EndBit is greater than 15, then ASSERT().\r | |
536 | If EndBit is less than StartBit, then ASSERT().\r | |
537 | \r | |
538 | @param Address PCI configuration register to write.\r | |
539 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
540 | Range 0..15.\r | |
541 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
542 | Range 0..15.\r | |
543 | @param Value New value of the bit field.\r | |
544 | \r | |
545 | @return The value written back to the PCI configuration register.\r | |
546 | \r | |
547 | **/\r | |
548 | UINT16\r | |
549 | EFIAPI\r | |
550 | PciBitFieldWrite16 (\r | |
551 | IN UINTN Address,\r | |
552 | IN UINTN StartBit,\r | |
553 | IN UINTN EndBit,\r | |
554 | IN UINT16 Value\r | |
555 | )\r | |
556 | {\r | |
557 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
558 | }\r | |
559 | \r | |
560 | /**\r | |
561 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
562 | writes the result back to the bit field in the 16-bit port.\r | |
563 | \r | |
564 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
565 | bitwise inclusive OR between the read result and the value specified by\r | |
566 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
567 | specified by Address. The value written to the PCI configuration register is\r | |
568 | returned. This function must guarantee that all PCI read and write operations\r | |
569 | are serialized. Extra left bits in OrData are stripped.\r | |
570 | \r | |
571 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
572 | If StartBit is greater than 15, then ASSERT().\r | |
573 | If EndBit is greater than 15, then ASSERT().\r | |
574 | If EndBit is less than StartBit, then ASSERT().\r | |
575 | \r | |
576 | @param Address PCI configuration register to write.\r | |
577 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
578 | Range 0..15.\r | |
579 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
580 | Range 0..15.\r | |
581 | @param OrData The value to OR with the PCI configuration register.\r | |
582 | \r | |
583 | @return The value written back to the PCI configuration register.\r | |
584 | \r | |
585 | **/\r | |
586 | UINT16\r | |
587 | EFIAPI\r | |
588 | PciBitFieldOr16 (\r | |
589 | IN UINTN Address,\r | |
590 | IN UINTN StartBit,\r | |
591 | IN UINTN EndBit,\r | |
592 | IN UINT16 OrData\r | |
593 | )\r | |
594 | {\r | |
595 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
596 | }\r | |
597 | \r | |
598 | /**\r | |
599 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
600 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
601 | \r | |
602 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
603 | bitwise AND between the read result and the value specified by AndData, and\r | |
604 | writes the result to the 16-bit PCI configuration register specified by\r | |
605 | Address. The value written to the PCI configuration register is returned.\r | |
606 | This function must guarantee that all PCI read and write operations are\r | |
607 | serialized. Extra left bits in AndData are stripped.\r | |
608 | \r | |
609 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
610 | If StartBit is greater than 15, then ASSERT().\r | |
611 | If EndBit is greater than 15, then ASSERT().\r | |
612 | If EndBit is less than StartBit, then ASSERT().\r | |
613 | \r | |
614 | @param Address PCI configuration register to write.\r | |
615 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
616 | Range 0..15.\r | |
617 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
618 | Range 0..15.\r | |
619 | @param AndData The value to AND with the PCI configuration register.\r | |
620 | \r | |
621 | @return The value written back to the PCI configuration register.\r | |
622 | \r | |
623 | **/\r | |
624 | UINT16\r | |
625 | EFIAPI\r | |
626 | PciBitFieldAnd16 (\r | |
627 | IN UINTN Address,\r | |
628 | IN UINTN StartBit,\r | |
629 | IN UINTN EndBit,\r | |
630 | IN UINT16 AndData\r | |
631 | )\r | |
632 | {\r | |
633 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
634 | }\r | |
635 | \r | |
636 | /**\r | |
637 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
638 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
639 | 16-bit port.\r | |
640 | \r | |
641 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
642 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
643 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
644 | configuration register specified by Address. The value written to the PCI\r | |
645 | configuration register is returned. This function must guarantee that all PCI\r | |
646 | read and write operations are serialized. Extra left bits in both AndData and\r | |
647 | OrData are stripped.\r | |
648 | \r | |
649 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
650 | If StartBit is greater than 15, then ASSERT().\r | |
651 | If EndBit is greater than 15, then ASSERT().\r | |
652 | If EndBit is less than StartBit, then ASSERT().\r | |
653 | \r | |
654 | @param Address PCI configuration register to write.\r | |
655 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
656 | Range 0..15.\r | |
657 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
658 | Range 0..15.\r | |
659 | @param AndData The value to AND with the PCI configuration register.\r | |
660 | @param OrData The value to OR with the result of the AND operation.\r | |
661 | \r | |
662 | @return The value written back to the PCI configuration register.\r | |
663 | \r | |
664 | **/\r | |
665 | UINT16\r | |
666 | EFIAPI\r | |
667 | PciBitFieldAndThenOr16 (\r | |
668 | IN UINTN Address,\r | |
669 | IN UINTN StartBit,\r | |
670 | IN UINTN EndBit,\r | |
671 | IN UINT16 AndData,\r | |
672 | IN UINT16 OrData\r | |
673 | )\r | |
674 | {\r | |
675 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
676 | }\r | |
677 | \r | |
678 | /**\r | |
679 | Reads a 32-bit PCI configuration register.\r | |
680 | \r | |
681 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
682 | This function must guarantee that all PCI read and write operations are\r | |
683 | serialized.\r | |
684 | \r | |
685 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
686 | \r | |
687 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
688 | Register.\r | |
689 | \r | |
690 | @return The read value from the PCI configuration register.\r | |
691 | \r | |
692 | **/\r | |
693 | UINT32\r | |
694 | EFIAPI\r | |
695 | PciRead32 (\r | |
696 | IN UINTN Address\r | |
697 | )\r | |
698 | {\r | |
699 | return PciExpressRead32 (Address);\r | |
700 | }\r | |
701 | \r | |
702 | /**\r | |
703 | Writes a 32-bit PCI configuration register.\r | |
704 | \r | |
705 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
706 | value specified by Value. Value is returned. This function must guarantee\r | |
707 | that all PCI read and write operations are serialized.\r | |
708 | \r | |
709 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
710 | \r | |
711 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
712 | Register.\r | |
713 | @param Value The value to write.\r | |
714 | \r | |
715 | @return The value written to the PCI configuration register.\r | |
716 | \r | |
717 | **/\r | |
718 | UINT32\r | |
719 | EFIAPI\r | |
720 | PciWrite32 (\r | |
721 | IN UINTN Address,\r | |
722 | IN UINT32 Data\r | |
723 | )\r | |
724 | {\r | |
725 | return PciExpressWrite32 (Address, Data);\r | |
726 | }\r | |
727 | \r | |
728 | /**\r | |
729 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
730 | a 32-bit value.\r | |
731 | \r | |
732 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
733 | bitwise inclusive OR between the read result and the value specified by\r | |
734 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
735 | specified by Address. The value written to the PCI configuration register is\r | |
736 | returned. This function must guarantee that all PCI read and write operations\r | |
737 | are serialized.\r | |
738 | \r | |
739 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
740 | \r | |
741 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
742 | Register.\r | |
743 | @param OrData The value to OR with the PCI configuration register.\r | |
744 | \r | |
745 | @return The value written back to the PCI configuration register.\r | |
746 | \r | |
747 | **/\r | |
748 | UINT32\r | |
749 | EFIAPI\r | |
750 | PciOr32 (\r | |
751 | IN UINTN Address,\r | |
752 | IN UINT32 OrData\r | |
753 | )\r | |
754 | {\r | |
755 | return PciExpressOr32 (Address, OrData);\r | |
756 | }\r | |
757 | \r | |
758 | /**\r | |
759 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
760 | value.\r | |
761 | \r | |
762 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
763 | bitwise AND between the read result and the value specified by AndData, and\r | |
764 | writes the result to the 32-bit PCI configuration register specified by\r | |
765 | Address. The value written to the PCI configuration register is returned.\r | |
766 | This function must guarantee that all PCI read and write operations are\r | |
767 | serialized.\r | |
768 | \r | |
769 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
770 | \r | |
771 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
772 | Register.\r | |
773 | @param AndData The value to AND with the PCI configuration register.\r | |
774 | \r | |
775 | @return The value written back to the PCI configuration register.\r | |
776 | \r | |
777 | **/\r | |
778 | UINT32\r | |
779 | EFIAPI\r | |
780 | PciAnd32 (\r | |
781 | IN UINTN Address,\r | |
782 | IN UINT32 AndData\r | |
783 | )\r | |
784 | {\r | |
785 | return PciExpressAnd32 (Address, AndData);\r | |
786 | }\r | |
787 | \r | |
788 | /**\r | |
789 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
790 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
791 | \r | |
792 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
793 | bitwise AND between the read result and the value specified by AndData,\r | |
794 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
795 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
796 | configuration register specified by Address. The value written to the PCI\r | |
797 | configuration register is returned. This function must guarantee that all PCI\r | |
798 | read and write operations are serialized.\r | |
799 | \r | |
800 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
801 | \r | |
802 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
803 | Register.\r | |
804 | @param AndData The value to AND with the PCI configuration register.\r | |
805 | @param OrData The value to OR with the result of the AND operation.\r | |
806 | \r | |
807 | @return The value written back to the PCI configuration register.\r | |
808 | \r | |
809 | **/\r | |
810 | UINT32\r | |
811 | EFIAPI\r | |
812 | PciAndThenOr32 (\r | |
813 | IN UINTN Address,\r | |
814 | IN UINT32 AndData,\r | |
815 | IN UINT32 OrData\r | |
816 | )\r | |
817 | {\r | |
818 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r | |
819 | }\r | |
820 | \r | |
821 | /**\r | |
822 | Reads a bit field of a PCI configuration register.\r | |
823 | \r | |
824 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
825 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
826 | returned.\r | |
827 | \r | |
828 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
829 | If StartBit is greater than 31, then ASSERT().\r | |
830 | If EndBit is greater than 31, then ASSERT().\r | |
831 | If EndBit is less than StartBit, then ASSERT().\r | |
832 | \r | |
833 | @param Address PCI configuration register to read.\r | |
834 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
835 | Range 0..31.\r | |
836 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
837 | Range 0..31.\r | |
838 | \r | |
839 | @return The value of the bit field read from the PCI configuration register.\r | |
840 | \r | |
841 | **/\r | |
842 | UINT32\r | |
843 | EFIAPI\r | |
844 | PciBitFieldRead32 (\r | |
845 | IN UINTN Address,\r | |
846 | IN UINTN StartBit,\r | |
847 | IN UINTN EndBit\r | |
848 | )\r | |
849 | {\r | |
850 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r | |
851 | }\r | |
852 | \r | |
853 | /**\r | |
854 | Writes a bit field to a PCI configuration register.\r | |
855 | \r | |
856 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
857 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
858 | destination PCI configuration register are preserved. The new value of the\r | |
859 | 32-bit register is returned.\r | |
860 | \r | |
861 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
862 | If StartBit is greater than 31, then ASSERT().\r | |
863 | If EndBit is greater than 31, then ASSERT().\r | |
864 | If EndBit is less than StartBit, then ASSERT().\r | |
865 | \r | |
866 | @param Address PCI configuration register to write.\r | |
867 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
868 | Range 0..31.\r | |
869 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
870 | Range 0..31.\r | |
871 | @param Value New value of the bit field.\r | |
872 | \r | |
873 | @return The value written back to the PCI configuration register.\r | |
874 | \r | |
875 | **/\r | |
876 | UINT32\r | |
877 | EFIAPI\r | |
878 | PciBitFieldWrite32 (\r | |
879 | IN UINTN Address,\r | |
880 | IN UINTN StartBit,\r | |
881 | IN UINTN EndBit,\r | |
882 | IN UINT32 Value\r | |
883 | )\r | |
884 | {\r | |
885 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
886 | }\r | |
887 | \r | |
888 | /**\r | |
889 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
890 | writes the result back to the bit field in the 32-bit port.\r | |
891 | \r | |
892 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
893 | bitwise inclusive OR between the read result and the value specified by\r | |
894 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
895 | specified by Address. The value written to the PCI configuration register is\r | |
896 | returned. This function must guarantee that all PCI read and write operations\r | |
897 | are serialized. Extra left bits in OrData are stripped.\r | |
898 | \r | |
899 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
900 | If StartBit is greater than 31, then ASSERT().\r | |
901 | If EndBit is greater than 31, then ASSERT().\r | |
902 | If EndBit is less than StartBit, then ASSERT().\r | |
903 | \r | |
904 | @param Address PCI configuration register to write.\r | |
905 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
906 | Range 0..31.\r | |
907 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
908 | Range 0..31.\r | |
909 | @param OrData The value to OR with the PCI configuration register.\r | |
910 | \r | |
911 | @return The value written back to the PCI configuration register.\r | |
912 | \r | |
913 | **/\r | |
914 | UINT32\r | |
915 | EFIAPI\r | |
916 | PciBitFieldOr32 (\r | |
917 | IN UINTN Address,\r | |
918 | IN UINTN StartBit,\r | |
919 | IN UINTN EndBit,\r | |
920 | IN UINT32 OrData\r | |
921 | )\r | |
922 | {\r | |
923 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
924 | }\r | |
925 | \r | |
926 | /**\r | |
927 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
928 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
929 | \r | |
930 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
931 | bitwise AND between the read result and the value specified by AndData, and\r | |
932 | writes the result to the 32-bit PCI configuration register specified by\r | |
933 | Address. The value written to the PCI configuration register is returned.\r | |
934 | This function must guarantee that all PCI read and write operations are\r | |
935 | serialized. Extra left bits in AndData are stripped.\r | |
936 | \r | |
937 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
938 | If StartBit is greater than 31, then ASSERT().\r | |
939 | If EndBit is greater than 31, then ASSERT().\r | |
940 | If EndBit is less than StartBit, then ASSERT().\r | |
941 | \r | |
942 | @param Address PCI configuration register to write.\r | |
943 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
944 | Range 0..31.\r | |
945 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
946 | Range 0..31.\r | |
947 | @param AndData The value to AND with the PCI configuration register.\r | |
948 | \r | |
949 | @return The value written back to the PCI configuration register.\r | |
950 | \r | |
951 | **/\r | |
952 | UINT32\r | |
953 | EFIAPI\r | |
954 | PciBitFieldAnd32 (\r | |
955 | IN UINTN Address,\r | |
956 | IN UINTN StartBit,\r | |
957 | IN UINTN EndBit,\r | |
958 | IN UINT32 AndData\r | |
959 | )\r | |
960 | {\r | |
961 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
962 | }\r | |
963 | \r | |
964 | /**\r | |
965 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
966 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
967 | 32-bit port.\r | |
968 | \r | |
969 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
970 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
971 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
972 | configuration register specified by Address. The value written to the PCI\r | |
973 | configuration register is returned. This function must guarantee that all PCI\r | |
974 | read and write operations are serialized. Extra left bits in both AndData and\r | |
975 | OrData are stripped.\r | |
976 | \r | |
977 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
978 | If StartBit is greater than 31, then ASSERT().\r | |
979 | If EndBit is greater than 31, then ASSERT().\r | |
980 | If EndBit is less than StartBit, then ASSERT().\r | |
981 | \r | |
982 | @param Address PCI configuration register to write.\r | |
983 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
984 | Range 0..31.\r | |
985 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
986 | Range 0..31.\r | |
987 | @param AndData The value to AND with the PCI configuration register.\r | |
988 | @param OrData The value to OR with the result of the AND operation.\r | |
989 | \r | |
990 | @return The value written back to the PCI configuration register.\r | |
991 | \r | |
992 | **/\r | |
993 | UINT32\r | |
994 | EFIAPI\r | |
995 | PciBitFieldAndThenOr32 (\r | |
996 | IN UINTN Address,\r | |
997 | IN UINTN StartBit,\r | |
998 | IN UINTN EndBit,\r | |
999 | IN UINT32 AndData,\r | |
1000 | IN UINT32 OrData\r | |
1001 | )\r | |
1002 | {\r | |
1003 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
1004 | }\r | |
1005 | \r | |
1006 | /**\r | |
1007 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1008 | \r | |
1009 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1010 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1011 | configuration registers from a single PCI function to be read. Size is\r | |
1012 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1013 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1014 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1015 | end of the range.\r | |
1016 | \r | |
1017 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1018 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1019 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1020 | \r | |
1021 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1022 | Function and Register.\r | |
1023 | @param Size Size in bytes of the transfer.\r | |
1024 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1025 | \r | |
1026 | @return Size\r | |
1027 | \r | |
1028 | **/\r | |
1029 | UINTN\r | |
1030 | EFIAPI\r | |
1031 | PciReadBuffer (\r | |
1032 | IN UINTN StartAddress,\r | |
1033 | IN UINTN Size,\r | |
1034 | OUT VOID *Buffer\r | |
1035 | )\r | |
1036 | {\r | |
1037 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r | |
1038 | }\r | |
1039 | \r | |
1040 | /**\r | |
1041 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1042 | configuration space.\r | |
1043 | \r | |
1044 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1045 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1046 | configuration registers from a single PCI function to be written. Size is\r | |
1047 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1048 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1049 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1050 | and the end of the range.\r | |
1051 | \r | |
1052 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1053 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1054 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1055 | \r | |
1056 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1057 | Function and Register.\r | |
1058 | @param Size Size in bytes of the transfer.\r | |
1059 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1060 | \r | |
1061 | @return Size\r | |
1062 | \r | |
1063 | **/\r | |
1064 | UINTN\r | |
1065 | EFIAPI\r | |
1066 | PciWriteBuffer (\r | |
1067 | IN UINTN StartAddress,\r | |
1068 | IN UINTN Size,\r | |
1069 | IN VOID *Buffer\r | |
1070 | )\r | |
1071 | {\r | |
1072 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r | |
1073 | }\r |