[mirror_edk2.git] / MdePkg / Library / BaseS3PciLib / S3PciLib.c

/** @file\r
  PCI configuration Library Services that do PCI configuration and also enable\r
  the PCI operations to be replayed during an S3 resume. This library class\r
  maps directly on top of the PciLib class.\r
\r
  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Base.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/S3BootScriptLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/S3PciLib.h>\r
\r
#define PCILIB_TO_COMMON_ADDRESS(Address) \\r
        ((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((Address>>15) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((UINTN) (Address & 0xfff )))\r
\r
/**\r
  Saves a PCI configuration value to the boot script.\r
\r
  This internal worker function saves a PCI configuration value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Width   The width of PCI configuration.\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Buffer  The buffer containing value.\r
\r
**/\r
VOID\r
InternalSavePciWriteValueToBootScript (\r
  IN S3_BOOT_SCRIPT_LIB_WIDTH  Width,\r
  IN UINTN                     Address,\r
  IN VOID                      *Buffer\r
  )\r
{\r
  RETURN_STATUS  Status;\r
\r
  Status = S3BootScriptSavePciCfgWrite (\r
             Width,\r
             PCILIB_TO_COMMON_ADDRESS (Address),\r
             1,\r
             Buffer\r
             );\r
  ASSERT (Status == RETURN_SUCCESS);\r
}\r
\r
/**\r
  Saves an 8-bit PCI configuration value to the boot script.\r
\r
  This internal worker function saves an 8-bit PCI configuration value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value saved to boot script.\r
\r
  @return Value.\r
\r
**/\r
UINT8\r
InternalSavePciWrite8ValueToBootScript (\r
  IN UINTN  Address,\r
  IN UINT8  Value\r
  )\r
{\r
  InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r
\r
  return Value;\r
}\r
\r
/**\r
  Reads an 8-bit PCI configuration register and saves the value in the S3\r
  script to be replayed on S3 resume.\r
\r
  Reads and returns the 8-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
\r
  @return The read value from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciRead8 (\r
  IN UINTN  Address\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciRead8 (Address));\r
}\r
\r
/**\r
  Writes an 8-bit PCI configuration register and saves the value in the S3\r
  script to be replayed on S3 resume.\r
\r
  Writes the 8-bit PCI configuration register specified by Address with the\r
  value specified by Value. Value is returned. This function must guarantee\r
  that all PCI read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciWrite8 (\r
  IN UINTN  Address,\r
  IN UINT8  Value\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciWrite8 (Address, Value));\r
}\r
\r
/**\r
  Performs a bitwise OR of an 8-bit PCI configuration register with\r
  an 8-bit value and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 8-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  OrData  The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciOr8 (\r
  IN UINTN  Address,\r
  IN UINT8  OrData\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciOr8 (Address, OrData));\r
}\r
\r
/**\r
  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
  value and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 8-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciAnd8 (\r
  IN UINTN  Address,\r
  IN UINT8  AndData\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciAnd8 (Address, AndData));\r
}\r
\r
/**\r
  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
  value, followed a  bitwise OR with another 8-bit value and saves\r
  the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and\r
  the value specified by OrData, and writes the result to the 8-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
  @param  OrData  The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciAndThenOr8 (\r
  IN UINTN  Address,\r
  IN UINT8  AndData,\r
  IN UINT8  OrData\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciAndThenOr8 (Address, AndData, OrData));\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciBitFieldRead8 (\r
  IN UINTN  Address,\r
  IN UINTN  StartBit,\r
  IN UINTN  EndBit\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldRead8 (Address, StartBit, EndBit));\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  8-bit register is returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciBitFieldWrite8 (\r
  IN UINTN  Address,\r
  IN UINTN  StartBit,\r
  IN UINTN  EndBit,\r
  IN UINT8  Value\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldWrite8 (Address, StartBit, EndBit, Value));\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
  writes the result back to the bit field in the 8-bit port and saves the value\r
  in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 8-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciBitFieldOr8 (\r
  IN UINTN  Address,\r
  IN UINTN  StartBit,\r
  IN UINTN  EndBit,\r
  IN UINT8  OrData\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldOr8 (Address, StartBit, EndBit, OrData));\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
  AND, and writes the result back to the bit field in the 8-bit register and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 8-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciBitFieldAnd8 (\r
  IN UINTN  Address,\r
  IN UINTN  StartBit,\r
  IN UINTN  EndBit,\r
  IN UINT8  AndData\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a\r
  bitwise OR, and writes the result back to the bit field in the\r
  8-bit port and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 8-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciBitFieldAndThenOr8 (\r
  IN UINTN  Address,\r
  IN UINTN  StartBit,\r
  IN UINTN  EndBit,\r
  IN UINT8  AndData,\r
  IN UINT8  OrData\r
  )\r
{\r
  return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r
}\r
\r
/**\r
  Saves a 16-bit PCI configuration value to the boot script.\r
\r
  This internal worker function saves a 16-bit PCI configuration value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return Value.\r
\r
**/\r
UINT16\r
InternalSavePciWrite16ValueToBootScript (\r
  IN UINTN   Address,\r
  IN UINT16  Value\r
  )\r
{\r
  InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r
\r
  return Value;\r
}\r
\r
/**\r
  Reads a 16-bit PCI configuration register and saves the value in the S3\r
  script to be replayed on S3 resume.\r
\r
  Reads and returns the 16-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
\r
  @return The read value from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciRead16 (\r
  IN UINTN  Address\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciRead16 (Address));\r
}\r
\r
/**\r
  Writes a 16-bit PCI configuration register and saves the value in the S3\r
  script to be replayed on S3 resume.\r
\r
  Writes the 16-bit PCI configuration register specified by Address with the\r
  value specified by Value. Value is returned. This function must guarantee\r
  that all PCI read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciWrite16 (\r
  IN UINTN   Address,\r
  IN UINT16  Value\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciWrite16 (Address, Value));\r
}\r
\r
/**\r
  Performs a bitwise OR of a 16-bit PCI configuration register with\r
  a 16-bit value and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 16-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  OrData  The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciOr16 (\r
  IN UINTN   Address,\r
  IN UINT16  OrData\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciOr16 (Address, OrData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
  value and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 16-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciAnd16 (\r
  IN UINTN   Address,\r
  IN UINT16  AndData\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciAnd16 (Address, AndData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
  value, followed a  bitwise OR with another 16-bit value and saves\r
  the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and\r
  the value specified by OrData, and writes the result to the 16-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
  @param  OrData  The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciAndThenOr16 (\r
  IN UINTN   Address,\r
  IN UINT16  AndData,\r
  IN UINT16  OrData\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciAndThenOr16 (Address, AndData, OrData));\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciBitFieldRead16 (\r
  IN UINTN  Address,\r
  IN UINTN  StartBit,\r
  IN UINTN  EndBit\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldRead16 (Address, StartBit, EndBit));\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  16-bit register is returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciBitFieldWrite16 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT16  Value\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldWrite16 (Address, StartBit, EndBit, Value));\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
  writes the result back to the bit field in the 16-bit port and saves the value\r
  in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 16-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciBitFieldOr16 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT16  OrData\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldOr16 (Address, StartBit, EndBit, OrData));\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
  AND, and writes the result back to the bit field in the 16-bit register and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 16-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciBitFieldAnd16 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT16  AndData\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a\r
  bitwise OR, and writes the result back to the bit field in the\r
  16-bit port and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 16-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciBitFieldAndThenOr16 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT16  AndData,\r
  IN UINT16  OrData\r
  )\r
{\r
  return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r
}\r
\r
/**\r
  Saves a 32-bit PCI configuration value to the boot script.\r
\r
  This internal worker function saves a 32-bit PCI configuration value in the S3 script\r
  to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return Value.\r
\r
**/\r
UINT32\r
InternalSavePciWrite32ValueToBootScript (\r
  IN UINTN   Address,\r
  IN UINT32  Value\r
  )\r
{\r
  InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r
\r
  return Value;\r
}\r
\r
/**\r
  Reads a 32-bit PCI configuration register and saves the value in the S3\r
  script to be replayed on S3 resume.\r
\r
  Reads and returns the 32-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
\r
  @return The read value from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciRead32 (\r
  IN UINTN  Address\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciRead32 (Address));\r
}\r
\r
/**\r
  Writes a 32-bit PCI configuration register and saves the value in the S3\r
  script to be replayed on S3 resume.\r
\r
  Writes the 32-bit PCI configuration register specified by Address with the\r
  value specified by Value. Value is returned. This function must guarantee\r
  that all PCI read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciWrite32 (\r
  IN UINTN   Address,\r
  IN UINT32  Value\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciWrite32 (Address, Value));\r
}\r
\r
/**\r
  Performs a bitwise OR of a 32-bit PCI configuration register with\r
  a 32-bit value and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 32-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  OrData  The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciOr32 (\r
  IN UINTN   Address,\r
  IN UINT32  OrData\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciOr32 (Address, OrData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
  value and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 32-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciAnd32 (\r
  IN UINTN   Address,\r
  IN UINT32  AndData\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciAnd32 (Address, AndData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
  value, followed a  bitwise OR with another 32-bit value and saves\r
  the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and\r
  the value specified by OrData, and writes the result to the 32-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
  @param  OrData  The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciAndThenOr32 (\r
  IN UINTN   Address,\r
  IN UINT32  AndData,\r
  IN UINT32  OrData\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciAndThenOr32 (Address, AndData, OrData));\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciBitFieldRead32 (\r
  IN UINTN  Address,\r
  IN UINTN  StartBit,\r
  IN UINTN  EndBit\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldRead32 (Address, StartBit, EndBit));\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  32-bit register is returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciBitFieldWrite32 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT32  Value\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldWrite32 (Address, StartBit, EndBit, Value));\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
  writes the result back to the bit field in the 32-bit port and saves the value\r
  in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 32-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciBitFieldOr32 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT32  OrData\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldOr32 (Address, StartBit, EndBit, OrData));\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
  AND, and writes the result back to the bit field in the 32-bit register and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 32-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciBitFieldAnd32 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT32  AndData\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a\r
  bitwise OR, and writes the result back to the bit field in the\r
  32-bit port and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 32-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciBitFieldAndThenOr32 (\r
  IN UINTN   Address,\r
  IN UINTN   StartBit,\r
  IN UINTN   EndBit,\r
  IN UINT32  AndData,\r
  IN UINT32  OrData\r
  )\r
{\r
  return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r
}\r
\r
/**\r
  Reads a range of PCI configuration registers into a caller supplied buffer\r
  and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the range of PCI configuration registers specified by StartAddress and\r
  Size into the buffer specified by Buffer. This function only allows the PCI\r
  configuration registers from a single PCI function to be read. Size is\r
  returned. When possible 32-bit PCI configuration read cycles are used to read\r
  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
  and 16-bit PCI configuration read cycles may be used at the beginning and the\r
  end of the range.\r
\r
  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
  If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                        Function and Register.\r
  @param  Size          Size in bytes of the transfer.\r
  @param  Buffer        Pointer to a buffer receiving the data read.\r
\r
  @return Size\r
\r
**/\r
UINTN\r
EFIAPI\r
S3PciReadBuffer (\r
  IN  UINTN  StartAddress,\r
  IN  UINTN  Size,\r
  OUT VOID   *Buffer\r
  )\r
{\r
  RETURN_STATUS  Status;\r
\r
  Status = S3BootScriptSavePciCfgWrite (\r
             S3BootScriptWidthUint8,\r
             PCILIB_TO_COMMON_ADDRESS (StartAddress),\r
             PciReadBuffer (StartAddress, Size, Buffer),\r
             Buffer\r
             );\r
  ASSERT (Status == RETURN_SUCCESS);\r
\r
  return Size;\r
}\r
\r
/**\r
  Copies the data in a caller supplied buffer to a specified range of PCI\r
  configuration space and saves the value in the S3 script to be replayed on S3\r
  resume.\r
\r
  Writes the range of PCI configuration registers specified by StartAddress and\r
  Size from the buffer specified by Buffer. This function only allows the PCI\r
  configuration registers from a single PCI function to be written. Size is\r
  returned. When possible 32-bit PCI configuration write cycles are used to\r
  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
  8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
  and the end of the range.\r
\r
  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
  If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                        Function and Register.\r
  @param  Size          Size in bytes of the transfer.\r
  @param  Buffer        Pointer to a buffer containing the data to write.\r
\r
  @return Size\r
\r
**/\r
UINTN\r
EFIAPI\r
S3PciWriteBuffer (\r
  IN UINTN  StartAddress,\r
  IN UINTN  Size,\r
  IN VOID   *Buffer\r
  )\r
{\r
  RETURN_STATUS  Status;\r
\r
  Status = S3BootScriptSavePciCfgWrite (\r
             S3BootScriptWidthUint8,\r
             PCILIB_TO_COMMON_ADDRESS (StartAddress),\r
             PciWriteBuffer (StartAddress, Size, Buffer),\r
             Buffer\r
             );\r
  ASSERT (Status == RETURN_SUCCESS);\r
\r
  return Size;\r
}\r