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a2285a89 RN |
1 | /** @file\r |
2 | The multiple segments PCI configuration Library Services that carry out\r | |
3 | PCI configuration and enable the PCI operations to be replayed during an\r | |
4 | S3 resume. This library class maps directly on top of the PciSegmentLib class.\r | |
5 | \r | |
6 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a2285a89 RN |
8 | \r |
9 | **/\r | |
10 | \r | |
a2285a89 RN |
11 | #include <Base.h>\r |
12 | \r | |
13 | #include <Library/DebugLib.h>\r | |
14 | #include <Library/S3BootScriptLib.h>\r | |
15 | #include <Library/PciSegmentLib.h>\r | |
16 | \r | |
17 | /**\r | |
18 | Macro that converts address in PciSegmentLib format to the new address that can be pass\r | |
19 | to the S3 Boot Script Library functions. The Segment is dropped.\r | |
20 | \r | |
21 | @param Address Address in PciSegmentLib format.\r | |
22 | \r | |
23 | @retval New address that can be pass to the S3 Boot Script Library functions.\r | |
24 | **/\r | |
25 | #define PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS(Address) \\r | |
26 | ((((UINT32)(Address) >> 20) & 0xff) << 24) | \\r | |
27 | ((((UINT32)(Address) >> 15) & 0x1f) << 16) | \\r | |
28 | ((((UINT32)(Address) >> 12) & 0x07) << 8) | \\r | |
29 | LShiftU64 ((Address) & 0xfff, 32) // Always put Register in high four bytes.\r | |
30 | \r | |
31 | /**\r | |
32 | Saves a PCI configuration value to the boot script.\r | |
33 | \r | |
34 | This internal worker function saves a PCI configuration value in\r | |
35 | the S3 script to be replayed on S3 resume.\r | |
36 | \r | |
37 | If the saving process fails, then ASSERT().\r | |
38 | \r | |
39 | @param Width The width of PCI configuration.\r | |
40 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
41 | Register.\r | |
42 | @param Buffer The buffer containing value.\r | |
43 | \r | |
44 | **/\r | |
45 | VOID\r | |
46 | InternalSavePciSegmentWriteValueToBootScript (\r | |
47 | IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r | |
2f88bd3a MK |
48 | IN UINT64 Address,\r |
49 | IN VOID *Buffer\r | |
a2285a89 RN |
50 | )\r |
51 | {\r | |
2f88bd3a | 52 | RETURN_STATUS Status;\r |
a2285a89 RN |
53 | \r |
54 | Status = S3BootScriptSavePciCfg2Write (\r | |
55 | Width,\r | |
56 | RShiftU64 ((Address), 32) & 0xffff,\r | |
57 | PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (Address),\r | |
58 | 1,\r | |
59 | Buffer\r | |
60 | );\r | |
61 | ASSERT_RETURN_ERROR (Status);\r | |
62 | }\r | |
63 | \r | |
64 | /**\r | |
65 | Saves an 8-bit PCI configuration value to the boot script.\r | |
66 | \r | |
67 | This internal worker function saves an 8-bit PCI configuration value in\r | |
68 | the S3 script to be replayed on S3 resume.\r | |
69 | \r | |
70 | If the saving process fails, then ASSERT().\r | |
71 | \r | |
72 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
73 | Register.\r | |
74 | @param Value The value saved to boot script.\r | |
75 | \r | |
76 | @return Value.\r | |
77 | \r | |
78 | **/\r | |
79 | UINT8\r | |
80 | InternalSavePciSegmentWrite8ValueToBootScript (\r | |
2f88bd3a MK |
81 | IN UINT64 Address,\r |
82 | IN UINT8 Value\r | |
a2285a89 RN |
83 | )\r |
84 | {\r | |
85 | InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r | |
86 | \r | |
87 | return Value;\r | |
88 | }\r | |
89 | \r | |
90 | /**\r | |
91 | Reads an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
92 | be replayed on S3 resume.\r | |
93 | \r | |
94 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
95 | This function must guarantee that all PCI read and write operations are serialized.\r | |
96 | \r | |
97 | If any reserved bits in Address are set, then ASSERT().\r | |
98 | \r | |
99 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
100 | \r | |
101 | @return The 8-bit PCI configuration register specified by Address.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT8\r | |
105 | EFIAPI\r | |
106 | S3PciSegmentRead8 (\r | |
2f88bd3a | 107 | IN UINT64 Address\r |
a2285a89 RN |
108 | )\r |
109 | {\r | |
110 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentRead8 (Address));\r | |
111 | }\r | |
112 | \r | |
113 | /**\r | |
114 | Writes an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
115 | be replayed on S3 resume.\r | |
116 | \r | |
117 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
118 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
119 | \r | |
120 | If any reserved bits in Address are set, then ASSERT().\r | |
121 | \r | |
122 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
123 | @param Value The value to write.\r | |
124 | \r | |
125 | @return The value written to the PCI configuration register.\r | |
126 | \r | |
127 | **/\r | |
128 | UINT8\r | |
129 | EFIAPI\r | |
130 | S3PciSegmentWrite8 (\r | |
2f88bd3a MK |
131 | IN UINT64 Address,\r |
132 | IN UINT8 Value\r | |
a2285a89 RN |
133 | )\r |
134 | {\r | |
135 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentWrite8 (Address, Value));\r | |
136 | }\r | |
137 | \r | |
138 | /**\r | |
139 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves\r | |
140 | the value in the S3 script to be replayed on S3 resume.\r | |
141 | \r | |
142 | Reads the 8-bit PCI configuration register specified by Address,\r | |
143 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
144 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
145 | The value written to the PCI configuration register is returned.\r | |
146 | This function must guarantee that all PCI read and write operations are serialized.\r | |
147 | \r | |
148 | If any reserved bits in Address are set, then ASSERT().\r | |
149 | \r | |
150 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
151 | @param OrData The value to OR with the PCI configuration register.\r | |
152 | \r | |
153 | @return The value written to the PCI configuration register.\r | |
154 | \r | |
155 | **/\r | |
156 | UINT8\r | |
157 | EFIAPI\r | |
158 | S3PciSegmentOr8 (\r | |
2f88bd3a MK |
159 | IN UINT64 Address,\r |
160 | IN UINT8 OrData\r | |
a2285a89 RN |
161 | )\r |
162 | {\r | |
163 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentOr8 (Address, OrData));\r | |
164 | }\r | |
165 | \r | |
166 | /**\r | |
167 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and\r | |
168 | saves the value in the S3 script to be replayed on S3 resume.\r | |
169 | \r | |
170 | Reads the 8-bit PCI configuration register specified by Address,\r | |
171 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
172 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
173 | The value written to the PCI configuration register is returned.\r | |
174 | This function must guarantee that all PCI read and write operations are serialized.\r | |
175 | If any reserved bits in Address are set, then ASSERT().\r | |
176 | \r | |
177 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
178 | @param AndData The value to AND with the PCI configuration register.\r | |
179 | \r | |
180 | @return The value written to the PCI configuration register.\r | |
181 | \r | |
182 | **/\r | |
183 | UINT8\r | |
184 | EFIAPI\r | |
185 | S3PciSegmentAnd8 (\r | |
2f88bd3a MK |
186 | IN UINT64 Address,\r |
187 | IN UINT8 AndData\r | |
a2285a89 RN |
188 | )\r |
189 | {\r | |
190 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAnd8 (Address, AndData));\r | |
191 | }\r | |
192 | \r | |
193 | /**\r | |
194 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
195 | followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to\r | |
196 | be replayed on S3 resume.\r | |
197 | \r | |
198 | Reads the 8-bit PCI configuration register specified by Address,\r | |
199 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
200 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
201 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
202 | The value written to the PCI configuration register is returned.\r | |
203 | This function must guarantee that all PCI read and write operations are serialized.\r | |
204 | \r | |
205 | If any reserved bits in Address are set, then ASSERT().\r | |
206 | \r | |
207 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
208 | @param AndData The value to AND with the PCI configuration register.\r | |
209 | @param OrData The value to OR with the PCI configuration register.\r | |
210 | \r | |
211 | @return The value written to the PCI configuration register.\r | |
212 | \r | |
213 | **/\r | |
214 | UINT8\r | |
215 | EFIAPI\r | |
216 | S3PciSegmentAndThenOr8 (\r | |
2f88bd3a MK |
217 | IN UINT64 Address,\r |
218 | IN UINT8 AndData,\r | |
219 | IN UINT8 OrData\r | |
a2285a89 RN |
220 | )\r |
221 | {\r | |
222 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAndThenOr8 (Address, AndData, OrData));\r | |
223 | }\r | |
224 | \r | |
225 | /**\r | |
226 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
227 | S3 script to be replayed on S3 resume.\r | |
228 | \r | |
229 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
230 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
231 | returned.\r | |
232 | \r | |
233 | If any reserved bits in Address are set, then ASSERT().\r | |
234 | If StartBit is greater than 7, then ASSERT().\r | |
235 | If EndBit is greater than 7, then ASSERT().\r | |
236 | If EndBit is less than StartBit, then ASSERT().\r | |
237 | \r | |
238 | @param Address PCI configuration register to read.\r | |
239 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
240 | Range 0..7.\r | |
241 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
242 | Range 0..7.\r | |
243 | \r | |
244 | @return The value of the bit field read from the PCI configuration register.\r | |
245 | \r | |
246 | **/\r | |
247 | UINT8\r | |
248 | EFIAPI\r | |
249 | S3PciSegmentBitFieldRead8 (\r | |
2f88bd3a MK |
250 | IN UINT64 Address,\r |
251 | IN UINTN StartBit,\r | |
252 | IN UINTN EndBit\r | |
a2285a89 RN |
253 | )\r |
254 | {\r | |
255 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldRead8 (Address, StartBit, EndBit));\r | |
256 | }\r | |
257 | \r | |
258 | /**\r | |
259 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
260 | the S3 script to be replayed on S3 resume.\r | |
261 | \r | |
262 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
263 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
264 | destination PCI configuration register are preserved. The new value of the\r | |
265 | 8-bit register is returned.\r | |
266 | \r | |
267 | If any reserved bits in Address are set, then ASSERT().\r | |
268 | If StartBit is greater than 7, then ASSERT().\r | |
269 | If EndBit is greater than 7, then ASSERT().\r | |
270 | If EndBit is less than StartBit, then ASSERT().\r | |
271 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
272 | \r | |
273 | @param Address PCI configuration register to write.\r | |
274 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
275 | Range 0..7.\r | |
276 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
277 | Range 0..7.\r | |
278 | @param Value New value of the bit field.\r | |
279 | \r | |
280 | @return The value written back to the PCI configuration register.\r | |
281 | \r | |
282 | **/\r | |
283 | UINT8\r | |
284 | EFIAPI\r | |
285 | S3PciSegmentBitFieldWrite8 (\r | |
2f88bd3a MK |
286 | IN UINT64 Address,\r |
287 | IN UINTN StartBit,\r | |
288 | IN UINTN EndBit,\r | |
289 | IN UINT8 Value\r | |
a2285a89 RN |
290 | )\r |
291 | {\r | |
292 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldWrite8 (Address, StartBit, EndBit, Value));\r | |
293 | }\r | |
294 | \r | |
295 | /**\r | |
296 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes\r | |
297 | the result back to the bit field in the 8-bit port, and saves the value in the\r | |
298 | S3 script to be replayed on S3 resume.\r | |
299 | \r | |
300 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
301 | bitwise OR between the read result and the value specified by\r | |
302 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
303 | specified by Address. The value written to the PCI configuration register is\r | |
304 | returned. This function must guarantee that all PCI read and write operations\r | |
305 | are serialized. Extra left bits in OrData are stripped.\r | |
306 | \r | |
307 | If any reserved bits in Address are set, then ASSERT().\r | |
308 | If StartBit is greater than 7, then ASSERT().\r | |
309 | If EndBit is greater than 7, then ASSERT().\r | |
310 | If EndBit is less than StartBit, then ASSERT().\r | |
311 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
312 | \r | |
313 | @param Address PCI configuration register to write.\r | |
314 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
315 | Range 0..7.\r | |
316 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
317 | Range 0..7.\r | |
318 | @param OrData The value to OR with the PCI configuration register.\r | |
319 | \r | |
320 | @return The value written back to the PCI configuration register.\r | |
321 | \r | |
322 | **/\r | |
323 | UINT8\r | |
324 | EFIAPI\r | |
325 | S3PciSegmentBitFieldOr8 (\r | |
2f88bd3a MK |
326 | IN UINT64 Address,\r |
327 | IN UINTN StartBit,\r | |
328 | IN UINTN EndBit,\r | |
329 | IN UINT8 OrData\r | |
a2285a89 RN |
330 | )\r |
331 | {\r | |
332 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldOr8 (Address, StartBit, EndBit, OrData));\r | |
333 | }\r | |
334 | \r | |
335 | /**\r | |
336 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
337 | AND, writes the result back to the bit field in the 8-bit register, and\r | |
338 | saves the value in the S3 script to be replayed on S3 resume.\r | |
339 | \r | |
340 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
341 | bitwise AND between the read result and the value specified by AndData, and\r | |
342 | writes the result to the 8-bit PCI configuration register specified by\r | |
343 | Address. The value written to the PCI configuration register is returned.\r | |
344 | This function must guarantee that all PCI read and write operations are\r | |
345 | serialized. Extra left bits in AndData are stripped.\r | |
346 | \r | |
347 | If any reserved bits in Address are set, then ASSERT().\r | |
348 | If StartBit is greater than 7, then ASSERT().\r | |
349 | If EndBit is greater than 7, then ASSERT().\r | |
350 | If EndBit is less than StartBit, then ASSERT().\r | |
351 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
352 | \r | |
353 | @param Address PCI configuration register to write.\r | |
354 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
355 | Range 0..7.\r | |
356 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
357 | Range 0..7.\r | |
358 | @param AndData The value to AND with the PCI configuration register.\r | |
359 | \r | |
360 | @return The value written back to the PCI configuration register.\r | |
361 | \r | |
362 | **/\r | |
363 | UINT8\r | |
364 | EFIAPI\r | |
365 | S3PciSegmentBitFieldAnd8 (\r | |
2f88bd3a MK |
366 | IN UINT64 Address,\r |
367 | IN UINTN StartBit,\r | |
368 | IN UINTN EndBit,\r | |
369 | IN UINT8 AndData\r | |
a2285a89 RN |
370 | )\r |
371 | {\r | |
372 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r | |
373 | }\r | |
374 | \r | |
375 | /**\r | |
376 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
377 | bitwise OR, writes the result back to the bit field in the 8-bit port,\r | |
378 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
379 | \r | |
380 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
381 | bitwise AND followed by a bitwise OR between the read result and\r | |
382 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
383 | configuration register specified by Address. The value written to the PCI\r | |
384 | configuration register is returned. This function must guarantee that all PCI\r | |
385 | read and write operations are serialized. Extra left bits in both AndData and\r | |
386 | OrData are stripped.\r | |
387 | \r | |
388 | If any reserved bits in Address are set, then ASSERT().\r | |
389 | If StartBit is greater than 7, then ASSERT().\r | |
390 | If EndBit is greater than 7, then ASSERT().\r | |
391 | If EndBit is less than StartBit, then ASSERT().\r | |
392 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
393 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
394 | \r | |
395 | @param Address PCI configuration register to write.\r | |
396 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
397 | Range 0..7.\r | |
398 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
399 | Range 0..7.\r | |
400 | @param AndData The value to AND with the PCI configuration register.\r | |
401 | @param OrData The value to OR with the result of the AND operation.\r | |
402 | \r | |
403 | @return The value written back to the PCI configuration register.\r | |
404 | \r | |
405 | **/\r | |
406 | UINT8\r | |
407 | EFIAPI\r | |
408 | S3PciSegmentBitFieldAndThenOr8 (\r | |
2f88bd3a MK |
409 | IN UINT64 Address,\r |
410 | IN UINTN StartBit,\r | |
411 | IN UINTN EndBit,\r | |
412 | IN UINT8 AndData,\r | |
413 | IN UINT8 OrData\r | |
a2285a89 RN |
414 | )\r |
415 | {\r | |
416 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r | |
417 | }\r | |
418 | \r | |
419 | /**\r | |
420 | Saves a 16-bit PCI configuration value to the boot script.\r | |
421 | \r | |
422 | This internal worker function saves a 16-bit PCI configuration value in\r | |
423 | the S3 script to be replayed on S3 resume.\r | |
424 | \r | |
425 | If the saving process fails, then ASSERT().\r | |
426 | \r | |
427 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
428 | Register.\r | |
429 | @param Value The value saved to boot script.\r | |
430 | \r | |
431 | @return Value.\r | |
432 | \r | |
433 | **/\r | |
434 | UINT16\r | |
435 | InternalSavePciSegmentWrite16ValueToBootScript (\r | |
2f88bd3a MK |
436 | IN UINT64 Address,\r |
437 | IN UINT16 Value\r | |
a2285a89 RN |
438 | )\r |
439 | {\r | |
440 | InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r | |
441 | \r | |
442 | return Value;\r | |
443 | }\r | |
444 | \r | |
445 | /**\r | |
446 | Reads a 16-bit PCI configuration register, and saves the value in the S3 script\r | |
447 | to be replayed on S3 resume.\r | |
448 | \r | |
449 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
450 | This function must guarantee that all PCI read and write operations are serialized.\r | |
451 | \r | |
452 | If any reserved bits in Address are set, then ASSERT().\r | |
453 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
454 | \r | |
455 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
456 | \r | |
457 | @return The 16-bit PCI configuration register specified by Address.\r | |
458 | \r | |
459 | **/\r | |
460 | UINT16\r | |
461 | EFIAPI\r | |
462 | S3PciSegmentRead16 (\r | |
2f88bd3a | 463 | IN UINT64 Address\r |
a2285a89 RN |
464 | )\r |
465 | {\r | |
466 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentRead16 (Address));\r | |
467 | }\r | |
468 | \r | |
469 | /**\r | |
470 | Writes a 16-bit PCI configuration register, and saves the value in the S3 script to\r | |
471 | be replayed on S3 resume.\r | |
472 | \r | |
473 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
474 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
475 | \r | |
476 | If any reserved bits in Address are set, then ASSERT().\r | |
477 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
478 | \r | |
479 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
480 | @param Value The value to write.\r | |
481 | \r | |
482 | @return The parameter of Value.\r | |
483 | \r | |
484 | **/\r | |
485 | UINT16\r | |
486 | EFIAPI\r | |
487 | S3PciSegmentWrite16 (\r | |
2f88bd3a MK |
488 | IN UINT64 Address,\r |
489 | IN UINT16 Value\r | |
a2285a89 RN |
490 | )\r |
491 | {\r | |
492 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentWrite16 (Address, Value));\r | |
493 | }\r | |
494 | \r | |
495 | /**\r | |
496 | Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit\r | |
497 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
498 | \r | |
499 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
500 | bitwise OR between the read result and the value specified by OrData, and\r | |
501 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
502 | The value written to the PCI configuration register is returned. This function\r | |
503 | must guarantee that all PCI read and write operations are serialized.\r | |
504 | \r | |
505 | If any reserved bits in Address are set, then ASSERT().\r | |
506 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
507 | \r | |
508 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
509 | Register.\r | |
510 | @param OrData The value to OR with the PCI configuration register.\r | |
511 | \r | |
512 | @return The value written back to the PCI configuration register.\r | |
513 | \r | |
514 | **/\r | |
515 | UINT16\r | |
516 | EFIAPI\r | |
517 | S3PciSegmentOr16 (\r | |
2f88bd3a MK |
518 | IN UINT64 Address,\r |
519 | IN UINT16 OrData\r | |
a2285a89 RN |
520 | )\r |
521 | {\r | |
522 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentOr16 (Address, OrData));\r | |
523 | }\r | |
524 | \r | |
525 | /**\r | |
526 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and\r | |
527 | saves the value in the S3 script to be replayed on S3 resume.\r | |
528 | \r | |
529 | Reads the 16-bit PCI configuration register specified by Address,\r | |
530 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
531 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
532 | The value written to the PCI configuration register is returned.\r | |
533 | This function must guarantee that all PCI read and write operations are serialized.\r | |
534 | \r | |
535 | If any reserved bits in Address are set, then ASSERT().\r | |
536 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
537 | \r | |
538 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
539 | @param AndData The value to AND with the PCI configuration register.\r | |
540 | \r | |
541 | @return The value written to the PCI configuration register.\r | |
542 | \r | |
543 | **/\r | |
544 | UINT16\r | |
545 | EFIAPI\r | |
546 | S3PciSegmentAnd16 (\r | |
2f88bd3a MK |
547 | IN UINT64 Address,\r |
548 | IN UINT16 AndData\r | |
a2285a89 RN |
549 | )\r |
550 | {\r | |
551 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAnd16 (Address, AndData));\r | |
552 | }\r | |
553 | \r | |
554 | /**\r | |
555 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
556 | followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to\r | |
557 | be replayed on S3 resume.\r | |
558 | \r | |
559 | Reads the 16-bit PCI configuration register specified by Address,\r | |
560 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
561 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
562 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
563 | The value written to the PCI configuration register is returned.\r | |
564 | This function must guarantee that all PCI read and write operations are serialized.\r | |
565 | \r | |
566 | If any reserved bits in Address are set, then ASSERT().\r | |
567 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
568 | \r | |
569 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
570 | @param AndData The value to AND with the PCI configuration register.\r | |
571 | @param OrData The value to OR with the PCI configuration register.\r | |
572 | \r | |
573 | @return The value written to the PCI configuration register.\r | |
574 | \r | |
575 | **/\r | |
576 | UINT16\r | |
577 | EFIAPI\r | |
578 | S3PciSegmentAndThenOr16 (\r | |
2f88bd3a MK |
579 | IN UINT64 Address,\r |
580 | IN UINT16 AndData,\r | |
581 | IN UINT16 OrData\r | |
a2285a89 RN |
582 | )\r |
583 | {\r | |
584 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAndThenOr16 (Address, AndData, OrData));\r | |
585 | }\r | |
586 | \r | |
587 | /**\r | |
588 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
589 | S3 script to be replayed on S3 resume.\r | |
590 | \r | |
591 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
592 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
593 | returned.\r | |
594 | \r | |
595 | If any reserved bits in Address are set, then ASSERT().\r | |
596 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
597 | If StartBit is greater than 15, then ASSERT().\r | |
598 | If EndBit is greater than 15, then ASSERT().\r | |
599 | If EndBit is less than StartBit, then ASSERT().\r | |
600 | \r | |
601 | @param Address PCI configuration register to read.\r | |
602 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
603 | Range 0..15.\r | |
604 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
605 | Range 0..15.\r | |
606 | \r | |
607 | @return The value of the bit field read from the PCI configuration register.\r | |
608 | \r | |
609 | **/\r | |
610 | UINT16\r | |
611 | EFIAPI\r | |
612 | S3PciSegmentBitFieldRead16 (\r | |
2f88bd3a MK |
613 | IN UINT64 Address,\r |
614 | IN UINTN StartBit,\r | |
615 | IN UINTN EndBit\r | |
a2285a89 RN |
616 | )\r |
617 | {\r | |
618 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldRead16 (Address, StartBit, EndBit));\r | |
619 | }\r | |
620 | \r | |
621 | /**\r | |
622 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
623 | the S3 script to be replayed on S3 resume.\r | |
624 | \r | |
625 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
626 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
627 | destination PCI configuration register are preserved. The new value of the\r | |
628 | 16-bit register is returned.\r | |
629 | \r | |
630 | If any reserved bits in Address are set, then ASSERT().\r | |
631 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
632 | If StartBit is greater than 15, then ASSERT().\r | |
633 | If EndBit is greater than 15, then ASSERT().\r | |
634 | If EndBit is less than StartBit, then ASSERT().\r | |
635 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
636 | \r | |
637 | @param Address PCI configuration register to write.\r | |
638 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
639 | Range 0..15.\r | |
640 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
641 | Range 0..15.\r | |
642 | @param Value New value of the bit field.\r | |
643 | \r | |
644 | @return The value written back to the PCI configuration register.\r | |
645 | \r | |
646 | **/\r | |
647 | UINT16\r | |
648 | EFIAPI\r | |
649 | S3PciSegmentBitFieldWrite16 (\r | |
2f88bd3a MK |
650 | IN UINT64 Address,\r |
651 | IN UINTN StartBit,\r | |
652 | IN UINTN EndBit,\r | |
653 | IN UINT16 Value\r | |
a2285a89 RN |
654 | )\r |
655 | {\r | |
656 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldWrite16 (Address, StartBit, EndBit, Value));\r | |
657 | }\r | |
658 | \r | |
659 | /**\r | |
660 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
661 | the result back to the bit field in the 16-bit port, and saves the value in the\r | |
662 | S3 script to be replayed on S3 resume.\r | |
663 | \r | |
664 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
665 | bitwise OR between the read result and the value specified by\r | |
666 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
667 | specified by Address. The value written to the PCI configuration register is\r | |
668 | returned. This function must guarantee that all PCI read and write operations\r | |
669 | are serialized. Extra left bits in OrData are stripped.\r | |
670 | \r | |
671 | If any reserved bits in Address are set, then ASSERT().\r | |
672 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
673 | If StartBit is greater than 15, then ASSERT().\r | |
674 | If EndBit is greater than 15, then ASSERT().\r | |
675 | If EndBit is less than StartBit, then ASSERT().\r | |
676 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
677 | \r | |
678 | @param Address PCI configuration register to write.\r | |
679 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
680 | Range 0..15.\r | |
681 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
682 | Range 0..15.\r | |
683 | @param OrData The value to OR with the PCI configuration register.\r | |
684 | \r | |
685 | @return The value written back to the PCI configuration register.\r | |
686 | \r | |
687 | **/\r | |
688 | UINT16\r | |
689 | EFIAPI\r | |
690 | S3PciSegmentBitFieldOr16 (\r | |
2f88bd3a MK |
691 | IN UINT64 Address,\r |
692 | IN UINTN StartBit,\r | |
693 | IN UINTN EndBit,\r | |
694 | IN UINT16 OrData\r | |
a2285a89 RN |
695 | )\r |
696 | {\r | |
697 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldOr16 (Address, StartBit, EndBit, OrData));\r | |
698 | }\r | |
699 | \r | |
700 | /**\r | |
701 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
702 | AND, writes the result back to the bit field in the 16-bit register, and\r | |
703 | saves the value in the S3 script to be replayed on S3 resume.\r | |
704 | \r | |
705 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
706 | bitwise AND between the read result and the value specified by AndData, and\r | |
707 | writes the result to the 16-bit PCI configuration register specified by\r | |
708 | Address. The value written to the PCI configuration register is returned.\r | |
709 | This function must guarantee that all PCI read and write operations are\r | |
710 | serialized. Extra left bits in AndData are stripped.\r | |
711 | \r | |
712 | If any reserved bits in Address are set, then ASSERT().\r | |
713 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
714 | If StartBit is greater than 15, then ASSERT().\r | |
715 | If EndBit is greater than 15, then ASSERT().\r | |
716 | If EndBit is less than StartBit, then ASSERT().\r | |
717 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
718 | \r | |
719 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
720 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
721 | Range 0..15.\r | |
722 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
723 | Range 0..15.\r | |
724 | @param AndData The value to AND with the PCI configuration register.\r | |
725 | \r | |
726 | @return The value written back to the PCI configuration register.\r | |
727 | \r | |
728 | **/\r | |
729 | UINT16\r | |
730 | EFIAPI\r | |
731 | S3PciSegmentBitFieldAnd16 (\r | |
2f88bd3a MK |
732 | IN UINT64 Address,\r |
733 | IN UINTN StartBit,\r | |
734 | IN UINTN EndBit,\r | |
735 | IN UINT16 AndData\r | |
a2285a89 RN |
736 | )\r |
737 | {\r | |
738 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r | |
739 | }\r | |
740 | \r | |
741 | /**\r | |
742 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
743 | bitwise OR, writes the result back to the bit field in the 16-bit port,\r | |
744 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
745 | \r | |
746 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
747 | bitwise AND followed by a bitwise OR between the read result and\r | |
748 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
749 | configuration register specified by Address. The value written to the PCI\r | |
750 | configuration register is returned. This function must guarantee that all PCI\r | |
751 | read and write operations are serialized. Extra left bits in both AndData and\r | |
752 | OrData are stripped.\r | |
753 | \r | |
754 | If any reserved bits in Address are set, then ASSERT().\r | |
755 | If StartBit is greater than 15, then ASSERT().\r | |
756 | If EndBit is greater than 15, then ASSERT().\r | |
757 | If EndBit is less than StartBit, then ASSERT().\r | |
758 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
759 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
760 | \r | |
761 | @param Address PCI configuration register to write.\r | |
762 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
763 | Range 0..15.\r | |
764 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
765 | Range 0..15.\r | |
766 | @param AndData The value to AND with the PCI configuration register.\r | |
767 | @param OrData The value to OR with the result of the AND operation.\r | |
768 | \r | |
769 | @return The value written back to the PCI configuration register.\r | |
770 | \r | |
771 | **/\r | |
772 | UINT16\r | |
773 | EFIAPI\r | |
774 | S3PciSegmentBitFieldAndThenOr16 (\r | |
2f88bd3a MK |
775 | IN UINT64 Address,\r |
776 | IN UINTN StartBit,\r | |
777 | IN UINTN EndBit,\r | |
778 | IN UINT16 AndData,\r | |
779 | IN UINT16 OrData\r | |
a2285a89 RN |
780 | )\r |
781 | {\r | |
782 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r | |
783 | }\r | |
784 | \r | |
a2285a89 RN |
785 | /**\r |
786 | Saves a 32-bit PCI configuration value to the boot script.\r | |
787 | \r | |
788 | This internal worker function saves a 32-bit PCI configuration value in the S3 script\r | |
789 | to be replayed on S3 resume.\r | |
790 | \r | |
791 | If the saving process fails, then ASSERT().\r | |
792 | \r | |
793 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
794 | Register.\r | |
795 | @param Value The value saved to boot script.\r | |
796 | \r | |
797 | @return Value.\r | |
798 | \r | |
799 | **/\r | |
800 | UINT32\r | |
801 | InternalSavePciSegmentWrite32ValueToBootScript (\r | |
2f88bd3a MK |
802 | IN UINT64 Address,\r |
803 | IN UINT32 Value\r | |
a2285a89 RN |
804 | )\r |
805 | {\r | |
806 | InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r | |
807 | \r | |
808 | return Value;\r | |
809 | }\r | |
810 | \r | |
811 | /**\r | |
812 | Reads a 32-bit PCI configuration register, and saves the value in the S3 script\r | |
813 | to be replayed on S3 resume.\r | |
814 | \r | |
815 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
816 | This function must guarantee that all PCI read and write operations are serialized.\r | |
817 | \r | |
818 | If any reserved bits in Address are set, then ASSERT().\r | |
819 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
820 | \r | |
821 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
822 | \r | |
823 | @return The 32-bit PCI configuration register specified by Address.\r | |
824 | \r | |
825 | **/\r | |
826 | UINT32\r | |
827 | EFIAPI\r | |
828 | S3PciSegmentRead32 (\r | |
2f88bd3a | 829 | IN UINT64 Address\r |
a2285a89 RN |
830 | )\r |
831 | {\r | |
832 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentRead32 (Address));\r | |
833 | }\r | |
834 | \r | |
835 | /**\r | |
836 | Writes a 32-bit PCI configuration register, and saves the value in the S3 script to\r | |
837 | be replayed on S3 resume.\r | |
838 | \r | |
839 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
840 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
841 | \r | |
842 | If any reserved bits in Address are set, then ASSERT().\r | |
843 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
844 | \r | |
845 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
846 | @param Value The value to write.\r | |
847 | \r | |
848 | @return The parameter of Value.\r | |
849 | \r | |
850 | **/\r | |
851 | UINT32\r | |
852 | EFIAPI\r | |
853 | S3PciSegmentWrite32 (\r | |
2f88bd3a MK |
854 | IN UINT64 Address,\r |
855 | IN UINT32 Value\r | |
a2285a89 RN |
856 | )\r |
857 | {\r | |
858 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentWrite32 (Address, Value));\r | |
859 | }\r | |
860 | \r | |
861 | /**\r | |
862 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit\r | |
863 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
864 | \r | |
865 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
866 | bitwise OR between the read result and the value specified by OrData, and\r | |
867 | writes the result to the 32-bit PCI configuration register specified by Address.\r | |
868 | The value written to the PCI configuration register is returned. This function\r | |
869 | must guarantee that all PCI read and write operations are serialized.\r | |
870 | \r | |
871 | If any reserved bits in Address are set, then ASSERT().\r | |
872 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
873 | \r | |
874 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and\r | |
875 | Register.\r | |
876 | @param OrData The value to OR with the PCI configuration register.\r | |
877 | \r | |
878 | @return The value written back to the PCI configuration register.\r | |
879 | \r | |
880 | **/\r | |
881 | UINT32\r | |
882 | EFIAPI\r | |
883 | S3PciSegmentOr32 (\r | |
2f88bd3a MK |
884 | IN UINT64 Address,\r |
885 | IN UINT32 OrData\r | |
a2285a89 RN |
886 | )\r |
887 | {\r | |
888 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentOr32 (Address, OrData));\r | |
889 | }\r | |
890 | \r | |
891 | /**\r | |
892 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and\r | |
893 | saves the value in the S3 script to be replayed on S3 resume.\r | |
894 | \r | |
895 | Reads the 32-bit PCI configuration register specified by Address,\r | |
896 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
897 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
898 | The value written to the PCI configuration register is returned.\r | |
899 | This function must guarantee that all PCI read and write operations are serialized.\r | |
900 | \r | |
901 | If any reserved bits in Address are set, then ASSERT().\r | |
902 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
903 | \r | |
904 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
905 | @param AndData The value to AND with the PCI configuration register.\r | |
906 | \r | |
907 | @return The value written to the PCI configuration register.\r | |
908 | \r | |
909 | **/\r | |
910 | UINT32\r | |
911 | EFIAPI\r | |
912 | S3PciSegmentAnd32 (\r | |
2f88bd3a MK |
913 | IN UINT64 Address,\r |
914 | IN UINT32 AndData\r | |
a2285a89 RN |
915 | )\r |
916 | {\r | |
917 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAnd32 (Address, AndData));\r | |
918 | }\r | |
919 | \r | |
920 | /**\r | |
921 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
922 | followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to\r | |
923 | be replayed on S3 resume.\r | |
924 | \r | |
925 | Reads the 32-bit PCI configuration register specified by Address,\r | |
926 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
927 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
928 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
929 | The value written to the PCI configuration register is returned.\r | |
930 | This function must guarantee that all PCI read and write operations are serialized.\r | |
931 | \r | |
932 | If any reserved bits in Address are set, then ASSERT().\r | |
933 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
934 | \r | |
935 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
936 | @param AndData The value to AND with the PCI configuration register.\r | |
937 | @param OrData The value to OR with the PCI configuration register.\r | |
938 | \r | |
939 | @return The value written to the PCI configuration register.\r | |
940 | \r | |
941 | **/\r | |
942 | UINT32\r | |
943 | EFIAPI\r | |
944 | S3PciSegmentAndThenOr32 (\r | |
2f88bd3a MK |
945 | IN UINT64 Address,\r |
946 | IN UINT32 AndData,\r | |
947 | IN UINT32 OrData\r | |
a2285a89 RN |
948 | )\r |
949 | {\r | |
950 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAndThenOr32 (Address, AndData, OrData));\r | |
951 | }\r | |
952 | \r | |
953 | /**\r | |
954 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
955 | S3 script to be replayed on S3 resume.\r | |
956 | \r | |
957 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
958 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
959 | returned.\r | |
960 | \r | |
961 | If any reserved bits in Address are set, then ASSERT().\r | |
962 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
963 | If StartBit is greater than 31, then ASSERT().\r | |
964 | If EndBit is greater than 31, then ASSERT().\r | |
965 | If EndBit is less than StartBit, then ASSERT().\r | |
966 | \r | |
967 | @param Address PCI configuration register to read.\r | |
968 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
969 | Range 0..31.\r | |
970 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
971 | Range 0..31.\r | |
972 | \r | |
973 | @return The value of the bit field read from the PCI configuration register.\r | |
974 | \r | |
975 | **/\r | |
976 | UINT32\r | |
977 | EFIAPI\r | |
978 | S3PciSegmentBitFieldRead32 (\r | |
2f88bd3a MK |
979 | IN UINT64 Address,\r |
980 | IN UINTN StartBit,\r | |
981 | IN UINTN EndBit\r | |
a2285a89 RN |
982 | )\r |
983 | {\r | |
984 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldRead32 (Address, StartBit, EndBit));\r | |
985 | }\r | |
986 | \r | |
987 | /**\r | |
988 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
989 | the S3 script to be replayed on S3 resume.\r | |
990 | \r | |
991 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
992 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
993 | destination PCI configuration register are preserved. The new value of the\r | |
994 | 32-bit register is returned.\r | |
995 | \r | |
996 | If any reserved bits in Address are set, then ASSERT().\r | |
997 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
998 | If StartBit is greater than 31, then ASSERT().\r | |
999 | If EndBit is greater than 31, then ASSERT().\r | |
1000 | If EndBit is less than StartBit, then ASSERT().\r | |
1001 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1002 | \r | |
1003 | @param Address PCI configuration register to write.\r | |
1004 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1005 | Range 0..31.\r | |
1006 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1007 | Range 0..31.\r | |
1008 | @param Value New value of the bit field.\r | |
1009 | \r | |
1010 | @return The value written back to the PCI configuration register.\r | |
1011 | \r | |
1012 | **/\r | |
1013 | UINT32\r | |
1014 | EFIAPI\r | |
1015 | S3PciSegmentBitFieldWrite32 (\r | |
2f88bd3a MK |
1016 | IN UINT64 Address,\r |
1017 | IN UINTN StartBit,\r | |
1018 | IN UINTN EndBit,\r | |
1019 | IN UINT32 Value\r | |
a2285a89 RN |
1020 | )\r |
1021 | {\r | |
1022 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldWrite32 (Address, StartBit, EndBit, Value));\r | |
1023 | }\r | |
1024 | \r | |
1025 | /**\r | |
1026 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes\r | |
1027 | the result back to the bit field in the 32-bit port, and saves the value in the\r | |
1028 | S3 script to be replayed on S3 resume.\r | |
1029 | \r | |
1030 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1031 | bitwise OR between the read result and the value specified by\r | |
1032 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1033 | specified by Address. The value written to the PCI configuration register is\r | |
1034 | returned. This function must guarantee that all PCI read and write operations\r | |
1035 | are serialized. Extra left bits in OrData are stripped.\r | |
1036 | \r | |
1037 | If any reserved bits in Address are set, then ASSERT().\r | |
1038 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1039 | If StartBit is greater than 31, then ASSERT().\r | |
1040 | If EndBit is greater than 31, then ASSERT().\r | |
1041 | If EndBit is less than StartBit, then ASSERT().\r | |
1042 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1043 | \r | |
1044 | @param Address PCI configuration register to write.\r | |
1045 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1046 | Range 0..31.\r | |
1047 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1048 | Range 0..31.\r | |
1049 | @param OrData The value to OR with the PCI configuration register.\r | |
1050 | \r | |
1051 | @return The value written back to the PCI configuration register.\r | |
1052 | \r | |
1053 | **/\r | |
1054 | UINT32\r | |
1055 | EFIAPI\r | |
1056 | S3PciSegmentBitFieldOr32 (\r | |
2f88bd3a MK |
1057 | IN UINT64 Address,\r |
1058 | IN UINTN StartBit,\r | |
1059 | IN UINTN EndBit,\r | |
1060 | IN UINT32 OrData\r | |
a2285a89 RN |
1061 | )\r |
1062 | {\r | |
1063 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldOr32 (Address, StartBit, EndBit, OrData));\r | |
1064 | }\r | |
1065 | \r | |
1066 | /**\r | |
1067 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1068 | AND, and writes the result back to the bit field in the 32-bit register, and\r | |
1069 | saves the value in the S3 script to be replayed on S3 resume.\r | |
1070 | \r | |
1071 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1072 | bitwise AND between the read result and the value specified by AndData, and\r | |
1073 | writes the result to the 32-bit PCI configuration register specified by\r | |
1074 | Address. The value written to the PCI configuration register is returned.\r | |
1075 | This function must guarantee that all PCI read and write operations are\r | |
1076 | serialized. Extra left bits in AndData are stripped.\r | |
1077 | \r | |
1078 | If any reserved bits in Address are set, then ASSERT().\r | |
1079 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1080 | If StartBit is greater than 31, then ASSERT().\r | |
1081 | If EndBit is greater than 31, then ASSERT().\r | |
1082 | If EndBit is less than StartBit, then ASSERT().\r | |
1083 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1084 | \r | |
1085 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
1086 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1087 | Range 0..31.\r | |
1088 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1089 | Range 0..31.\r | |
1090 | @param AndData The value to AND with the PCI configuration register.\r | |
1091 | \r | |
1092 | @return The value written back to the PCI configuration register.\r | |
1093 | \r | |
1094 | **/\r | |
1095 | UINT32\r | |
1096 | EFIAPI\r | |
1097 | S3PciSegmentBitFieldAnd32 (\r | |
2f88bd3a MK |
1098 | IN UINT64 Address,\r |
1099 | IN UINTN StartBit,\r | |
1100 | IN UINTN EndBit,\r | |
1101 | IN UINT32 AndData\r | |
a2285a89 RN |
1102 | )\r |
1103 | {\r | |
1104 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r | |
1105 | }\r | |
1106 | \r | |
1107 | /**\r | |
1108 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1109 | bitwise OR, writes the result back to the bit field in the 32-bit port,\r | |
1110 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
1111 | \r | |
1112 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1113 | bitwise AND followed by a bitwise OR between the read result and\r | |
1114 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1115 | configuration register specified by Address. The value written to the PCI\r | |
1116 | configuration register is returned. This function must guarantee that all PCI\r | |
1117 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1118 | OrData are stripped.\r | |
1119 | \r | |
1120 | If any reserved bits in Address are set, then ASSERT().\r | |
1121 | If StartBit is greater than 31, then ASSERT().\r | |
1122 | If EndBit is greater than 31, then ASSERT().\r | |
1123 | If EndBit is less than StartBit, then ASSERT().\r | |
1124 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1125 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1126 | \r | |
1127 | @param Address PCI configuration register to write.\r | |
1128 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1129 | Range 0..31.\r | |
1130 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1131 | Range 0..31.\r | |
1132 | @param AndData The value to AND with the PCI configuration register.\r | |
1133 | @param OrData The value to OR with the result of the AND operation.\r | |
1134 | \r | |
1135 | @return The value written back to the PCI configuration register.\r | |
1136 | \r | |
1137 | **/\r | |
1138 | UINT32\r | |
1139 | EFIAPI\r | |
1140 | S3PciSegmentBitFieldAndThenOr32 (\r | |
2f88bd3a MK |
1141 | IN UINT64 Address,\r |
1142 | IN UINTN StartBit,\r | |
1143 | IN UINTN EndBit,\r | |
1144 | IN UINT32 AndData,\r | |
1145 | IN UINT32 OrData\r | |
a2285a89 RN |
1146 | )\r |
1147 | {\r | |
1148 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r | |
1149 | }\r | |
1150 | \r | |
1151 | /**\r | |
1152 | Reads a range of PCI configuration registers into a caller supplied buffer,\r | |
1153 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
1154 | \r | |
1155 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1156 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1157 | configuration registers from a single PCI function to be read. Size is\r | |
1158 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1159 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1160 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1161 | end of the range.\r | |
1162 | \r | |
1163 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1164 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1165 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1166 | \r | |
1167 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1168 | Function and Register.\r | |
1169 | @param Size Size in bytes of the transfer.\r | |
1170 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1171 | \r | |
1172 | @return Size\r | |
1173 | \r | |
1174 | **/\r | |
1175 | UINTN\r | |
1176 | EFIAPI\r | |
1177 | S3PciSegmentReadBuffer (\r | |
2f88bd3a MK |
1178 | IN UINT64 StartAddress,\r |
1179 | IN UINTN Size,\r | |
1180 | OUT VOID *Buffer\r | |
a2285a89 RN |
1181 | )\r |
1182 | {\r | |
2f88bd3a | 1183 | RETURN_STATUS Status;\r |
a2285a89 RN |
1184 | \r |
1185 | Status = S3BootScriptSavePciCfg2Write (\r | |
1186 | S3BootScriptWidthUint8,\r | |
1187 | RShiftU64 (StartAddress, 32) & 0xffff,\r | |
1188 | PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),\r | |
1189 | PciSegmentReadBuffer (StartAddress, Size, Buffer),\r | |
1190 | Buffer\r | |
1191 | );\r | |
1192 | ASSERT_RETURN_ERROR (Status);\r | |
1193 | return Size;\r | |
1194 | }\r | |
1195 | \r | |
1196 | /**\r | |
1197 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1198 | configuration space, and saves the value in the S3 script to be replayed on S3\r | |
1199 | resume.\r | |
1200 | \r | |
1201 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1202 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1203 | configuration registers from a single PCI function to be written. Size is\r | |
1204 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1205 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1206 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1207 | and the end of the range.\r | |
1208 | \r | |
1209 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1210 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1211 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1212 | \r | |
1213 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1214 | Function and Register.\r | |
1215 | @param Size Size in bytes of the transfer.\r | |
1216 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1217 | \r | |
1218 | @return The parameter of Size.\r | |
1219 | \r | |
1220 | **/\r | |
1221 | UINTN\r | |
1222 | EFIAPI\r | |
1223 | S3PciSegmentWriteBuffer (\r | |
2f88bd3a MK |
1224 | IN UINT64 StartAddress,\r |
1225 | IN UINTN Size,\r | |
1226 | IN VOID *Buffer\r | |
a2285a89 RN |
1227 | )\r |
1228 | {\r | |
2f88bd3a | 1229 | RETURN_STATUS Status;\r |
a2285a89 RN |
1230 | \r |
1231 | Status = S3BootScriptSavePciCfg2Write (\r | |
1232 | S3BootScriptWidthUint8,\r | |
1233 | RShiftU64 (StartAddress, 32) & 0xffff,\r | |
1234 | PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),\r | |
1235 | PciSegmentWriteBuffer (StartAddress, Size, Buffer),\r | |
1236 | Buffer\r | |
1237 | );\r | |
1238 | ASSERT_RETURN_ERROR (Status);\r | |
1239 | return Size;\r | |
1240 | }\r |