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1 | /** @file\r |
2 | Timer Library functions built upon local APIC on IA32/x64.\r |
3 | \r |
4 | @bug Should use PCD to retrieve all the constants including index of\r |
5 | the IA32_APIC_BASE MSR, the offsets of InitialCount, CorrentCount\r |
6 | and DivideConfiguration.\r |
7 | \r |
8 | Copyright (c) 2006, Intel Corporation<BR>\r |
9 | All rights reserved. This program and the accompanying materials\r |
10 | are licensed and made available under the terms and conditions of the BSD License\r |
11 | which accompanies this distribution. The full text of the license may be found at\r |
12 | http://opensource.org/licenses/bsd-license.php\r |
13 | \r |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
16 | \r |
17 | Module Name: x86TimerLib.c\r |
18 | \r |
19 | **/\r |
20 | \r |
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21 | //\r |
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22 | // The following array is used in calculating the frequency of local APIC\r |
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23 | // timer. Refer to IA-32 developers' manual for more details.\r |
24 | //\r |
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25 | GLOBAL_REMOVE_IF_UNREFERENCED\r |
26 | CONST UINT8 mTimerLibLocalApicDivisor[] = {\r |
27 | 0x02, 0x04, 0x08, 0x10,\r |
28 | 0x02, 0x04, 0x08, 0x10,\r |
29 | 0x20, 0x40, 0x80, 0x01,\r |
30 | 0x20, 0x40, 0x80, 0x01\r |
31 | };\r |
32 | \r |
33 | /**\r |
34 | Internal function to retrieve the base address of local APIC.\r |
35 | \r |
36 | Internal function to retrieve the base address of local APIC.\r |
37 | \r |
38 | @return The base address of local APIC\r |
39 | \r |
40 | **/\r |
41 | STATIC\r |
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42 | UINTN\r |
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43 | InternalX86GetApicBase (\r |
44 | VOID\r |
45 | )\r |
46 | {\r |
47 | return (UINTN)AsmMsrBitFieldRead64 (27, 12, 35) << 12;\r |
48 | }\r |
49 | \r |
50 | /**\r |
51 | Internal function to return the frequency of the local APIC timer.\r |
52 | \r |
53 | Internal function to return the frequency of the local APIC timer.\r |
54 | \r |
55 | @param ApicBase The base address of memory mapped registers of local APIC.\r |
56 | \r |
57 | @return The frequency of the timer in Hz.\r |
58 | \r |
59 | **/\r |
60 | STATIC\r |
61 | UINT32\r |
62 | InternalX86GetTimerFrequency (\r |
63 | IN UINTN ApicBase\r |
64 | )\r |
65 | {\r |
66 | return\r |
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67 | PcdGet32(PcdFSBClock) /\r |
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68 | mTimerLibLocalApicDivisor[MmioBitFieldRead32 (ApicBase + 0x3e0, 0, 3)];\r |
69 | }\r |
70 | \r |
71 | /**\r |
72 | Internal function to read the current tick counter of local APIC.\r |
73 | \r |
74 | Internal function to read the current tick counter of local APIC.\r |
75 | \r |
76 | @param ApicBase The base address of memory mapped registers of local APIC.\r |
77 | \r |
78 | @return The tick counter read.\r |
79 | \r |
80 | **/\r |
81 | STATIC\r |
82 | INT32\r |
83 | InternalX86GetTimerTick (\r |
84 | IN UINTN ApicBase\r |
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85 | )\r |
86 | {\r |
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87 | return MmioRead32 (ApicBase + 0x390);\r |
88 | }\r |
89 | \r |
90 | /**\r |
91 | Stalls the CPU for at least the given number of ticks.\r |
92 | \r |
93 | Stalls the CPU for at least the given number of ticks. It's invoked by\r |
94 | MicroSecondDelay() and NanoSecondDelay().\r |
95 | \r |
96 | @param ApicBase The base address of memory mapped registers of local APIC.\r |
97 | @param Delay A period of time to delay in ticks.\r |
98 | \r |
99 | **/\r |
100 | STATIC\r |
101 | VOID\r |
102 | InternalX86Delay (\r |
103 | IN UINTN ApicBase,\r |
104 | IN UINT32 Delay\r |
105 | )\r |
106 | {\r |
107 | INT32 Ticks;\r |
108 | \r |
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109 | //\r |
110 | // The target timer count is calculated here\r |
111 | //\r |
112 | Ticks = InternalX86GetTimerTick (ApicBase) - Delay;\r |
113 | \r |
114 | //\r |
115 | // Wait until time out\r |
116 | // Delay > 2^31 could not be handled by this function\r |
117 | // Timer wrap-arounds are handled correctly by this function\r |
118 | //\r |
119 | while (InternalX86GetTimerTick (ApicBase) - Ticks >= 0);\r |
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120 | }\r |
121 | \r |
122 | /**\r |
123 | Stalls the CPU for at least the given number of microseconds.\r |
124 | \r |
125 | Stalls the CPU for the number of microseconds specified by MicroSeconds.\r |
126 | \r |
127 | @param MicroSeconds The minimum number of microseconds to delay.\r |
128 | \r |
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129 | @return MicroSeconds\r |
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130 | \r |
131 | **/\r |
132 | UINTN\r |
133 | EFIAPI\r |
134 | MicroSecondDelay (\r |
135 | IN UINTN MicroSeconds\r |
136 | )\r |
137 | {\r |
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138 | UINTN ApicBase;\r |
139 | \r |
140 | ApicBase = InternalX86GetApicBase ();\r |
141 | InternalX86Delay (\r |
142 | ApicBase,\r |
143 | (UINT32)DivU64x32 (\r |
144 | MultU64x64 (\r |
145 | InternalX86GetTimerFrequency (ApicBase),\r |
146 | MicroSeconds\r |
147 | ),\r |
148 | 1000000u\r |
149 | )\r |
150 | );\r |
151 | return MicroSeconds;\r |
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152 | }\r |
153 | \r |
154 | /**\r |
155 | Stalls the CPU for at least the given number of nanoseconds.\r |
156 | \r |
157 | Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r |
158 | \r |
159 | @param NanoSeconds The minimum number of nanoseconds to delay.\r |
160 | \r |
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161 | @return NanoSeconds\r |
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162 | \r |
163 | **/\r |
164 | UINTN\r |
165 | EFIAPI\r |
166 | NanoSecondDelay (\r |
167 | IN UINTN NanoSeconds\r |
168 | )\r |
169 | {\r |
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170 | UINTN ApicBase;\r |
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171 | \r |
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172 | ApicBase = InternalX86GetApicBase ();\r |
173 | InternalX86Delay (\r |
174 | ApicBase,\r |
175 | (UINT32)DivU64x32 (\r |
176 | MultU64x64 (\r |
177 | InternalX86GetTimerFrequency (ApicBase),\r |
178 | NanoSeconds\r |
179 | ),\r |
180 | 1000000000u\r |
181 | )\r |
182 | );\r |
183 | return NanoSeconds;\r |
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184 | }\r |
185 | \r |
186 | /**\r |
187 | Retrieves the current value of a 64-bit free running performance counter.\r |
188 | \r |
189 | Retrieves the current value of a 64-bit free running performance counter. The\r |
190 | counter can either count up by 1 or count down by 1. If the physical\r |
191 | performance counter counts by a larger increment, then the counter values\r |
192 | must be translated. The properties of the counter can be retrieved from\r |
193 | GetPerformanceCounterProperties().\r |
194 | \r |
195 | @return The current value of the free running performance counter.\r |
196 | \r |
197 | **/\r |
198 | UINT64\r |
199 | EFIAPI\r |
200 | GetPerformanceCounter (\r |
201 | VOID\r |
202 | )\r |
203 | {\r |
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204 | return (UINT64)(UINT32)InternalX86GetTimerTick (InternalX86GetApicBase ());\r |
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205 | }\r |
206 | \r |
207 | /**\r |
208 | Retrieves the 64-bit frequency in Hz and the range of performance counter\r |
209 | values.\r |
210 | \r |
211 | If StartValue is not NULL, then the value that the performance counter starts\r |
212 | with immediately after is it rolls over is returned in StartValue. If\r |
213 | EndValue is not NULL, then the value that the performance counter end with\r |
214 | immediately before it rolls over is returned in EndValue. The 64-bit\r |
215 | frequency of the performance counter in Hz is always returned. If StartValue\r |
216 | is less than EndValue, then the performance counter counts up. If StartValue\r |
217 | is greater than EndValue, then the performance counter counts down. For\r |
218 | example, a 64-bit free running counter that counts up would have a StartValue\r |
219 | of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r |
220 | that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r |
221 | \r |
222 | @param StartValue The value the performance counter starts with when it\r |
223 | rolls over.\r |
224 | @param EndValue The value that the performance counter ends with before\r |
225 | it rolls over.\r |
226 | \r |
227 | @return The frequency in Hz.\r |
228 | \r |
229 | **/\r |
230 | UINT64\r |
231 | EFIAPI\r |
232 | GetPerformanceCounterProperties (\r |
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233 | OUT UINT64 *StartValue, OPTIONAL\r |
234 | OUT UINT64 *EndValue OPTIONAL\r |
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235 | )\r |
236 | {\r |
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237 | UINTN ApicBase;\r |
238 | \r |
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239 | ApicBase = InternalX86GetApicBase ();\r |
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240 | \r |
241 | if (StartValue != NULL) {\r |
242 | *StartValue = MmioRead32 (ApicBase + 0x380);\r |
243 | }\r |
244 | \r |
245 | if (EndValue != NULL) {\r |
246 | *EndValue = 0;\r |
247 | }\r |
248 | \r |
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249 | return (UINT64) InternalX86GetTimerFrequency (ApicBase);;\r |
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250 | }\r |