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1a3eaf06 | 1 | /** @file\r |
2 | PCI Segment Library implementation using PCI CFG2 PPI.\r | |
3 | \r | |
19388d29 HT |
4 | Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials are\r | |
1a3eaf06 | 6 | licensed and made available under the terms and conditions of\r |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
2fc59a00 | 9 | http://opensource.org/licenses/bsd-license.php.\r |
1a3eaf06 | 10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiPei.h>\r | |
17 | \r | |
18 | #include <Ppi/PciCfg2.h>\r | |
19 | \r | |
20 | #include <Library/PciSegmentLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/PeiServicesTablePointerLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | #include <Library/PeiServicesLib.h>\r | |
25 | \r | |
26 | /**\r | |
27 | Assert the validity of a PCI Segment address.\r | |
59ceeabe | 28 | A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r |
1a3eaf06 | 29 | \r |
30 | @param A The address to validate.\r | |
31 | @param M Additional bits to assert to be zero.\r | |
32 | \r | |
33 | **/\r | |
34 | #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r | |
59ceeabe | 35 | ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r |
1a3eaf06 | 36 | \r |
37 | /**\r | |
38 | Translate PCI Lib address into format of PCI CFG2 PPI.\r | |
39 | \r | |
2fc59a00 | 40 | @param A The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 41 | Register.\r |
42 | \r | |
43 | **/\r | |
44 | #define PCI_TO_PCICFG2_ADDRESS(A) \\r | |
f5305d5a | 45 | ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
1a3eaf06 | 46 | \r |
47 | /**\r | |
48 | Gets PCI CFG2 PPI.\r | |
49 | \r | |
50 | This internal function retrieves PCI CFG2 PPI from PPI database.\r | |
51 | \r | |
2fc59a00 | 52 | @param Address The address that encodes the PCI Segment, Bus, Device, Function and Register.\r |
1a3eaf06 | 53 | \r |
54 | @return The pointer to PCI CFG2 PPI.\r | |
55 | \r | |
56 | **/\r | |
57 | EFI_PEI_PCI_CFG2_PPI *\r | |
58 | InternalGetPciCfg2Ppi (\r | |
59 | IN UINT64 Address\r | |
60 | )\r | |
61 | {\r | |
62 | EFI_STATUS Status;\r | |
63 | UINTN Instance;\r | |
64 | EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
65 | UINT64 SegmentNumber;\r | |
66 | \r | |
67 | Instance = 0;\r | |
68 | PciCfg2Ppi = NULL;\r | |
69 | SegmentNumber = BitFieldRead64 (Address, 32, 63);\r | |
70 | \r | |
71 | //\r | |
72 | // Loop through all instances of the PPI and match segment number\r | |
73 | //\r | |
74 | do {\r | |
75 | Status = PeiServicesLocatePpi(\r | |
76 | &gEfiPciCfg2PpiGuid,\r | |
77 | Instance,\r | |
78 | NULL,\r | |
79 | (VOID**) &PciCfg2Ppi\r | |
80 | );\r | |
81 | ASSERT_EFI_ERROR (Status);\r | |
82 | Instance++;\r | |
83 | } while (PciCfg2Ppi->Segment != SegmentNumber);\r | |
84 | \r | |
85 | return PciCfg2Ppi;\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Internal worker function to read a PCI configuration register.\r | |
90 | \r | |
91 | This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r | |
92 | It reads and returns the PCI configuration register specified by Address,\r | |
93 | the width of data is specified by Width.\r | |
94 | \r | |
2fc59a00 | 95 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 96 | Register.\r |
97 | @param Width Width of data to read\r | |
98 | \r | |
99 | @return The value read from the PCI configuration register.\r | |
100 | \r | |
101 | **/\r | |
102 | UINT32\r | |
103 | PeiPciSegmentLibPciCfg2ReadWorker (\r | |
104 | IN UINT64 Address,\r | |
105 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r | |
106 | )\r | |
107 | {\r | |
108 | UINT32 Data;\r | |
109 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 110 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 111 | \r |
112 | PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r | |
43fe5cdc | 113 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 114 | PciCfg2Ppi->Read (\r |
115 | GetPeiServicesTablePointer (),\r | |
116 | PciCfg2Ppi,\r | |
117 | Width,\r | |
43fe5cdc | 118 | PciCfg2Address,\r |
1a3eaf06 | 119 | &Data\r |
120 | );\r | |
121 | \r | |
122 | return Data;\r | |
123 | }\r | |
124 | \r | |
125 | /**\r | |
126 | Internal worker function to writes a PCI configuration register.\r | |
127 | \r | |
128 | This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r | |
129 | It writes the PCI configuration register specified by Address with the\r | |
130 | value specified by Data. The width of data is specifed by Width.\r | |
131 | Data is returned.\r | |
132 | \r | |
2fc59a00 | 133 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 134 | Register.\r |
135 | @param Width Width of data to write\r | |
136 | @param Data The value to write.\r | |
137 | \r | |
138 | @return The value written to the PCI configuration register.\r | |
139 | \r | |
140 | **/\r | |
141 | UINT32\r | |
142 | PeiPciSegmentLibPciCfg2WriteWorker (\r | |
143 | IN UINT64 Address,\r | |
144 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
145 | IN UINT32 Data\r | |
146 | )\r | |
147 | {\r | |
148 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 149 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 150 | \r |
151 | PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r | |
43fe5cdc | 152 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 153 | PciCfg2Ppi->Write (\r |
154 | GetPeiServicesTablePointer (),\r | |
155 | PciCfg2Ppi,\r | |
156 | Width,\r | |
43fe5cdc | 157 | PciCfg2Address,\r |
1a3eaf06 | 158 | &Data\r |
159 | );\r | |
160 | \r | |
161 | return Data;\r | |
162 | }\r | |
163 | \r | |
3e3ae634 | 164 | /**\r |
165 | Register a PCI device so PCI configuration registers may be accessed after \r | |
166 | SetVirtualAddressMap().\r | |
167 | \r | |
59ceeabe | 168 | If any reserved bits in Address are set, then ASSERT().\r |
3e3ae634 | 169 | \r |
2fc59a00 | 170 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 171 | Register.\r |
172 | \r | |
173 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
174 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
175 | after ExitBootServices().\r | |
176 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
177 | at runtime could not be mapped.\r | |
178 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
179 | complete the registration.\r | |
180 | \r | |
181 | **/\r | |
182 | RETURN_STATUS\r | |
183 | EFIAPI\r | |
184 | PciSegmentRegisterForRuntimeAccess (\r | |
185 | IN UINTN Address\r | |
186 | )\r | |
187 | {\r | |
59ceeabe | 188 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r |
3e3ae634 | 189 | return RETURN_UNSUPPORTED;\r |
190 | }\r | |
191 | \r | |
1a3eaf06 | 192 | /**\r |
193 | Reads an 8-bit PCI configuration register.\r | |
194 | \r | |
195 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
d5979dc0 | 196 | This function must guarantee that all PCI read and write operations are serialized.\r |
197 | \r | |
1a3eaf06 | 198 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 199 | \r |
2fc59a00 | 200 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
1a3eaf06 | 201 | \r |
d5979dc0 | 202 | @return The 8-bit PCI configuration register specified by Address.\r |
1a3eaf06 | 203 | \r |
204 | **/\r | |
205 | UINT8\r | |
206 | EFIAPI\r | |
207 | PciSegmentRead8 (\r | |
0c3437e0 | 208 | IN UINT64 Address\r |
1a3eaf06 | 209 | )\r |
210 | {\r | |
211 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
212 | \r | |
213 | return (UINT8) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r | |
214 | }\r | |
215 | \r | |
216 | /**\r | |
217 | Writes an 8-bit PCI configuration register.\r | |
218 | \r | |
d5979dc0 | 219 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r |
220 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
221 | \r | |
59ceeabe | 222 | If any reserved bits in Address are set, then ASSERT().\r |
1a3eaf06 | 223 | \r |
2fc59a00 | 224 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 225 | @param Value The value to write.\r |
1a3eaf06 | 226 | \r |
227 | @return The value written to the PCI configuration register.\r | |
228 | \r | |
229 | **/\r | |
230 | UINT8\r | |
231 | EFIAPI\r | |
232 | PciSegmentWrite8 (\r | |
0c3437e0 | 233 | IN UINT64 Address,\r |
234 | IN UINT8 Value\r | |
1a3eaf06 | 235 | )\r |
236 | {\r | |
237 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
238 | \r | |
d5979dc0 | 239 | return (UINT8) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r |
1a3eaf06 | 240 | }\r |
241 | \r | |
242 | /**\r | |
62991af2 | 243 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r |
1a3eaf06 | 244 | \r |
d5979dc0 | 245 | Reads the 8-bit PCI configuration register specified by Address,\r |
62991af2 | 246 | performs a bitwise OR between the read result and the value specified by OrData,\r |
d5979dc0 | 247 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
248 | The value written to the PCI configuration register is returned.\r | |
249 | This function must guarantee that all PCI read and write operations are serialized.\r | |
250 | \r | |
1a3eaf06 | 251 | If any reserved bits in Address are set, then ASSERT().\r |
252 | \r | |
2fc59a00 | 253 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 254 | @param OrData The value to OR with the PCI configuration register.\r |
1a3eaf06 | 255 | \r |
d5979dc0 | 256 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 257 | \r |
258 | **/\r | |
259 | UINT8\r | |
260 | EFIAPI\r | |
261 | PciSegmentOr8 (\r | |
0c3437e0 | 262 | IN UINT64 Address,\r |
263 | IN UINT8 OrData\r | |
1a3eaf06 | 264 | )\r |
265 | {\r | |
266 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r | |
267 | }\r | |
268 | \r | |
269 | /**\r | |
122e2191 | 270 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
1a3eaf06 | 271 | \r |
122e2191 | 272 | Reads the 8-bit PCI configuration register specified by Address,\r |
273 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
274 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
275 | The value written to the PCI configuration register is returned.\r | |
276 | This function must guarantee that all PCI read and write operations are serialized.\r | |
1a3eaf06 | 277 | If any reserved bits in Address are set, then ASSERT().\r |
278 | \r | |
2fc59a00 | 279 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 280 | @param AndData The value to AND with the PCI configuration register.\r |
1a3eaf06 | 281 | \r |
122e2191 | 282 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 283 | \r |
284 | **/\r | |
285 | UINT8\r | |
286 | EFIAPI\r | |
287 | PciSegmentAnd8 (\r | |
0c3437e0 | 288 | IN UINT64 Address,\r |
289 | IN UINT8 AndData\r | |
1a3eaf06 | 290 | )\r |
291 | {\r | |
292 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r | |
293 | }\r | |
294 | \r | |
295 | /**\r | |
122e2191 | 296 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
62991af2 | 297 | followed a bitwise OR with another 8-bit value.\r |
122e2191 | 298 | \r |
299 | Reads the 8-bit PCI configuration register specified by Address,\r | |
300 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 301 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
122e2191 | 302 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
303 | The value written to the PCI configuration register is returned.\r | |
304 | This function must guarantee that all PCI read and write operations are serialized.\r | |
305 | \r | |
1a3eaf06 | 306 | If any reserved bits in Address are set, then ASSERT().\r |
307 | \r | |
2fc59a00 | 308 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 309 | @param AndData The value to AND with the PCI configuration register.\r |
310 | @param OrData The value to OR with the PCI configuration register.\r | |
1a3eaf06 | 311 | \r |
122e2191 | 312 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 313 | \r |
314 | **/\r | |
315 | UINT8\r | |
316 | EFIAPI\r | |
317 | PciSegmentAndThenOr8 (\r | |
0c3437e0 | 318 | IN UINT64 Address,\r |
319 | IN UINT8 AndData,\r | |
320 | IN UINT8 OrData\r | |
1a3eaf06 | 321 | )\r |
322 | {\r | |
323 | return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r | |
324 | }\r | |
325 | \r | |
326 | /**\r | |
327 | Reads a bit field of a PCI configuration register.\r | |
328 | \r | |
329 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
330 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
331 | returned.\r | |
332 | \r | |
333 | If any reserved bits in Address are set, then ASSERT().\r | |
334 | If StartBit is greater than 7, then ASSERT().\r | |
335 | If EndBit is greater than 7, then ASSERT().\r | |
336 | If EndBit is less than StartBit, then ASSERT().\r | |
337 | \r | |
2fc59a00 | 338 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 339 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
340 | Range 0..7.\r | |
341 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
342 | Range 0..7.\r | |
343 | \r | |
344 | @return The value of the bit field read from the PCI configuration register.\r | |
345 | \r | |
346 | **/\r | |
347 | UINT8\r | |
348 | EFIAPI\r | |
349 | PciSegmentBitFieldRead8 (\r | |
0c3437e0 | 350 | IN UINT64 Address,\r |
351 | IN UINTN StartBit,\r | |
352 | IN UINTN EndBit\r | |
1a3eaf06 | 353 | )\r |
354 | {\r | |
355 | return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r | |
356 | }\r | |
357 | \r | |
358 | /**\r | |
359 | Writes a bit field to a PCI configuration register.\r | |
360 | \r | |
361 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
362 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
363 | destination PCI configuration register are preserved. The new value of the\r | |
364 | 8-bit register is returned.\r | |
365 | \r | |
366 | If any reserved bits in Address are set, then ASSERT().\r | |
367 | If StartBit is greater than 7, then ASSERT().\r | |
368 | If EndBit is greater than 7, then ASSERT().\r | |
369 | If EndBit is less than StartBit, then ASSERT().\r | |
370 | \r | |
2fc59a00 | 371 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 372 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
373 | Range 0..7.\r | |
374 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
375 | Range 0..7.\r | |
2fc59a00 | 376 | @param Value The new value of the bit field.\r |
1a3eaf06 | 377 | \r |
378 | @return The value written back to the PCI configuration register.\r | |
379 | \r | |
380 | **/\r | |
381 | UINT8\r | |
382 | EFIAPI\r | |
383 | PciSegmentBitFieldWrite8 (\r | |
0c3437e0 | 384 | IN UINT64 Address,\r |
385 | IN UINTN StartBit,\r | |
386 | IN UINTN EndBit,\r | |
387 | IN UINT8 Value\r | |
1a3eaf06 | 388 | )\r |
389 | {\r | |
390 | return PciSegmentWrite8 (\r | |
391 | Address,\r | |
392 | BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r | |
393 | );\r | |
394 | }\r | |
395 | \r | |
396 | /**\r | |
397 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
398 | writes the result back to the bit field in the 8-bit port.\r | |
399 | \r | |
400 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 401 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 402 | OrData, and writes the result to the 8-bit PCI configuration register\r |
403 | specified by Address. The value written to the PCI configuration register is\r | |
404 | returned. This function must guarantee that all PCI read and write operations\r | |
405 | are serialized. Extra left bits in OrData are stripped.\r | |
406 | \r | |
407 | If any reserved bits in Address are set, then ASSERT().\r | |
408 | If StartBit is greater than 7, then ASSERT().\r | |
409 | If EndBit is greater than 7, then ASSERT().\r | |
410 | If EndBit is less than StartBit, then ASSERT().\r | |
411 | \r | |
2fc59a00 | 412 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 413 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
414 | Range 0..7.\r | |
415 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
416 | Range 0..7.\r | |
417 | @param OrData The value to OR with the PCI configuration register.\r | |
418 | \r | |
419 | @return The value written back to the PCI configuration register.\r | |
420 | \r | |
421 | **/\r | |
422 | UINT8\r | |
423 | EFIAPI\r | |
424 | PciSegmentBitFieldOr8 (\r | |
0c3437e0 | 425 | IN UINT64 Address,\r |
426 | IN UINTN StartBit,\r | |
427 | IN UINTN EndBit,\r | |
428 | IN UINT8 OrData\r | |
1a3eaf06 | 429 | )\r |
430 | {\r | |
431 | return PciSegmentWrite8 (\r | |
432 | Address,\r | |
433 | BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r | |
434 | );\r | |
435 | }\r | |
436 | \r | |
437 | /**\r | |
438 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
439 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
440 | \r | |
441 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
442 | bitwise AND between the read result and the value specified by AndData, and\r | |
443 | writes the result to the 8-bit PCI configuration register specified by\r | |
444 | Address. The value written to the PCI configuration register is returned.\r | |
445 | This function must guarantee that all PCI read and write operations are\r | |
446 | serialized. Extra left bits in AndData are stripped.\r | |
447 | \r | |
448 | If any reserved bits in Address are set, then ASSERT().\r | |
449 | If StartBit is greater than 7, then ASSERT().\r | |
450 | If EndBit is greater than 7, then ASSERT().\r | |
451 | If EndBit is less than StartBit, then ASSERT().\r | |
452 | \r | |
2fc59a00 | 453 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 454 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
455 | Range 0..7.\r | |
456 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
457 | Range 0..7.\r | |
458 | @param AndData The value to AND with the PCI configuration register.\r | |
459 | \r | |
460 | @return The value written back to the PCI configuration register.\r | |
461 | \r | |
462 | **/\r | |
463 | UINT8\r | |
464 | EFIAPI\r | |
465 | PciSegmentBitFieldAnd8 (\r | |
0c3437e0 | 466 | IN UINT64 Address,\r |
467 | IN UINTN StartBit,\r | |
468 | IN UINTN EndBit,\r | |
469 | IN UINT8 AndData\r | |
1a3eaf06 | 470 | )\r |
471 | {\r | |
472 | return PciSegmentWrite8 (\r | |
473 | Address,\r | |
474 | BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r | |
475 | );\r | |
476 | }\r | |
477 | \r | |
478 | /**\r | |
479 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 480 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 481 | 8-bit port.\r |
482 | \r | |
483 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 484 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 485 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
486 | configuration register specified by Address. The value written to the PCI\r | |
487 | configuration register is returned. This function must guarantee that all PCI\r | |
488 | read and write operations are serialized. Extra left bits in both AndData and\r | |
489 | OrData are stripped.\r | |
490 | \r | |
491 | If any reserved bits in Address are set, then ASSERT().\r | |
492 | If StartBit is greater than 7, then ASSERT().\r | |
493 | If EndBit is greater than 7, then ASSERT().\r | |
494 | If EndBit is less than StartBit, then ASSERT().\r | |
495 | \r | |
2fc59a00 | 496 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 497 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
498 | Range 0..7.\r | |
499 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
500 | Range 0..7.\r | |
501 | @param AndData The value to AND with the PCI configuration register.\r | |
502 | @param OrData The value to OR with the result of the AND operation.\r | |
503 | \r | |
504 | @return The value written back to the PCI configuration register.\r | |
505 | \r | |
506 | **/\r | |
507 | UINT8\r | |
508 | EFIAPI\r | |
509 | PciSegmentBitFieldAndThenOr8 (\r | |
0c3437e0 | 510 | IN UINT64 Address,\r |
511 | IN UINTN StartBit,\r | |
512 | IN UINTN EndBit,\r | |
513 | IN UINT8 AndData,\r | |
514 | IN UINT8 OrData\r | |
1a3eaf06 | 515 | )\r |
516 | {\r | |
517 | return PciSegmentWrite8 (\r | |
518 | Address,\r | |
519 | BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
520 | );\r | |
521 | }\r | |
522 | \r | |
523 | /**\r | |
524 | Reads a 16-bit PCI configuration register.\r | |
525 | \r | |
526 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
d5979dc0 | 527 | This function must guarantee that all PCI read and write operations are serialized.\r |
528 | \r | |
1a3eaf06 | 529 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 530 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
531 | \r | |
2fc59a00 | 532 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
1a3eaf06 | 533 | \r |
d5979dc0 | 534 | @return The 16-bit PCI configuration register specified by Address.\r |
1a3eaf06 | 535 | \r |
536 | **/\r | |
537 | UINT16\r | |
538 | EFIAPI\r | |
539 | PciSegmentRead16 (\r | |
0c3437e0 | 540 | IN UINT64 Address\r |
1a3eaf06 | 541 | )\r |
542 | {\r | |
543 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
544 | \r | |
545 | return (UINT16) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r | |
546 | }\r | |
547 | \r | |
548 | /**\r | |
549 | Writes a 16-bit PCI configuration register.\r | |
550 | \r | |
d5979dc0 | 551 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r |
552 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
553 | \r | |
1a3eaf06 | 554 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 555 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 556 | \r |
2fc59a00 | 557 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 558 | @param Value The value to write.\r |
1a3eaf06 | 559 | \r |
d5979dc0 | 560 | @return The parameter of Value.\r |
1a3eaf06 | 561 | \r |
562 | **/\r | |
563 | UINT16\r | |
564 | EFIAPI\r | |
565 | PciSegmentWrite16 (\r | |
0c3437e0 | 566 | IN UINT64 Address,\r |
567 | IN UINT16 Value\r | |
1a3eaf06 | 568 | )\r |
569 | {\r | |
570 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
571 | \r | |
d5979dc0 | 572 | return (UINT16) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r |
1a3eaf06 | 573 | }\r |
574 | \r | |
575 | /**\r | |
62991af2 | 576 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
1a3eaf06 | 577 | a 16-bit value.\r |
578 | \r | |
579 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 580 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 581 | OrData, and writes the result to the 16-bit PCI configuration register\r |
582 | specified by Address. The value written to the PCI configuration register is\r | |
583 | returned. This function must guarantee that all PCI read and write operations\r | |
584 | are serialized.\r | |
585 | \r | |
586 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 587 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 588 | \r |
2fc59a00 | 589 | @param Address The address that encodes the PCI Segment, Bus, Device, Function and\r |
1a3eaf06 | 590 | Register.\r |
591 | @param OrData The value to OR with the PCI configuration register.\r | |
592 | \r | |
593 | @return The value written back to the PCI configuration register.\r | |
594 | \r | |
595 | **/\r | |
596 | UINT16\r | |
597 | EFIAPI\r | |
598 | PciSegmentOr16 (\r | |
0c3437e0 | 599 | IN UINT64 Address,\r |
600 | IN UINT16 OrData\r | |
1a3eaf06 | 601 | )\r |
602 | {\r | |
603 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r | |
604 | }\r | |
605 | \r | |
606 | /**\r | |
122e2191 | 607 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
1a3eaf06 | 608 | \r |
122e2191 | 609 | Reads the 16-bit PCI configuration register specified by Address,\r |
610 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
611 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
612 | The value written to the PCI configuration register is returned.\r | |
613 | This function must guarantee that all PCI read and write operations are serialized.\r | |
614 | \r | |
1a3eaf06 | 615 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 616 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
617 | \r | |
2fc59a00 | 618 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 619 | @param AndData The value to AND with the PCI configuration register.\r |
1a3eaf06 | 620 | \r |
122e2191 | 621 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 622 | \r |
623 | **/\r | |
624 | UINT16\r | |
625 | EFIAPI\r | |
626 | PciSegmentAnd16 (\r | |
0c3437e0 | 627 | IN UINT64 Address,\r |
628 | IN UINT16 AndData\r | |
1a3eaf06 | 629 | )\r |
630 | {\r | |
631 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r | |
632 | }\r | |
633 | \r | |
634 | /**\r | |
d5979dc0 | 635 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r |
62991af2 | 636 | followed a bitwise OR with another 16-bit value.\r |
d5979dc0 | 637 | \r |
638 | Reads the 16-bit PCI configuration register specified by Address,\r | |
639 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 640 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
d5979dc0 | 641 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
642 | The value written to the PCI configuration register is returned.\r | |
643 | This function must guarantee that all PCI read and write operations are serialized.\r | |
644 | \r | |
1a3eaf06 | 645 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 646 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 647 | \r |
2fc59a00 | 648 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 649 | @param AndData The value to AND with the PCI configuration register.\r |
650 | @param OrData The value to OR with the PCI configuration register.\r | |
1a3eaf06 | 651 | \r |
d5979dc0 | 652 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 653 | \r |
654 | **/\r | |
655 | UINT16\r | |
656 | EFIAPI\r | |
657 | PciSegmentAndThenOr16 (\r | |
0c3437e0 | 658 | IN UINT64 Address,\r |
659 | IN UINT16 AndData,\r | |
660 | IN UINT16 OrData\r | |
1a3eaf06 | 661 | )\r |
662 | {\r | |
663 | return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r | |
664 | }\r | |
665 | \r | |
666 | /**\r | |
667 | Reads a bit field of a PCI configuration register.\r | |
668 | \r | |
669 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
670 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
671 | returned.\r | |
672 | \r | |
673 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 674 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 675 | If StartBit is greater than 15, then ASSERT().\r |
676 | If EndBit is greater than 15, then ASSERT().\r | |
677 | If EndBit is less than StartBit, then ASSERT().\r | |
678 | \r | |
2fc59a00 | 679 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 680 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
681 | Range 0..15.\r | |
682 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
683 | Range 0..15.\r | |
684 | \r | |
685 | @return The value of the bit field read from the PCI configuration register.\r | |
686 | \r | |
687 | **/\r | |
688 | UINT16\r | |
689 | EFIAPI\r | |
690 | PciSegmentBitFieldRead16 (\r | |
0c3437e0 | 691 | IN UINT64 Address,\r |
692 | IN UINTN StartBit,\r | |
693 | IN UINTN EndBit\r | |
1a3eaf06 | 694 | )\r |
695 | {\r | |
696 | return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r | |
697 | }\r | |
698 | \r | |
699 | /**\r | |
700 | Writes a bit field to a PCI configuration register.\r | |
701 | \r | |
702 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
703 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
704 | destination PCI configuration register are preserved. The new value of the\r | |
705 | 16-bit register is returned.\r | |
706 | \r | |
707 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 708 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 709 | If StartBit is greater than 15, then ASSERT().\r |
710 | If EndBit is greater than 15, then ASSERT().\r | |
711 | If EndBit is less than StartBit, then ASSERT().\r | |
712 | \r | |
2fc59a00 | 713 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 714 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
715 | Range 0..15.\r | |
716 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
717 | Range 0..15.\r | |
2fc59a00 | 718 | @param Value The new value of the bit field.\r |
1a3eaf06 | 719 | \r |
720 | @return The value written back to the PCI configuration register.\r | |
721 | \r | |
722 | **/\r | |
723 | UINT16\r | |
724 | EFIAPI\r | |
725 | PciSegmentBitFieldWrite16 (\r | |
0c3437e0 | 726 | IN UINT64 Address,\r |
727 | IN UINTN StartBit,\r | |
728 | IN UINTN EndBit,\r | |
729 | IN UINT16 Value\r | |
1a3eaf06 | 730 | )\r |
731 | {\r | |
732 | return PciSegmentWrite16 (\r | |
733 | Address,\r | |
734 | BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r | |
735 | );\r | |
736 | }\r | |
737 | \r | |
738 | /**\r | |
d5979dc0 | 739 | Reads the 16-bit PCI configuration register specified by Address,\r |
62991af2 | 740 | performs a bitwise OR between the read result and the value specified by OrData,\r |
d5979dc0 | 741 | and writes the result to the 16-bit PCI configuration register specified by Address. \r |
1a3eaf06 | 742 | \r |
743 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 744 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 745 | If StartBit is greater than 15, then ASSERT().\r |
746 | If EndBit is greater than 15, then ASSERT().\r | |
747 | If EndBit is less than StartBit, then ASSERT().\r | |
748 | \r | |
2fc59a00 | 749 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 750 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
751 | Range 0..15.\r | |
752 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
753 | Range 0..15.\r | |
754 | @param OrData The value to OR with the PCI configuration register.\r | |
755 | \r | |
756 | @return The value written back to the PCI configuration register.\r | |
757 | \r | |
758 | **/\r | |
759 | UINT16\r | |
760 | EFIAPI\r | |
761 | PciSegmentBitFieldOr16 (\r | |
0c3437e0 | 762 | IN UINT64 Address,\r |
763 | IN UINTN StartBit,\r | |
764 | IN UINTN EndBit,\r | |
765 | IN UINT16 OrData\r | |
1a3eaf06 | 766 | )\r |
767 | {\r | |
768 | return PciSegmentWrite16 (\r | |
769 | Address,\r | |
770 | BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r | |
771 | );\r | |
772 | }\r | |
773 | \r | |
774 | /**\r | |
0c3437e0 | 775 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r |
776 | and writes the result back to the bit field in the 16-bit port.\r | |
1a3eaf06 | 777 | \r |
0c3437e0 | 778 | Reads the 16-bit PCI configuration register specified by Address,\r |
779 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
780 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
781 | The value written to the PCI configuration register is returned.\r | |
782 | This function must guarantee that all PCI read and write operations are serialized.\r | |
783 | Extra left bits in OrData are stripped.\r | |
784 | \r | |
1a3eaf06 | 785 | If any reserved bits in Address are set, then ASSERT().\r |
0c3437e0 | 786 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
787 | If StartBit is greater than 7, then ASSERT().\r | |
788 | If EndBit is greater than 7, then ASSERT().\r | |
1a3eaf06 | 789 | If EndBit is less than StartBit, then ASSERT().\r |
790 | \r | |
2fc59a00 | 791 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
1a3eaf06 | 792 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
0c3437e0 | 793 | The ordinal of the least significant bit in a byte is bit 0.\r |
1a3eaf06 | 794 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
0c3437e0 | 795 | The ordinal of the most significant bit in a byte is bit 7.\r |
796 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
1a3eaf06 | 797 | \r |
0c3437e0 | 798 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 799 | \r |
800 | **/\r | |
801 | UINT16\r | |
802 | EFIAPI\r | |
803 | PciSegmentBitFieldAnd16 (\r | |
0c3437e0 | 804 | IN UINT64 Address,\r |
805 | IN UINTN StartBit,\r | |
806 | IN UINTN EndBit,\r | |
807 | IN UINT16 AndData\r | |
1a3eaf06 | 808 | )\r |
809 | {\r | |
810 | return PciSegmentWrite16 (\r | |
811 | Address,\r | |
812 | BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r | |
813 | );\r | |
814 | }\r | |
815 | \r | |
816 | /**\r | |
817 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 818 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 819 | 16-bit port.\r |
820 | \r | |
821 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 822 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 823 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
824 | configuration register specified by Address. The value written to the PCI\r | |
825 | configuration register is returned. This function must guarantee that all PCI\r | |
826 | read and write operations are serialized. Extra left bits in both AndData and\r | |
827 | OrData are stripped.\r | |
828 | \r | |
829 | If any reserved bits in Address are set, then ASSERT().\r | |
830 | If StartBit is greater than 15, then ASSERT().\r | |
831 | If EndBit is greater than 15, then ASSERT().\r | |
832 | If EndBit is less than StartBit, then ASSERT().\r | |
833 | \r | |
2fc59a00 | 834 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 835 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
836 | Range 0..15.\r | |
837 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
838 | Range 0..15.\r | |
839 | @param AndData The value to AND with the PCI configuration register.\r | |
840 | @param OrData The value to OR with the result of the AND operation.\r | |
841 | \r | |
842 | @return The value written back to the PCI configuration register.\r | |
843 | \r | |
844 | **/\r | |
845 | UINT16\r | |
846 | EFIAPI\r | |
847 | PciSegmentBitFieldAndThenOr16 (\r | |
0c3437e0 | 848 | IN UINT64 Address,\r |
849 | IN UINTN StartBit,\r | |
850 | IN UINTN EndBit,\r | |
851 | IN UINT16 AndData,\r | |
852 | IN UINT16 OrData\r | |
1a3eaf06 | 853 | )\r |
854 | {\r | |
855 | return PciSegmentWrite16 (\r | |
856 | Address,\r | |
857 | BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
858 | );\r | |
859 | }\r | |
860 | \r | |
861 | /**\r | |
862 | Reads a 32-bit PCI configuration register.\r | |
863 | \r | |
864 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
d5979dc0 | 865 | This function must guarantee that all PCI read and write operations are serialized.\r |
866 | \r | |
1a3eaf06 | 867 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 868 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 869 | \r |
2fc59a00 | 870 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
1a3eaf06 | 871 | \r |
d5979dc0 | 872 | @return The 32-bit PCI configuration register specified by Address.\r |
1a3eaf06 | 873 | \r |
874 | **/\r | |
875 | UINT32\r | |
876 | EFIAPI\r | |
877 | PciSegmentRead32 (\r | |
0c3437e0 | 878 | IN UINT64 Address\r |
1a3eaf06 | 879 | )\r |
880 | {\r | |
881 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
882 | \r | |
883 | return PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r | |
884 | }\r | |
885 | \r | |
886 | /**\r | |
887 | Writes a 32-bit PCI configuration register.\r | |
888 | \r | |
d5979dc0 | 889 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r |
890 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
891 | \r | |
1a3eaf06 | 892 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 893 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 894 | \r |
2fc59a00 | 895 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 896 | @param Value The value to write.\r |
1a3eaf06 | 897 | \r |
d5979dc0 | 898 | @return The parameter of Value.\r |
1a3eaf06 | 899 | \r |
900 | **/\r | |
901 | UINT32\r | |
902 | EFIAPI\r | |
903 | PciSegmentWrite32 (\r | |
0c3437e0 | 904 | IN UINT64 Address,\r |
905 | IN UINT32 Value\r | |
1a3eaf06 | 906 | )\r |
907 | {\r | |
908 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
909 | \r | |
d5979dc0 | 910 | return PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);\r |
1a3eaf06 | 911 | }\r |
912 | \r | |
913 | /**\r | |
62991af2 | 914 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r |
1a3eaf06 | 915 | \r |
d5979dc0 | 916 | Reads the 32-bit PCI configuration register specified by Address,\r |
62991af2 | 917 | performs a bitwise OR between the read result and the value specified by OrData,\r |
d5979dc0 | 918 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
919 | The value written to the PCI configuration register is returned.\r | |
920 | This function must guarantee that all PCI read and write operations are serialized.\r | |
921 | \r | |
1a3eaf06 | 922 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 923 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 924 | \r |
2fc59a00 | 925 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 926 | @param OrData The value to OR with the PCI configuration register.\r |
1a3eaf06 | 927 | \r |
d5979dc0 | 928 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 929 | \r |
930 | **/\r | |
931 | UINT32\r | |
932 | EFIAPI\r | |
933 | PciSegmentOr32 (\r | |
0c3437e0 | 934 | IN UINT64 Address,\r |
935 | IN UINT32 OrData\r | |
1a3eaf06 | 936 | )\r |
937 | {\r | |
938 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r | |
939 | }\r | |
940 | \r | |
941 | /**\r | |
122e2191 | 942 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
1a3eaf06 | 943 | \r |
122e2191 | 944 | Reads the 32-bit PCI configuration register specified by Address,\r |
945 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
946 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
947 | The value written to the PCI configuration register is returned.\r | |
948 | This function must guarantee that all PCI read and write operations are serialized.\r | |
949 | \r | |
1a3eaf06 | 950 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 951 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 952 | \r |
2fc59a00 | 953 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 954 | @param AndData The value to AND with the PCI configuration register.\r |
1a3eaf06 | 955 | \r |
122e2191 | 956 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 957 | \r |
958 | **/\r | |
959 | UINT32\r | |
960 | EFIAPI\r | |
961 | PciSegmentAnd32 (\r | |
0c3437e0 | 962 | IN UINT64 Address,\r |
963 | IN UINT32 AndData\r | |
1a3eaf06 | 964 | )\r |
965 | {\r | |
966 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r | |
967 | }\r | |
968 | \r | |
969 | /**\r | |
122e2191 | 970 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
62991af2 | 971 | followed a bitwise OR with another 32-bit value.\r |
122e2191 | 972 | \r |
973 | Reads the 32-bit PCI configuration register specified by Address,\r | |
974 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 975 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
122e2191 | 976 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
977 | The value written to the PCI configuration register is returned.\r | |
978 | This function must guarantee that all PCI read and write operations are serialized.\r | |
979 | \r | |
1a3eaf06 | 980 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 981 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 982 | \r |
2fc59a00 | 983 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 984 | @param AndData The value to AND with the PCI configuration register.\r |
985 | @param OrData The value to OR with the PCI configuration register.\r | |
1a3eaf06 | 986 | \r |
122e2191 | 987 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 988 | \r |
989 | **/\r | |
990 | UINT32\r | |
991 | EFIAPI\r | |
992 | PciSegmentAndThenOr32 (\r | |
0c3437e0 | 993 | IN UINT64 Address,\r |
994 | IN UINT32 AndData,\r | |
995 | IN UINT32 OrData\r | |
1a3eaf06 | 996 | )\r |
997 | {\r | |
998 | return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r | |
999 | }\r | |
1000 | \r | |
1001 | /**\r | |
1002 | Reads a bit field of a PCI configuration register.\r | |
1003 | \r | |
1004 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1005 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1006 | returned.\r | |
1007 | \r | |
1008 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 1009 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 1010 | If StartBit is greater than 31, then ASSERT().\r |
1011 | If EndBit is greater than 31, then ASSERT().\r | |
1012 | If EndBit is less than StartBit, then ASSERT().\r | |
1013 | \r | |
2fc59a00 | 1014 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 1015 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1016 | Range 0..31.\r | |
1017 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1018 | Range 0..31.\r | |
1019 | \r | |
1020 | @return The value of the bit field read from the PCI configuration register.\r | |
1021 | \r | |
1022 | **/\r | |
1023 | UINT32\r | |
1024 | EFIAPI\r | |
1025 | PciSegmentBitFieldRead32 (\r | |
0c3437e0 | 1026 | IN UINT64 Address,\r |
1027 | IN UINTN StartBit,\r | |
1028 | IN UINTN EndBit\r | |
1a3eaf06 | 1029 | )\r |
1030 | {\r | |
1031 | return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r | |
1032 | }\r | |
1033 | \r | |
1034 | /**\r | |
1035 | Writes a bit field to a PCI configuration register.\r | |
1036 | \r | |
1037 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1038 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1039 | destination PCI configuration register are preserved. The new value of the\r | |
1040 | 32-bit register is returned.\r | |
1041 | \r | |
1042 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 1043 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 1044 | If StartBit is greater than 31, then ASSERT().\r |
1045 | If EndBit is greater than 31, then ASSERT().\r | |
1046 | If EndBit is less than StartBit, then ASSERT().\r | |
1047 | \r | |
2fc59a00 | 1048 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1049 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1050 | Range 0..31.\r | |
1051 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1052 | Range 0..31.\r | |
2fc59a00 | 1053 | @param Value The new value of the bit field.\r |
1a3eaf06 | 1054 | \r |
1055 | @return The value written back to the PCI configuration register.\r | |
1056 | \r | |
1057 | **/\r | |
1058 | UINT32\r | |
1059 | EFIAPI\r | |
1060 | PciSegmentBitFieldWrite32 (\r | |
0c3437e0 | 1061 | IN UINT64 Address,\r |
1062 | IN UINTN StartBit,\r | |
1063 | IN UINTN EndBit,\r | |
1064 | IN UINT32 Value\r | |
1a3eaf06 | 1065 | )\r |
1066 | {\r | |
1067 | return PciSegmentWrite32 (\r | |
1068 | Address,\r | |
1069 | BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r | |
1070 | );\r | |
1071 | }\r | |
1072 | \r | |
1073 | /**\r | |
1074 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1075 | writes the result back to the bit field in the 32-bit port.\r | |
1076 | \r | |
1077 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1078 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 1079 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1080 | specified by Address. The value written to the PCI configuration register is\r | |
1081 | returned. This function must guarantee that all PCI read and write operations\r | |
1082 | are serialized. Extra left bits in OrData are stripped.\r | |
1083 | \r | |
1084 | If any reserved bits in Address are set, then ASSERT().\r | |
1085 | If StartBit is greater than 31, then ASSERT().\r | |
1086 | If EndBit is greater than 31, then ASSERT().\r | |
1087 | If EndBit is less than StartBit, then ASSERT().\r | |
1088 | \r | |
2fc59a00 | 1089 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1090 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1091 | Range 0..31.\r | |
1092 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1093 | Range 0..31.\r | |
1094 | @param OrData The value to OR with the PCI configuration register.\r | |
1095 | \r | |
1096 | @return The value written back to the PCI configuration register.\r | |
1097 | \r | |
1098 | **/\r | |
1099 | UINT32\r | |
1100 | EFIAPI\r | |
1101 | PciSegmentBitFieldOr32 (\r | |
0c3437e0 | 1102 | IN UINT64 Address,\r |
1103 | IN UINTN StartBit,\r | |
1104 | IN UINTN EndBit,\r | |
1105 | IN UINT32 OrData\r | |
1a3eaf06 | 1106 | )\r |
1107 | {\r | |
1108 | return PciSegmentWrite32 (\r | |
1109 | Address,\r | |
1110 | BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r | |
1111 | );\r | |
1112 | }\r | |
1113 | \r | |
1114 | /**\r | |
1115 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1116 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1117 | \r | |
0c3437e0 | 1118 | \r |
1119 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r | |
1120 | AND between the read result and the value specified by AndData, and writes the result\r | |
1121 | to the 32-bit PCI configuration register specified by Address. The value written to\r | |
1122 | the PCI configuration register is returned. This function must guarantee that all PCI\r | |
1123 | read and write operations are serialized. Extra left bits in AndData are stripped.\r | |
1a3eaf06 | 1124 | If any reserved bits in Address are set, then ASSERT().\r |
0c3437e0 | 1125 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 1126 | If StartBit is greater than 31, then ASSERT().\r |
1127 | If EndBit is greater than 31, then ASSERT().\r | |
1128 | If EndBit is less than StartBit, then ASSERT().\r | |
0c3437e0 | 1129 | \r |
1a3eaf06 | 1130 | \r |
2fc59a00 | 1131 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1132 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1133 | Range 0..31.\r | |
1134 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1135 | Range 0..31.\r | |
1136 | @param AndData The value to AND with the PCI configuration register.\r | |
1137 | \r | |
1138 | @return The value written back to the PCI configuration register.\r | |
1139 | \r | |
1140 | **/\r | |
1141 | UINT32\r | |
1142 | EFIAPI\r | |
1143 | PciSegmentBitFieldAnd32 (\r | |
0c3437e0 | 1144 | IN UINT64 Address,\r |
1145 | IN UINTN StartBit,\r | |
1146 | IN UINTN EndBit,\r | |
1147 | IN UINT32 AndData\r | |
1a3eaf06 | 1148 | )\r |
1149 | {\r | |
1150 | return PciSegmentWrite32 (\r | |
1151 | Address,\r | |
1152 | BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r | |
1153 | );\r | |
1154 | }\r | |
1155 | \r | |
1156 | /**\r | |
1157 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1158 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 1159 | 32-bit port.\r |
1160 | \r | |
1161 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1162 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 1163 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1164 | configuration register specified by Address. The value written to the PCI\r | |
1165 | configuration register is returned. This function must guarantee that all PCI\r | |
1166 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1167 | OrData are stripped.\r | |
1168 | \r | |
1169 | If any reserved bits in Address are set, then ASSERT().\r | |
1170 | If StartBit is greater than 31, then ASSERT().\r | |
1171 | If EndBit is greater than 31, then ASSERT().\r | |
1172 | If EndBit is less than StartBit, then ASSERT().\r | |
1173 | \r | |
2fc59a00 | 1174 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1175 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1176 | Range 0..31.\r | |
1177 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1178 | Range 0..31.\r | |
1179 | @param AndData The value to AND with the PCI configuration register.\r | |
1180 | @param OrData The value to OR with the result of the AND operation.\r | |
1181 | \r | |
1182 | @return The value written back to the PCI configuration register.\r | |
1183 | \r | |
1184 | **/\r | |
1185 | UINT32\r | |
1186 | EFIAPI\r | |
1187 | PciSegmentBitFieldAndThenOr32 (\r | |
0c3437e0 | 1188 | IN UINT64 Address,\r |
1189 | IN UINTN StartBit,\r | |
1190 | IN UINTN EndBit,\r | |
1191 | IN UINT32 AndData,\r | |
1192 | IN UINT32 OrData\r | |
1a3eaf06 | 1193 | )\r |
1194 | {\r | |
1195 | return PciSegmentWrite32 (\r | |
1196 | Address,\r | |
1197 | BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1198 | );\r | |
1199 | }\r | |
1200 | \r | |
1201 | /**\r | |
1202 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1203 | \r | |
0c3437e0 | 1204 | Reads the range of PCI configuration registers specified by StartAddress and\r |
1205 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1206 | configuration registers from a single PCI function to be read. Size is\r | |
1207 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1208 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1209 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1210 | end of the range.\r | |
1211 | \r | |
59ceeabe | 1212 | If any reserved bits in StartAddress are set, then ASSERT().\r |
1a3eaf06 | 1213 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
1214 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1215 | \r | |
2fc59a00 | 1216 | @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,\r |
0c3437e0 | 1217 | Function and Register.\r |
2fc59a00 | 1218 | @param Size The size in bytes of the transfer.\r |
1219 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1a3eaf06 | 1220 | \r |
0c3437e0 | 1221 | @return Size\r |
1a3eaf06 | 1222 | \r |
1223 | **/\r | |
1224 | UINTN\r | |
1225 | EFIAPI\r | |
1226 | PciSegmentReadBuffer (\r | |
0c3437e0 | 1227 | IN UINT64 StartAddress,\r |
1228 | IN UINTN Size,\r | |
1229 | OUT VOID *Buffer\r | |
1a3eaf06 | 1230 | )\r |
1231 | {\r | |
1232 | UINTN ReturnValue;\r | |
1233 | \r | |
1234 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1235 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1236 | \r | |
1237 | if (Size == 0) {\r | |
1238 | return Size;\r | |
1239 | }\r | |
1240 | \r | |
1241 | ASSERT (Buffer != NULL);\r | |
1242 | \r | |
1243 | //\r | |
1244 | // Save Size for return\r | |
1245 | //\r | |
1246 | ReturnValue = Size;\r | |
1247 | \r | |
e43e4b3e | 1248 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1249 | //\r |
1250 | // Read a byte if StartAddress is byte aligned\r | |
1251 | //\r | |
1252 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1253 | StartAddress += sizeof (UINT8);\r | |
1254 | Size -= sizeof (UINT8);\r | |
1255 | Buffer = (UINT8*)Buffer + 1;\r | |
1256 | }\r | |
1257 | \r | |
e43e4b3e | 1258 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1259 | //\r |
1260 | // Read a word if StartAddress is word aligned\r | |
1261 | //\r | |
5dc4fd78 | 1262 | WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r |
1a3eaf06 | 1263 | StartAddress += sizeof (UINT16);\r |
1264 | Size -= sizeof (UINT16);\r | |
1265 | Buffer = (UINT16*)Buffer + 1;\r | |
1266 | }\r | |
1267 | \r | |
1268 | while (Size >= sizeof (UINT32)) {\r | |
1269 | //\r | |
1270 | // Read as many double words as possible\r | |
1271 | //\r | |
5dc4fd78 | 1272 | WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r |
1a3eaf06 | 1273 | StartAddress += sizeof (UINT32);\r |
1274 | Size -= sizeof (UINT32);\r | |
1275 | Buffer = (UINT32*)Buffer + 1;\r | |
1276 | }\r | |
1277 | \r | |
1278 | if (Size >= sizeof (UINT16)) {\r | |
1279 | //\r | |
1280 | // Read the last remaining word if exist\r | |
1281 | //\r | |
5dc4fd78 | 1282 | WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r |
1a3eaf06 | 1283 | StartAddress += sizeof (UINT16);\r |
1284 | Size -= sizeof (UINT16);\r | |
1285 | Buffer = (UINT16*)Buffer + 1;\r | |
1286 | }\r | |
1287 | \r | |
1288 | if (Size >= sizeof (UINT8)) {\r | |
1289 | //\r | |
1290 | // Read the last remaining byte if exist\r | |
1291 | //\r | |
1292 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1293 | }\r | |
1294 | \r | |
1295 | return ReturnValue;\r | |
1296 | }\r | |
1297 | \r | |
d5979dc0 | 1298 | \r |
1a3eaf06 | 1299 | /**\r |
0c3437e0 | 1300 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
1301 | configuration space.\r | |
1302 | \r | |
1303 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1304 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1305 | configuration registers from a single PCI function to be written. Size is\r | |
1306 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1307 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1308 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1309 | and the end of the range.\r | |
1310 | \r | |
59ceeabe | 1311 | If any reserved bits in StartAddress are set, then ASSERT().\r |
1a3eaf06 | 1312 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
1313 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1314 | \r | |
2fc59a00 | 1315 | @param StartAddress The starting address that encodes the PCI Segment, Bus, Device,\r |
0c3437e0 | 1316 | Function and Register.\r |
2fc59a00 | 1317 | @param Size The size in bytes of the transfer.\r |
1318 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1a3eaf06 | 1319 | \r |
d5979dc0 | 1320 | @return The parameter of Size.\r |
1a3eaf06 | 1321 | \r |
1322 | **/\r | |
1323 | UINTN\r | |
1324 | EFIAPI\r | |
1325 | PciSegmentWriteBuffer (\r | |
0c3437e0 | 1326 | IN UINT64 StartAddress,\r |
1327 | IN UINTN Size,\r | |
1328 | IN VOID *Buffer\r | |
1a3eaf06 | 1329 | )\r |
1330 | {\r | |
1331 | UINTN ReturnValue;\r | |
1332 | \r | |
1333 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1334 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1335 | \r | |
1336 | if (Size == 0) {\r | |
1337 | return 0;\r | |
1338 | }\r | |
1339 | \r | |
1340 | ASSERT (Buffer != NULL);\r | |
1341 | \r | |
1342 | //\r | |
1343 | // Save Size for return\r | |
1344 | //\r | |
1345 | ReturnValue = Size;\r | |
1346 | \r | |
e43e4b3e | 1347 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1348 | //\r |
1349 | // Write a byte if StartAddress is byte aligned\r | |
1350 | //\r | |
1351 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1352 | StartAddress += sizeof (UINT8);\r | |
1353 | Size -= sizeof (UINT8);\r | |
1354 | Buffer = (UINT8*)Buffer + 1;\r | |
1355 | }\r | |
1356 | \r | |
e43e4b3e | 1357 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1358 | //\r |
1359 | // Write a word if StartAddress is word aligned\r | |
1360 | //\r | |
5dc4fd78 | 1361 | PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1362 | StartAddress += sizeof (UINT16);\r |
1363 | Size -= sizeof (UINT16);\r | |
1364 | Buffer = (UINT16*)Buffer + 1;\r | |
1365 | }\r | |
1366 | \r | |
1367 | while (Size >= sizeof (UINT32)) {\r | |
1368 | //\r | |
1369 | // Write as many double words as possible\r | |
1370 | //\r | |
5dc4fd78 | 1371 | PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r |
1a3eaf06 | 1372 | StartAddress += sizeof (UINT32);\r |
1373 | Size -= sizeof (UINT32);\r | |
1374 | Buffer = (UINT32*)Buffer + 1;\r | |
1375 | }\r | |
1376 | \r | |
1377 | if (Size >= sizeof (UINT16)) {\r | |
1378 | //\r | |
1379 | // Write the last remaining word if exist\r | |
1380 | //\r | |
5dc4fd78 | 1381 | PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1382 | StartAddress += sizeof (UINT16);\r |
1383 | Size -= sizeof (UINT16);\r | |
1384 | Buffer = (UINT16*)Buffer + 1;\r | |
1385 | }\r | |
1386 | \r | |
1387 | if (Size >= sizeof (UINT8)) {\r | |
1388 | //\r | |
1389 | // Write the last remaining byte if exist\r | |
1390 | //\r | |
1391 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1392 | }\r | |
1393 | \r | |
1394 | return ReturnValue;\r | |
1395 | }\r |