MdePkg/PciSegmentLib: Fix typo in function header comments
[mirror_edk2.git] / MdePkg / Library / PeiPciSegmentLibPciCfg2 / PciSegmentLib.c
CommitLineData
1a3eaf06 1/** @file\r
2 PCI Segment Library implementation using PCI CFG2 PPI.\r
3\r
ebdde8ff 4 Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
19388d29 5 This program and the accompanying materials are\r
1a3eaf06 6 licensed and made available under the terms and conditions of\r
7 the BSD License which accompanies this distribution. The full\r
8 text of the license may be found at\r
2fc59a00 9 http://opensource.org/licenses/bsd-license.php.\r
1a3eaf06 10 \r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include <PiPei.h>\r
17\r
18#include <Ppi/PciCfg2.h>\r
19\r
20#include <Library/PciSegmentLib.h>\r
21#include <Library/BaseLib.h>\r
22#include <Library/PeiServicesTablePointerLib.h>\r
23#include <Library/DebugLib.h>\r
24#include <Library/PeiServicesLib.h>\r
25\r
26/**\r
27 Assert the validity of a PCI Segment address.\r
59ceeabe 28 A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r
1a3eaf06 29\r
30 @param A The address to validate.\r
31 @param M Additional bits to assert to be zero.\r
32\r
33**/\r
34#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
59ceeabe 35 ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
1a3eaf06 36\r
37/**\r
38 Translate PCI Lib address into format of PCI CFG2 PPI.\r
39\r
2fc59a00 40 @param A The address that encodes the PCI Bus, Device, Function and\r
1a3eaf06 41 Register.\r
42\r
43**/\r
44#define PCI_TO_PCICFG2_ADDRESS(A) \\r
f5305d5a 45 ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r
1a3eaf06 46\r
47/**\r
48 Gets PCI CFG2 PPI.\r
49\r
50 This internal function retrieves PCI CFG2 PPI from PPI database.\r
51\r
58380e9c 52 @param Address The address that encodes the PCI Segment, Bus, Device, \r
53 Function and Register.\r
1a3eaf06 54\r
55 @return The pointer to PCI CFG2 PPI.\r
56\r
57**/\r
58EFI_PEI_PCI_CFG2_PPI *\r
59InternalGetPciCfg2Ppi (\r
60 IN UINT64 Address\r
61 )\r
62{\r
63 EFI_STATUS Status;\r
64 UINTN Instance;\r
65 EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
66 UINT64 SegmentNumber;\r
67\r
68 Instance = 0;\r
69 PciCfg2Ppi = NULL;\r
70 SegmentNumber = BitFieldRead64 (Address, 32, 63);\r
71\r
72 //\r
73 // Loop through all instances of the PPI and match segment number\r
74 //\r
75 do {\r
76 Status = PeiServicesLocatePpi(\r
77 &gEfiPciCfg2PpiGuid,\r
78 Instance,\r
79 NULL,\r
80 (VOID**) &PciCfg2Ppi\r
81 );\r
82 ASSERT_EFI_ERROR (Status);\r
83 Instance++;\r
84 } while (PciCfg2Ppi->Segment != SegmentNumber);\r
85\r
86 return PciCfg2Ppi;\r
87}\r
88\r
89/**\r
90 Internal worker function to read a PCI configuration register.\r
91\r
92 This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r
93 It reads and returns the PCI configuration register specified by Address,\r
94 the width of data is specified by Width.\r
95\r
2fc59a00 96 @param Address The address that encodes the PCI Bus, Device, Function and\r
1a3eaf06 97 Register.\r
58380e9c 98 @param Width The width of data to read\r
1a3eaf06 99\r
100 @return The value read from the PCI configuration register.\r
101\r
102**/\r
103UINT32\r
104PeiPciSegmentLibPciCfg2ReadWorker (\r
105 IN UINT64 Address,\r
106 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r
107 )\r
108{\r
109 UINT32 Data;\r
110 CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
43fe5cdc 111 UINT64 PciCfg2Address;\r
1a3eaf06 112\r
113 PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
43fe5cdc 114 PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r
1a3eaf06 115 PciCfg2Ppi->Read (\r
116 GetPeiServicesTablePointer (),\r
117 PciCfg2Ppi,\r
118 Width,\r
43fe5cdc 119 PciCfg2Address,\r
1a3eaf06 120 &Data\r
121 );\r
122\r
123 return Data;\r
124}\r
125\r
126/**\r
127 Internal worker function to writes a PCI configuration register.\r
128\r
129 This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r
130 It writes the PCI configuration register specified by Address with the\r
131 value specified by Data. The width of data is specifed by Width.\r
132 Data is returned.\r
133\r
2fc59a00 134 @param Address The address that encodes the PCI Bus, Device, Function and\r
1a3eaf06 135 Register.\r
58380e9c 136 @param Width The width of data to write\r
1a3eaf06 137 @param Data The value to write.\r
138\r
139 @return The value written to the PCI configuration register.\r
140\r
141**/\r
142UINT32\r
143PeiPciSegmentLibPciCfg2WriteWorker (\r
144 IN UINT64 Address,\r
145 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
146 IN UINT32 Data\r
147 )\r
148{\r
149 CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
43fe5cdc 150 UINT64 PciCfg2Address;\r
1a3eaf06 151\r
152 PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
43fe5cdc 153 PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r
1a3eaf06 154 PciCfg2Ppi->Write (\r
155 GetPeiServicesTablePointer (),\r
156 PciCfg2Ppi,\r
157 Width,\r
43fe5cdc 158 PciCfg2Address,\r
1a3eaf06 159 &Data\r
160 );\r
161\r
162 return Data;\r
163}\r
164\r
3e3ae634 165/**\r
166 Register a PCI device so PCI configuration registers may be accessed after \r
167 SetVirtualAddressMap().\r
168 \r
59ceeabe 169 If any reserved bits in Address are set, then ASSERT().\r
3e3ae634 170\r
ebdde8ff 171 @param Address Address that encodes the PCI Bus, Device, Function and\r
3e3ae634 172 Register.\r
173 \r
174 @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r
175 @retval RETURN_UNSUPPORTED An attempt was made to call this function \r
176 after ExitBootServices().\r
177 @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r
178 at runtime could not be mapped.\r
179 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r
180 complete the registration.\r
181\r
182**/\r
183RETURN_STATUS\r
184EFIAPI\r
185PciSegmentRegisterForRuntimeAccess (\r
186 IN UINTN Address\r
187 )\r
188{\r
59ceeabe 189 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
3e3ae634 190 return RETURN_UNSUPPORTED;\r
191}\r
192\r
1a3eaf06 193/**\r
194 Reads an 8-bit PCI configuration register.\r
195\r
196 Reads and returns the 8-bit PCI configuration register specified by Address.\r
d5979dc0 197 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 198\r
1a3eaf06 199 If any reserved bits in Address are set, then ASSERT().\r
ebdde8ff
RN
200\r
201 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
1a3eaf06 202\r
d5979dc0 203 @return The 8-bit PCI configuration register specified by Address.\r
1a3eaf06 204\r
205**/\r
206UINT8\r
207EFIAPI\r
208PciSegmentRead8 (\r
0c3437e0 209 IN UINT64 Address\r
1a3eaf06 210 )\r
211{\r
212 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
213\r
214 return (UINT8) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r
215}\r
216\r
217/**\r
218 Writes an 8-bit PCI configuration register.\r
219\r
d5979dc0 220 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
221 Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 222\r
59ceeabe 223 If any reserved bits in Address are set, then ASSERT().\r
1a3eaf06 224\r
ebdde8ff 225 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
d5979dc0 226 @param Value The value to write.\r
1a3eaf06 227\r
228 @return The value written to the PCI configuration register.\r
229\r
230**/\r
231UINT8\r
232EFIAPI\r
233PciSegmentWrite8 (\r
0c3437e0 234 IN UINT64 Address,\r
235 IN UINT8 Value\r
1a3eaf06 236 )\r
237{\r
238 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
239\r
d5979dc0 240 return (UINT8) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r
1a3eaf06 241}\r
242\r
243/**\r
62991af2 244 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r
1a3eaf06 245\r
d5979dc0 246 Reads the 8-bit PCI configuration register specified by Address,\r
62991af2 247 performs a bitwise OR between the read result and the value specified by OrData,\r
d5979dc0 248 and writes the result to the 8-bit PCI configuration register specified by Address.\r
249 The value written to the PCI configuration register is returned.\r
250 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 251\r
1a3eaf06 252 If any reserved bits in Address are set, then ASSERT().\r
253\r
ebdde8ff 254 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
d5979dc0 255 @param OrData The value to OR with the PCI configuration register.\r
1a3eaf06 256\r
d5979dc0 257 @return The value written to the PCI configuration register.\r
1a3eaf06 258\r
259**/\r
260UINT8\r
261EFIAPI\r
262PciSegmentOr8 (\r
0c3437e0 263 IN UINT64 Address,\r
264 IN UINT8 OrData\r
1a3eaf06 265 )\r
266{\r
267 return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
268}\r
269\r
270/**\r
122e2191 271 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
1a3eaf06 272\r
122e2191 273 Reads the 8-bit PCI configuration register specified by Address,\r
274 performs a bitwise AND between the read result and the value specified by AndData,\r
275 and writes the result to the 8-bit PCI configuration register specified by Address.\r
276 The value written to the PCI configuration register is returned.\r
277 This function must guarantee that all PCI read and write operations are serialized.\r
1a3eaf06 278 If any reserved bits in Address are set, then ASSERT().\r
279\r
ebdde8ff 280 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
122e2191 281 @param AndData The value to AND with the PCI configuration register.\r
1a3eaf06 282\r
122e2191 283 @return The value written to the PCI configuration register.\r
1a3eaf06 284\r
285**/\r
286UINT8\r
287EFIAPI\r
288PciSegmentAnd8 (\r
0c3437e0 289 IN UINT64 Address,\r
290 IN UINT8 AndData\r
1a3eaf06 291 )\r
292{\r
293 return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
294}\r
295\r
296/**\r
122e2191 297 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
62991af2 298 followed a bitwise OR with another 8-bit value.\r
ebdde8ff 299\r
122e2191 300 Reads the 8-bit PCI configuration register specified by Address,\r
301 performs a bitwise AND between the read result and the value specified by AndData,\r
62991af2 302 performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
122e2191 303 and writes the result to the 8-bit PCI configuration register specified by Address.\r
304 The value written to the PCI configuration register is returned.\r
305 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 306\r
1a3eaf06 307 If any reserved bits in Address are set, then ASSERT().\r
308\r
ebdde8ff
RN
309 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
310 @param AndData The value to AND with the PCI configuration register.\r
122e2191 311 @param OrData The value to OR with the PCI configuration register.\r
1a3eaf06 312\r
122e2191 313 @return The value written to the PCI configuration register.\r
1a3eaf06 314\r
315**/\r
316UINT8\r
317EFIAPI\r
318PciSegmentAndThenOr8 (\r
0c3437e0 319 IN UINT64 Address,\r
320 IN UINT8 AndData,\r
321 IN UINT8 OrData\r
1a3eaf06 322 )\r
323{\r
324 return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
325}\r
326\r
327/**\r
328 Reads a bit field of a PCI configuration register.\r
329\r
330 Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
331 specified by the StartBit and the EndBit. The value of the bit field is\r
332 returned.\r
333\r
334 If any reserved bits in Address are set, then ASSERT().\r
335 If StartBit is greater than 7, then ASSERT().\r
336 If EndBit is greater than 7, then ASSERT().\r
337 If EndBit is less than StartBit, then ASSERT().\r
338\r
ebdde8ff 339 @param Address PCI configuration register to read.\r
1a3eaf06 340 @param StartBit The ordinal of the least significant bit in the bit field.\r
341 Range 0..7.\r
342 @param EndBit The ordinal of the most significant bit in the bit field.\r
343 Range 0..7.\r
344\r
345 @return The value of the bit field read from the PCI configuration register.\r
346\r
347**/\r
348UINT8\r
349EFIAPI\r
350PciSegmentBitFieldRead8 (\r
0c3437e0 351 IN UINT64 Address,\r
352 IN UINTN StartBit,\r
353 IN UINTN EndBit\r
1a3eaf06 354 )\r
355{\r
356 return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
357}\r
358\r
359/**\r
360 Writes a bit field to a PCI configuration register.\r
361\r
362 Writes Value to the bit field of the PCI configuration register. The bit\r
363 field is specified by the StartBit and the EndBit. All other bits in the\r
364 destination PCI configuration register are preserved. The new value of the\r
365 8-bit register is returned.\r
366\r
367 If any reserved bits in Address are set, then ASSERT().\r
368 If StartBit is greater than 7, then ASSERT().\r
369 If EndBit is greater than 7, then ASSERT().\r
370 If EndBit is less than StartBit, then ASSERT().\r
94952554 371 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 372\r
ebdde8ff 373 @param Address PCI configuration register to write.\r
1a3eaf06 374 @param StartBit The ordinal of the least significant bit in the bit field.\r
375 Range 0..7.\r
376 @param EndBit The ordinal of the most significant bit in the bit field.\r
377 Range 0..7.\r
ebdde8ff 378 @param Value New value of the bit field.\r
1a3eaf06 379\r
380 @return The value written back to the PCI configuration register.\r
381\r
382**/\r
383UINT8\r
384EFIAPI\r
385PciSegmentBitFieldWrite8 (\r
0c3437e0 386 IN UINT64 Address,\r
387 IN UINTN StartBit,\r
388 IN UINTN EndBit,\r
389 IN UINT8 Value\r
1a3eaf06 390 )\r
391{\r
392 return PciSegmentWrite8 (\r
393 Address,\r
394 BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r
395 );\r
396}\r
397\r
398/**\r
399 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
400 writes the result back to the bit field in the 8-bit port.\r
401\r
402 Reads the 8-bit PCI configuration register specified by Address, performs a\r
62991af2 403 bitwise OR between the read result and the value specified by\r
1a3eaf06 404 OrData, and writes the result to the 8-bit PCI configuration register\r
405 specified by Address. The value written to the PCI configuration register is\r
406 returned. This function must guarantee that all PCI read and write operations\r
407 are serialized. Extra left bits in OrData are stripped.\r
408\r
409 If any reserved bits in Address are set, then ASSERT().\r
410 If StartBit is greater than 7, then ASSERT().\r
411 If EndBit is greater than 7, then ASSERT().\r
412 If EndBit is less than StartBit, then ASSERT().\r
94952554 413 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 414\r
ebdde8ff 415 @param Address PCI configuration register to write.\r
1a3eaf06 416 @param StartBit The ordinal of the least significant bit in the bit field.\r
417 Range 0..7.\r
418 @param EndBit The ordinal of the most significant bit in the bit field.\r
419 Range 0..7.\r
420 @param OrData The value to OR with the PCI configuration register.\r
421\r
422 @return The value written back to the PCI configuration register.\r
423\r
424**/\r
425UINT8\r
426EFIAPI\r
427PciSegmentBitFieldOr8 (\r
0c3437e0 428 IN UINT64 Address,\r
429 IN UINTN StartBit,\r
430 IN UINTN EndBit,\r
431 IN UINT8 OrData\r
1a3eaf06 432 )\r
433{\r
434 return PciSegmentWrite8 (\r
435 Address,\r
436 BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r
437 );\r
438}\r
439\r
440/**\r
441 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
442 AND, and writes the result back to the bit field in the 8-bit register.\r
443\r
444 Reads the 8-bit PCI configuration register specified by Address, performs a\r
445 bitwise AND between the read result and the value specified by AndData, and\r
446 writes the result to the 8-bit PCI configuration register specified by\r
447 Address. The value written to the PCI configuration register is returned.\r
448 This function must guarantee that all PCI read and write operations are\r
449 serialized. Extra left bits in AndData are stripped.\r
450\r
451 If any reserved bits in Address are set, then ASSERT().\r
452 If StartBit is greater than 7, then ASSERT().\r
453 If EndBit is greater than 7, then ASSERT().\r
454 If EndBit is less than StartBit, then ASSERT().\r
94952554 455 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 456\r
ebdde8ff 457 @param Address PCI configuration register to write.\r
1a3eaf06 458 @param StartBit The ordinal of the least significant bit in the bit field.\r
459 Range 0..7.\r
460 @param EndBit The ordinal of the most significant bit in the bit field.\r
461 Range 0..7.\r
462 @param AndData The value to AND with the PCI configuration register.\r
463\r
464 @return The value written back to the PCI configuration register.\r
465\r
466**/\r
467UINT8\r
468EFIAPI\r
469PciSegmentBitFieldAnd8 (\r
0c3437e0 470 IN UINT64 Address,\r
471 IN UINTN StartBit,\r
472 IN UINTN EndBit,\r
473 IN UINT8 AndData\r
1a3eaf06 474 )\r
475{\r
476 return PciSegmentWrite8 (\r
477 Address,\r
478 BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r
479 );\r
480}\r
481\r
482/**\r
483 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
ebdde8ff 484 bitwise OR, and writes the result back to the bit field in the 8-bit port.\r
1a3eaf06 485\r
486 Reads the 8-bit PCI configuration register specified by Address, performs a\r
62991af2 487 bitwise AND followed by a bitwise OR between the read result and\r
1a3eaf06 488 the value specified by AndData, and writes the result to the 8-bit PCI\r
489 configuration register specified by Address. The value written to the PCI\r
490 configuration register is returned. This function must guarantee that all PCI\r
491 read and write operations are serialized. Extra left bits in both AndData and\r
492 OrData are stripped.\r
493\r
494 If any reserved bits in Address are set, then ASSERT().\r
495 If StartBit is greater than 7, then ASSERT().\r
496 If EndBit is greater than 7, then ASSERT().\r
497 If EndBit is less than StartBit, then ASSERT().\r
94952554
LG
498 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
499 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 500\r
ebdde8ff 501 @param Address PCI configuration register to write.\r
1a3eaf06 502 @param StartBit The ordinal of the least significant bit in the bit field.\r
503 Range 0..7.\r
504 @param EndBit The ordinal of the most significant bit in the bit field.\r
505 Range 0..7.\r
506 @param AndData The value to AND with the PCI configuration register.\r
507 @param OrData The value to OR with the result of the AND operation.\r
508\r
509 @return The value written back to the PCI configuration register.\r
510\r
511**/\r
512UINT8\r
513EFIAPI\r
514PciSegmentBitFieldAndThenOr8 (\r
0c3437e0 515 IN UINT64 Address,\r
516 IN UINTN StartBit,\r
517 IN UINTN EndBit,\r
518 IN UINT8 AndData,\r
519 IN UINT8 OrData\r
1a3eaf06 520 )\r
521{\r
522 return PciSegmentWrite8 (\r
523 Address,\r
524 BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r
525 );\r
526}\r
527\r
528/**\r
529 Reads a 16-bit PCI configuration register.\r
530\r
531 Reads and returns the 16-bit PCI configuration register specified by Address.\r
d5979dc0 532 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 533\r
1a3eaf06 534 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 535 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
ebdde8ff
RN
536\r
537 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
1a3eaf06 538\r
d5979dc0 539 @return The 16-bit PCI configuration register specified by Address.\r
1a3eaf06 540\r
541**/\r
542UINT16\r
543EFIAPI\r
544PciSegmentRead16 (\r
0c3437e0 545 IN UINT64 Address\r
1a3eaf06 546 )\r
547{\r
548 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
549\r
550 return (UINT16) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r
551}\r
552\r
553/**\r
554 Writes a 16-bit PCI configuration register.\r
555\r
d5979dc0 556 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
557 Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 558\r
1a3eaf06 559 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 560 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
1a3eaf06 561\r
ebdde8ff 562 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
d5979dc0 563 @param Value The value to write.\r
1a3eaf06 564\r
d5979dc0 565 @return The parameter of Value.\r
1a3eaf06 566\r
567**/\r
568UINT16\r
569EFIAPI\r
570PciSegmentWrite16 (\r
0c3437e0 571 IN UINT64 Address,\r
572 IN UINT16 Value\r
1a3eaf06 573 )\r
574{\r
575 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
576\r
d5979dc0 577 return (UINT16) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r
1a3eaf06 578}\r
579\r
580/**\r
62991af2 581 Performs a bitwise OR of a 16-bit PCI configuration register with\r
1a3eaf06 582 a 16-bit value.\r
583\r
584 Reads the 16-bit PCI configuration register specified by Address, performs a\r
ebdde8ff
RN
585 bitwise OR between the read result and the value specified by OrData, and\r
586 writes the result to the 16-bit PCI configuration register specified by Address.\r
587 The value written to the PCI configuration register is returned. This function\r
588 must guarantee that all PCI read and write operations are serialized.\r
1a3eaf06 589\r
590 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 591 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
1a3eaf06 592\r
ebdde8ff 593 @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
1a3eaf06 594 Register.\r
595 @param OrData The value to OR with the PCI configuration register.\r
596\r
597 @return The value written back to the PCI configuration register.\r
598\r
599**/\r
600UINT16\r
601EFIAPI\r
602PciSegmentOr16 (\r
0c3437e0 603 IN UINT64 Address,\r
604 IN UINT16 OrData\r
1a3eaf06 605 )\r
606{\r
607 return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
608}\r
609\r
610/**\r
122e2191 611 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
1a3eaf06 612\r
122e2191 613 Reads the 16-bit PCI configuration register specified by Address,\r
614 performs a bitwise AND between the read result and the value specified by AndData,\r
615 and writes the result to the 16-bit PCI configuration register specified by Address.\r
616 The value written to the PCI configuration register is returned.\r
617 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 618\r
1a3eaf06 619 If any reserved bits in Address are set, then ASSERT().\r
122e2191 620 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
ebdde8ff
RN
621\r
622 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
122e2191 623 @param AndData The value to AND with the PCI configuration register.\r
1a3eaf06 624\r
122e2191 625 @return The value written to the PCI configuration register.\r
1a3eaf06 626\r
627**/\r
628UINT16\r
629EFIAPI\r
630PciSegmentAnd16 (\r
0c3437e0 631 IN UINT64 Address,\r
632 IN UINT16 AndData\r
1a3eaf06 633 )\r
634{\r
635 return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
636}\r
637\r
638/**\r
d5979dc0 639 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
62991af2 640 followed a bitwise OR with another 16-bit value.\r
ebdde8ff 641\r
d5979dc0 642 Reads the 16-bit PCI configuration register specified by Address,\r
643 performs a bitwise AND between the read result and the value specified by AndData,\r
62991af2 644 performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
d5979dc0 645 and writes the result to the 16-bit PCI configuration register specified by Address.\r
646 The value written to the PCI configuration register is returned.\r
647 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 648\r
1a3eaf06 649 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 650 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
1a3eaf06 651\r
ebdde8ff 652 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
58380e9c 653 @param AndData The value to AND with the PCI configuration register.\r
d5979dc0 654 @param OrData The value to OR with the PCI configuration register.\r
1a3eaf06 655\r
d5979dc0 656 @return The value written to the PCI configuration register.\r
1a3eaf06 657\r
658**/\r
659UINT16\r
660EFIAPI\r
661PciSegmentAndThenOr16 (\r
0c3437e0 662 IN UINT64 Address,\r
663 IN UINT16 AndData,\r
664 IN UINT16 OrData\r
1a3eaf06 665 )\r
666{\r
667 return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
668}\r
669\r
670/**\r
671 Reads a bit field of a PCI configuration register.\r
672\r
673 Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
674 specified by the StartBit and the EndBit. The value of the bit field is\r
675 returned.\r
676\r
677 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 678 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
1a3eaf06 679 If StartBit is greater than 15, then ASSERT().\r
680 If EndBit is greater than 15, then ASSERT().\r
681 If EndBit is less than StartBit, then ASSERT().\r
682\r
ebdde8ff 683 @param Address PCI configuration register to read.\r
1a3eaf06 684 @param StartBit The ordinal of the least significant bit in the bit field.\r
685 Range 0..15.\r
686 @param EndBit The ordinal of the most significant bit in the bit field.\r
687 Range 0..15.\r
688\r
689 @return The value of the bit field read from the PCI configuration register.\r
690\r
691**/\r
692UINT16\r
693EFIAPI\r
694PciSegmentBitFieldRead16 (\r
0c3437e0 695 IN UINT64 Address,\r
696 IN UINTN StartBit,\r
697 IN UINTN EndBit\r
1a3eaf06 698 )\r
699{\r
700 return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
701}\r
702\r
703/**\r
704 Writes a bit field to a PCI configuration register.\r
705\r
706 Writes Value to the bit field of the PCI configuration register. The bit\r
707 field is specified by the StartBit and the EndBit. All other bits in the\r
708 destination PCI configuration register are preserved. The new value of the\r
709 16-bit register is returned.\r
710\r
711 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 712 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
1a3eaf06 713 If StartBit is greater than 15, then ASSERT().\r
714 If EndBit is greater than 15, then ASSERT().\r
715 If EndBit is less than StartBit, then ASSERT().\r
94952554 716 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 717\r
ebdde8ff 718 @param Address PCI configuration register to write.\r
1a3eaf06 719 @param StartBit The ordinal of the least significant bit in the bit field.\r
720 Range 0..15.\r
721 @param EndBit The ordinal of the most significant bit in the bit field.\r
722 Range 0..15.\r
ebdde8ff 723 @param Value New value of the bit field.\r
1a3eaf06 724\r
725 @return The value written back to the PCI configuration register.\r
726\r
727**/\r
728UINT16\r
729EFIAPI\r
730PciSegmentBitFieldWrite16 (\r
0c3437e0 731 IN UINT64 Address,\r
732 IN UINTN StartBit,\r
733 IN UINTN EndBit,\r
734 IN UINT16 Value\r
1a3eaf06 735 )\r
736{\r
737 return PciSegmentWrite16 (\r
738 Address,\r
739 BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r
740 );\r
741}\r
742\r
743/**\r
ebdde8ff
RN
744 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r
745 the result back to the bit field in the 16-bit port.\r
746\r
747 Reads the 16-bit PCI configuration register specified by Address, performs a\r
748 bitwise OR between the read result and the value specified by\r
749 OrData, and writes the result to the 16-bit PCI configuration register\r
750 specified by Address. The value written to the PCI configuration register is\r
751 returned. This function must guarantee that all PCI read and write operations\r
752 are serialized. Extra left bits in OrData are stripped.\r
1a3eaf06 753\r
754 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 755 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
1a3eaf06 756 If StartBit is greater than 15, then ASSERT().\r
757 If EndBit is greater than 15, then ASSERT().\r
758 If EndBit is less than StartBit, then ASSERT().\r
94952554 759 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 760\r
ebdde8ff 761 @param Address PCI configuration register to write.\r
1a3eaf06 762 @param StartBit The ordinal of the least significant bit in the bit field.\r
763 Range 0..15.\r
764 @param EndBit The ordinal of the most significant bit in the bit field.\r
765 Range 0..15.\r
766 @param OrData The value to OR with the PCI configuration register.\r
767\r
768 @return The value written back to the PCI configuration register.\r
769\r
770**/\r
771UINT16\r
772EFIAPI\r
773PciSegmentBitFieldOr16 (\r
0c3437e0 774 IN UINT64 Address,\r
775 IN UINTN StartBit,\r
776 IN UINTN EndBit,\r
777 IN UINT16 OrData\r
1a3eaf06 778 )\r
779{\r
780 return PciSegmentWrite16 (\r
781 Address,\r
782 BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r
783 );\r
784}\r
785\r
786/**\r
ebdde8ff
RN
787 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
788 AND, writes the result back to the bit field in the 16-bit register.\r
789\r
790 Reads the 16-bit PCI configuration register specified by Address, performs a\r
791 bitwise AND between the read result and the value specified by AndData, and\r
792 writes the result to the 16-bit PCI configuration register specified by\r
793 Address. The value written to the PCI configuration register is returned.\r
794 This function must guarantee that all PCI read and write operations are\r
795 serialized. Extra left bits in AndData are stripped.\r
1a3eaf06 796\r
797 If any reserved bits in Address are set, then ASSERT().\r
0c3437e0 798 If Address is not aligned on a 16-bit boundary, then ASSERT().\r
ebdde8ff
RN
799 If StartBit is greater than 15, then ASSERT().\r
800 If EndBit is greater than 15, then ASSERT().\r
1a3eaf06 801 If EndBit is less than StartBit, then ASSERT().\r
94952554 802 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 803\r
ebdde8ff 804 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
1a3eaf06 805 @param StartBit The ordinal of the least significant bit in the bit field.\r
ebdde8ff 806 Range 0..15.\r
1a3eaf06 807 @param EndBit The ordinal of the most significant bit in the bit field.\r
ebdde8ff
RN
808 Range 0..15.\r
809 @param AndData The value to AND with the PCI configuration register.\r
1a3eaf06 810\r
ebdde8ff 811 @return The value written back to the PCI configuration register.\r
1a3eaf06 812\r
813**/\r
814UINT16\r
815EFIAPI\r
816PciSegmentBitFieldAnd16 (\r
0c3437e0 817 IN UINT64 Address,\r
818 IN UINTN StartBit,\r
819 IN UINTN EndBit,\r
820 IN UINT16 AndData\r
1a3eaf06 821 )\r
822{\r
823 return PciSegmentWrite16 (\r
824 Address,\r
825 BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r
826 );\r
827}\r
828\r
829/**\r
830 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
62991af2 831 bitwise OR, and writes the result back to the bit field in the\r
1a3eaf06 832 16-bit port.\r
833\r
834 Reads the 16-bit PCI configuration register specified by Address, performs a\r
62991af2 835 bitwise AND followed by a bitwise OR between the read result and\r
1a3eaf06 836 the value specified by AndData, and writes the result to the 16-bit PCI\r
837 configuration register specified by Address. The value written to the PCI\r
838 configuration register is returned. This function must guarantee that all PCI\r
839 read and write operations are serialized. Extra left bits in both AndData and\r
840 OrData are stripped.\r
841\r
842 If any reserved bits in Address are set, then ASSERT().\r
843 If StartBit is greater than 15, then ASSERT().\r
844 If EndBit is greater than 15, then ASSERT().\r
845 If EndBit is less than StartBit, then ASSERT().\r
94952554
LG
846 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
847 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 848\r
ebdde8ff 849 @param Address PCI configuration register to write.\r
1a3eaf06 850 @param StartBit The ordinal of the least significant bit in the bit field.\r
851 Range 0..15.\r
852 @param EndBit The ordinal of the most significant bit in the bit field.\r
853 Range 0..15.\r
854 @param AndData The value to AND with the PCI configuration register.\r
855 @param OrData The value to OR with the result of the AND operation.\r
856\r
857 @return The value written back to the PCI configuration register.\r
858\r
859**/\r
860UINT16\r
861EFIAPI\r
862PciSegmentBitFieldAndThenOr16 (\r
0c3437e0 863 IN UINT64 Address,\r
864 IN UINTN StartBit,\r
865 IN UINTN EndBit,\r
866 IN UINT16 AndData,\r
867 IN UINT16 OrData\r
1a3eaf06 868 )\r
869{\r
870 return PciSegmentWrite16 (\r
871 Address,\r
872 BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r
873 );\r
874}\r
875\r
876/**\r
877 Reads a 32-bit PCI configuration register.\r
878\r
879 Reads and returns the 32-bit PCI configuration register specified by Address.\r
d5979dc0 880 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 881\r
1a3eaf06 882 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 883 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 884\r
ebdde8ff 885 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
1a3eaf06 886\r
d5979dc0 887 @return The 32-bit PCI configuration register specified by Address.\r
1a3eaf06 888\r
889**/\r
890UINT32\r
891EFIAPI\r
892PciSegmentRead32 (\r
0c3437e0 893 IN UINT64 Address\r
1a3eaf06 894 )\r
895{\r
896 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
897\r
898 return PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r
899}\r
900\r
901/**\r
902 Writes a 32-bit PCI configuration register.\r
903\r
d5979dc0 904 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
905 Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 906\r
1a3eaf06 907 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 908 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 909\r
ebdde8ff 910 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
d5979dc0 911 @param Value The value to write.\r
1a3eaf06 912\r
d5979dc0 913 @return The parameter of Value.\r
1a3eaf06 914\r
915**/\r
916UINT32\r
917EFIAPI\r
918PciSegmentWrite32 (\r
0c3437e0 919 IN UINT64 Address,\r
920 IN UINT32 Value\r
1a3eaf06 921 )\r
922{\r
923 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
924\r
d5979dc0 925 return PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);\r
1a3eaf06 926}\r
927\r
928/**\r
62991af2 929 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r
1a3eaf06 930\r
d5979dc0 931 Reads the 32-bit PCI configuration register specified by Address,\r
62991af2 932 performs a bitwise OR between the read result and the value specified by OrData,\r
d5979dc0 933 and writes the result to the 32-bit PCI configuration register specified by Address.\r
934 The value written to the PCI configuration register is returned.\r
935 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 936\r
1a3eaf06 937 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 938 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 939\r
ebdde8ff 940 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
d5979dc0 941 @param OrData The value to OR with the PCI configuration register.\r
1a3eaf06 942\r
d5979dc0 943 @return The value written to the PCI configuration register.\r
1a3eaf06 944\r
945**/\r
946UINT32\r
947EFIAPI\r
948PciSegmentOr32 (\r
0c3437e0 949 IN UINT64 Address,\r
950 IN UINT32 OrData\r
1a3eaf06 951 )\r
952{\r
953 return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
954}\r
955\r
956/**\r
122e2191 957 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
1a3eaf06 958\r
122e2191 959 Reads the 32-bit PCI configuration register specified by Address,\r
960 performs a bitwise AND between the read result and the value specified by AndData,\r
961 and writes the result to the 32-bit PCI configuration register specified by Address.\r
962 The value written to the PCI configuration register is returned.\r
963 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 964\r
1a3eaf06 965 If any reserved bits in Address are set, then ASSERT().\r
122e2191 966 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 967\r
ebdde8ff 968 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
122e2191 969 @param AndData The value to AND with the PCI configuration register.\r
1a3eaf06 970\r
122e2191 971 @return The value written to the PCI configuration register.\r
1a3eaf06 972\r
973**/\r
974UINT32\r
975EFIAPI\r
976PciSegmentAnd32 (\r
0c3437e0 977 IN UINT64 Address,\r
978 IN UINT32 AndData\r
1a3eaf06 979 )\r
980{\r
981 return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
982}\r
983\r
984/**\r
122e2191 985 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
62991af2 986 followed a bitwise OR with another 32-bit value.\r
ebdde8ff 987\r
122e2191 988 Reads the 32-bit PCI configuration register specified by Address,\r
989 performs a bitwise AND between the read result and the value specified by AndData,\r
62991af2 990 performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
122e2191 991 and writes the result to the 32-bit PCI configuration register specified by Address.\r
992 The value written to the PCI configuration register is returned.\r
993 This function must guarantee that all PCI read and write operations are serialized.\r
ebdde8ff 994\r
1a3eaf06 995 If any reserved bits in Address are set, then ASSERT().\r
122e2191 996 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 997\r
ebdde8ff 998 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
122e2191 999 @param AndData The value to AND with the PCI configuration register.\r
1000 @param OrData The value to OR with the PCI configuration register.\r
1a3eaf06 1001\r
122e2191 1002 @return The value written to the PCI configuration register.\r
1a3eaf06 1003\r
1004**/\r
1005UINT32\r
1006EFIAPI\r
1007PciSegmentAndThenOr32 (\r
0c3437e0 1008 IN UINT64 Address,\r
1009 IN UINT32 AndData,\r
1010 IN UINT32 OrData\r
1a3eaf06 1011 )\r
1012{\r
1013 return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
1014}\r
1015\r
1016/**\r
1017 Reads a bit field of a PCI configuration register.\r
1018\r
1019 Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
1020 specified by the StartBit and the EndBit. The value of the bit field is\r
1021 returned.\r
1022\r
1023 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 1024 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 1025 If StartBit is greater than 31, then ASSERT().\r
1026 If EndBit is greater than 31, then ASSERT().\r
1027 If EndBit is less than StartBit, then ASSERT().\r
1028\r
ebdde8ff 1029 @param Address PCI configuration register to read.\r
1a3eaf06 1030 @param StartBit The ordinal of the least significant bit in the bit field.\r
1031 Range 0..31.\r
1032 @param EndBit The ordinal of the most significant bit in the bit field.\r
1033 Range 0..31.\r
1034\r
1035 @return The value of the bit field read from the PCI configuration register.\r
1036\r
1037**/\r
1038UINT32\r
1039EFIAPI\r
1040PciSegmentBitFieldRead32 (\r
0c3437e0 1041 IN UINT64 Address,\r
1042 IN UINTN StartBit,\r
1043 IN UINTN EndBit\r
1a3eaf06 1044 )\r
1045{\r
1046 return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
1047}\r
1048\r
1049/**\r
1050 Writes a bit field to a PCI configuration register.\r
1051\r
1052 Writes Value to the bit field of the PCI configuration register. The bit\r
1053 field is specified by the StartBit and the EndBit. All other bits in the\r
1054 destination PCI configuration register are preserved. The new value of the\r
1055 32-bit register is returned.\r
1056\r
1057 If any reserved bits in Address are set, then ASSERT().\r
d5979dc0 1058 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 1059 If StartBit is greater than 31, then ASSERT().\r
1060 If EndBit is greater than 31, then ASSERT().\r
1061 If EndBit is less than StartBit, then ASSERT().\r
94952554 1062 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 1063\r
ebdde8ff 1064 @param Address PCI configuration register to write.\r
1a3eaf06 1065 @param StartBit The ordinal of the least significant bit in the bit field.\r
1066 Range 0..31.\r
1067 @param EndBit The ordinal of the most significant bit in the bit field.\r
1068 Range 0..31.\r
ebdde8ff 1069 @param Value New value of the bit field.\r
1a3eaf06 1070\r
1071 @return The value written back to the PCI configuration register.\r
1072\r
1073**/\r
1074UINT32\r
1075EFIAPI\r
1076PciSegmentBitFieldWrite32 (\r
0c3437e0 1077 IN UINT64 Address,\r
1078 IN UINTN StartBit,\r
1079 IN UINTN EndBit,\r
1080 IN UINT32 Value\r
1a3eaf06 1081 )\r
1082{\r
1083 return PciSegmentWrite32 (\r
1084 Address,\r
1085 BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r
1086 );\r
1087}\r
1088\r
1089/**\r
1090 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
1091 writes the result back to the bit field in the 32-bit port.\r
1092\r
1093 Reads the 32-bit PCI configuration register specified by Address, performs a\r
62991af2 1094 bitwise OR between the read result and the value specified by\r
1a3eaf06 1095 OrData, and writes the result to the 32-bit PCI configuration register\r
1096 specified by Address. The value written to the PCI configuration register is\r
1097 returned. This function must guarantee that all PCI read and write operations\r
1098 are serialized. Extra left bits in OrData are stripped.\r
1099\r
1100 If any reserved bits in Address are set, then ASSERT().\r
1101 If StartBit is greater than 31, then ASSERT().\r
1102 If EndBit is greater than 31, then ASSERT().\r
1103 If EndBit is less than StartBit, then ASSERT().\r
94952554 1104 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 1105\r
ebdde8ff 1106 @param Address PCI configuration register to write.\r
1a3eaf06 1107 @param StartBit The ordinal of the least significant bit in the bit field.\r
1108 Range 0..31.\r
1109 @param EndBit The ordinal of the most significant bit in the bit field.\r
1110 Range 0..31.\r
1111 @param OrData The value to OR with the PCI configuration register.\r
1112\r
1113 @return The value written back to the PCI configuration register.\r
1114\r
1115**/\r
1116UINT32\r
1117EFIAPI\r
1118PciSegmentBitFieldOr32 (\r
0c3437e0 1119 IN UINT64 Address,\r
1120 IN UINTN StartBit,\r
1121 IN UINTN EndBit,\r
1122 IN UINT32 OrData\r
1a3eaf06 1123 )\r
1124{\r
1125 return PciSegmentWrite32 (\r
1126 Address,\r
1127 BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r
1128 );\r
1129}\r
1130\r
1131/**\r
1132 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
1133 AND, and writes the result back to the bit field in the 32-bit register.\r
1134\r
ebdde8ff 1135\r
0c3437e0 1136 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
1137 AND between the read result and the value specified by AndData, and writes the result\r
1138 to the 32-bit PCI configuration register specified by Address. The value written to\r
1139 the PCI configuration register is returned. This function must guarantee that all PCI\r
1140 read and write operations are serialized. Extra left bits in AndData are stripped.\r
1a3eaf06 1141 If any reserved bits in Address are set, then ASSERT().\r
0c3437e0 1142 If Address is not aligned on a 32-bit boundary, then ASSERT().\r
1a3eaf06 1143 If StartBit is greater than 31, then ASSERT().\r
1144 If EndBit is greater than 31, then ASSERT().\r
1145 If EndBit is less than StartBit, then ASSERT().\r
94952554 1146 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 1147\r
ebdde8ff 1148 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
1a3eaf06 1149 @param StartBit The ordinal of the least significant bit in the bit field.\r
1150 Range 0..31.\r
1151 @param EndBit The ordinal of the most significant bit in the bit field.\r
1152 Range 0..31.\r
1153 @param AndData The value to AND with the PCI configuration register.\r
1154\r
1155 @return The value written back to the PCI configuration register.\r
1156\r
1157**/\r
1158UINT32\r
1159EFIAPI\r
1160PciSegmentBitFieldAnd32 (\r
0c3437e0 1161 IN UINT64 Address,\r
1162 IN UINTN StartBit,\r
1163 IN UINTN EndBit,\r
1164 IN UINT32 AndData\r
1a3eaf06 1165 )\r
1166{\r
1167 return PciSegmentWrite32 (\r
1168 Address,\r
1169 BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r
1170 );\r
1171}\r
1172\r
1173/**\r
1174 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
62991af2 1175 bitwise OR, and writes the result back to the bit field in the\r
1a3eaf06 1176 32-bit port.\r
1177\r
1178 Reads the 32-bit PCI configuration register specified by Address, performs a\r
62991af2 1179 bitwise AND followed by a bitwise OR between the read result and\r
1a3eaf06 1180 the value specified by AndData, and writes the result to the 32-bit PCI\r
1181 configuration register specified by Address. The value written to the PCI\r
1182 configuration register is returned. This function must guarantee that all PCI\r
1183 read and write operations are serialized. Extra left bits in both AndData and\r
1184 OrData are stripped.\r
1185\r
1186 If any reserved bits in Address are set, then ASSERT().\r
1187 If StartBit is greater than 31, then ASSERT().\r
1188 If EndBit is greater than 31, then ASSERT().\r
1189 If EndBit is less than StartBit, then ASSERT().\r
94952554
LG
1190 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1191 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
1a3eaf06 1192\r
ebdde8ff 1193 @param Address PCI configuration register to write.\r
1a3eaf06 1194 @param StartBit The ordinal of the least significant bit in the bit field.\r
1195 Range 0..31.\r
1196 @param EndBit The ordinal of the most significant bit in the bit field.\r
1197 Range 0..31.\r
1198 @param AndData The value to AND with the PCI configuration register.\r
1199 @param OrData The value to OR with the result of the AND operation.\r
1200\r
1201 @return The value written back to the PCI configuration register.\r
1202\r
1203**/\r
1204UINT32\r
1205EFIAPI\r
1206PciSegmentBitFieldAndThenOr32 (\r
0c3437e0 1207 IN UINT64 Address,\r
1208 IN UINTN StartBit,\r
1209 IN UINTN EndBit,\r
1210 IN UINT32 AndData,\r
1211 IN UINT32 OrData\r
1a3eaf06 1212 )\r
1213{\r
1214 return PciSegmentWrite32 (\r
1215 Address,\r
1216 BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r
1217 );\r
1218}\r
1219\r
1220/**\r
1221 Reads a range of PCI configuration registers into a caller supplied buffer.\r
1222\r
0c3437e0 1223 Reads the range of PCI configuration registers specified by StartAddress and\r
1224 Size into the buffer specified by Buffer. This function only allows the PCI\r
1225 configuration registers from a single PCI function to be read. Size is\r
1226 returned. When possible 32-bit PCI configuration read cycles are used to read\r
1227 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
1228 and 16-bit PCI configuration read cycles may be used at the beginning and the\r
1229 end of the range.\r
1230\r
59ceeabe 1231 If any reserved bits in StartAddress are set, then ASSERT().\r
1a3eaf06 1232 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
1233 If Size > 0 and Buffer is NULL, then ASSERT().\r
1234\r
ebdde8ff
RN
1235 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
1236 Function and Register.\r
1237 @param Size Size in bytes of the transfer.\r
1238 @param Buffer Pointer to a buffer receiving the data read.\r
1a3eaf06 1239\r
0c3437e0 1240 @return Size\r
1a3eaf06 1241\r
1242**/\r
1243UINTN\r
1244EFIAPI\r
1245PciSegmentReadBuffer (\r
0c3437e0 1246 IN UINT64 StartAddress,\r
1247 IN UINTN Size,\r
1248 OUT VOID *Buffer\r
1a3eaf06 1249 )\r
1250{\r
1251 UINTN ReturnValue;\r
1252\r
1253 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
1254 ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
1255\r
1256 if (Size == 0) {\r
1257 return Size;\r
1258 }\r
1259\r
1260 ASSERT (Buffer != NULL);\r
1261\r
1262 //\r
1263 // Save Size for return\r
1264 //\r
1265 ReturnValue = Size;\r
1266\r
e43e4b3e 1267 if ((StartAddress & BIT0) != 0) {\r
1a3eaf06 1268 //\r
1269 // Read a byte if StartAddress is byte aligned\r
1270 //\r
1271 *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
1272 StartAddress += sizeof (UINT8);\r
1273 Size -= sizeof (UINT8);\r
1274 Buffer = (UINT8*)Buffer + 1;\r
1275 }\r
1276\r
e43e4b3e 1277 if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
1a3eaf06 1278 //\r
1279 // Read a word if StartAddress is word aligned\r
1280 //\r
5dc4fd78 1281 WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
1a3eaf06 1282 StartAddress += sizeof (UINT16);\r
1283 Size -= sizeof (UINT16);\r
1284 Buffer = (UINT16*)Buffer + 1;\r
1285 }\r
1286\r
1287 while (Size >= sizeof (UINT32)) {\r
1288 //\r
1289 // Read as many double words as possible\r
1290 //\r
5dc4fd78 1291 WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r
1a3eaf06 1292 StartAddress += sizeof (UINT32);\r
1293 Size -= sizeof (UINT32);\r
1294 Buffer = (UINT32*)Buffer + 1;\r
1295 }\r
1296\r
1297 if (Size >= sizeof (UINT16)) {\r
1298 //\r
1299 // Read the last remaining word if exist\r
1300 //\r
5dc4fd78 1301 WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
1a3eaf06 1302 StartAddress += sizeof (UINT16);\r
1303 Size -= sizeof (UINT16);\r
1304 Buffer = (UINT16*)Buffer + 1;\r
1305 }\r
1306\r
1307 if (Size >= sizeof (UINT8)) {\r
1308 //\r
1309 // Read the last remaining byte if exist\r
1310 //\r
1311 *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
1312 }\r
1313\r
1314 return ReturnValue;\r
1315}\r
1316\r
d5979dc0 1317\r
1a3eaf06 1318/**\r
0c3437e0 1319 Copies the data in a caller supplied buffer to a specified range of PCI\r
1320 configuration space.\r
1321\r
1322 Writes the range of PCI configuration registers specified by StartAddress and\r
1323 Size from the buffer specified by Buffer. This function only allows the PCI\r
1324 configuration registers from a single PCI function to be written. Size is\r
1325 returned. When possible 32-bit PCI configuration write cycles are used to\r
1326 write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
1327 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
1328 and the end of the range.\r
1329\r
59ceeabe 1330 If any reserved bits in StartAddress are set, then ASSERT().\r
1a3eaf06 1331 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
1332 If Size > 0 and Buffer is NULL, then ASSERT().\r
1333\r
ebdde8ff
RN
1334 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
1335 Function and Register.\r
1336 @param Size Size in bytes of the transfer.\r
1337 @param Buffer Pointer to a buffer containing the data to write.\r
1a3eaf06 1338\r
d5979dc0 1339 @return The parameter of Size.\r
1a3eaf06 1340\r
1341**/\r
1342UINTN\r
1343EFIAPI\r
1344PciSegmentWriteBuffer (\r
0c3437e0 1345 IN UINT64 StartAddress,\r
1346 IN UINTN Size,\r
1347 IN VOID *Buffer\r
1a3eaf06 1348 )\r
1349{\r
1350 UINTN ReturnValue;\r
1351\r
1352 ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
1353 ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
1354\r
1355 if (Size == 0) {\r
1356 return 0;\r
1357 }\r
1358\r
1359 ASSERT (Buffer != NULL);\r
1360\r
1361 //\r
1362 // Save Size for return\r
1363 //\r
1364 ReturnValue = Size;\r
1365\r
e43e4b3e 1366 if ((StartAddress & BIT0) != 0) {\r
1a3eaf06 1367 //\r
1368 // Write a byte if StartAddress is byte aligned\r
1369 //\r
1370 PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
1371 StartAddress += sizeof (UINT8);\r
1372 Size -= sizeof (UINT8);\r
1373 Buffer = (UINT8*)Buffer + 1;\r
1374 }\r
1375\r
e43e4b3e 1376 if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
1a3eaf06 1377 //\r
1378 // Write a word if StartAddress is word aligned\r
1379 //\r
5dc4fd78 1380 PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
1a3eaf06 1381 StartAddress += sizeof (UINT16);\r
1382 Size -= sizeof (UINT16);\r
1383 Buffer = (UINT16*)Buffer + 1;\r
1384 }\r
1385\r
1386 while (Size >= sizeof (UINT32)) {\r
1387 //\r
1388 // Write as many double words as possible\r
1389 //\r
5dc4fd78 1390 PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
1a3eaf06 1391 StartAddress += sizeof (UINT32);\r
1392 Size -= sizeof (UINT32);\r
1393 Buffer = (UINT32*)Buffer + 1;\r
1394 }\r
1395\r
1396 if (Size >= sizeof (UINT16)) {\r
1397 //\r
1398 // Write the last remaining word if exist\r
1399 //\r
5dc4fd78 1400 PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
1a3eaf06 1401 StartAddress += sizeof (UINT16);\r
1402 Size -= sizeof (UINT16);\r
1403 Buffer = (UINT16*)Buffer + 1;\r
1404 }\r
1405\r
1406 if (Size >= sizeof (UINT8)) {\r
1407 //\r
1408 // Write the last remaining byte if exist\r
1409 //\r
1410 PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
1411 }\r
1412\r
1413 return ReturnValue;\r
1414}\r