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Adding top-level Conf directory for next generation of EDK II build infrastructure...
[mirror_edk2.git] / OldMdePkg / Include / Ipf / SalApi.h
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878ddf1f 1/** @file\r
2 Main SAL API's defined in SAL 3.0 specification. \r
3\r
4 Copyright (c) 2006, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
13 Module Name: SalApi.h\r
14\r
15**/\r
16\r
17#ifndef __SAL_API_H__\r
18#define __SAL_API_H__\r
19\r
4e3f1861 20//\r
21// FIT Types \r
22// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
23//\r
24#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
25#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
26//\r
27// type from 0x02 to 0x0E is reserved.\r
28//\r
29#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
30//\r
31// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
32//\r
33#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
34#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
878ddf1f 35\r
36//\r
4e3f1861 37// EFI_SAL_STATUS \r
878ddf1f 38//\r
4e3f1861 39typedef UINTN EFI_SAL_STATUS;\r
40\r
878ddf1f 41#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
42#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
43#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
44#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
45#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
46#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
47#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
48#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
49\r
9c89ec98 50//\r
51// Return values from SAL\r
52//\r
53typedef struct {\r
54 EFI_SAL_STATUS Status; // register r8\r
55 UINTN r9;\r
56 UINTN r10;\r
57 UINTN r11;\r
58} SAL_RETURN_REGS;\r
59\r
7ac2bbc1 60//\r
61// Delivery Mode of IPF CPU.\r
62//\r
63typedef enum {\r
64 EFI_DELIVERY_MODE_INT,\r
65 EFI_DELIVERY_MODE_MPreserved1,\r
66 EFI_DELIVERY_MODE_PMI,\r
67 EFI_DELIVERY_MODE_MPreserved2,\r
68 EFI_DELIVERY_MODE_NMI,\r
69 EFI_DELIVERY_MODE_INIT,\r
70 EFI_DELIVERY_MODE_MPreserved3,\r
71 EFI_DELIVERY_MODE_ExtINT\r
72} EFI_DELIVERY_MODE;\r
73\r
878ddf1f 74typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
75 (\r
76 IN UINT64 FunctionId,\r
77 IN UINT64 Arg2,\r
78 IN UINT64 Arg3,\r
79 IN UINT64 Arg4,\r
80 IN UINT64 Arg5,\r
81 IN UINT64 Arg6,\r
82 IN UINT64 Arg7,\r
83 IN UINT64 Arg8\r
84 );\r
85\r
86//\r
87// SAL Procedure FunctionId definition\r
88//\r
89#define EFI_SAL_SET_VECTORS 0x01000000\r
90#define EFI_SAL_GET_STATE_INFO 0x01000001\r
91#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
92#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
93#define EFI_SAL_MC_RENDEZ 0x01000004\r
94#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
95#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
96#define EFI_SAL_CACHE_FLUSH 0x01000008\r
97#define EFI_SAL_CACHE_INIT 0x01000009\r
98#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
99#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
100#define EFI_SAL_FREQ_BASE 0x01000012\r
101#define EFI_SAL_UPDATE_PAL 0x01000020\r
102\r
103#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
104#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
105\r
106//\r
107// SAL Procedure parameter definitions\r
108// Not much point in using typedefs or enums because all params\r
109// are UINT64 and the entry point is common\r
110//\r
111// EFI_SAL_SET_VECTORS\r
112//\r
113#define EFI_SAL_SET_MCA_VECTOR 0x0\r
114#define EFI_SAL_SET_INIT_VECTOR 0x1\r
115#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
116\r
117typedef struct {\r
118 UINT64 Length : 32;\r
119 UINT64 ChecksumValid : 1;\r
120 UINT64 Reserved1 : 7;\r
121 UINT64 ByteChecksum : 8;\r
122 UINT64 Reserved2 : 16;\r
123} SAL_SET_VECTORS_CS_N;\r
124\r
125//\r
126// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
127// EFI_SAL_CLEAR_STATE_INFO\r
128//\r
129#define EFI_SAL_MCA_STATE_INFO 0x0\r
130#define EFI_SAL_INIT_STATE_INFO 0x1\r
131#define EFI_SAL_CMC_STATE_INFO 0x2\r
132#define EFI_SAL_CP_STATE_INFO 0x3\r
133\r
134//\r
135// EFI_SAL_MC_SET_PARAMS\r
136//\r
137#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
138#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
139#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
140\r
141#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
142#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
143\r
144//\r
145// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
146//\r
147#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
148\r
149//\r
150// EFI_SAL_CACHE_FLUSH\r
151//\r
152#define EFI_SAL_FLUSH_I_CACHE 0x01\r
153#define EFI_SAL_FLUSH_D_CACHE 0x02\r
154#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
155#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
156\r
157//\r
158// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
159//\r
160#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
161#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
162#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
163\r
164typedef struct {\r
165 UINT64 Register : 8;\r
166 UINT64 Function : 3;\r
167 UINT64 Device : 5;\r
168 UINT64 Bus : 8;\r
169 UINT64 Segment : 8;\r
170 UINT64 Reserved : 32;\r
171} SAL_PCI_ADDRESS;\r
172\r
173//\r
174// EFI_SAL_FREQ_BASE\r
175//\r
176#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
177#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
178#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
179\r
180//\r
181// EFI_SAL_UPDATE_PAL\r
182//\r
183#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
184#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
185#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
186#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
187#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
188#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
189#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
190#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
191\r
192typedef struct {\r
193 UINT32 Size;\r
194 UINT32 MmddyyyyDate;\r
195 UINT16 Version;\r
196 UINT8 Type;\r
197 UINT8 Reserved[5];\r
198 UINT64 FwVendorId;\r
199} SAL_UPDATE_PAL_DATA_BLOCK;\r
200\r
201typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
202 struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
203 struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
204 UINT8 StoreChecksum;\r
205 UINT8 Reserved[15];\r
206} SAL_UPDATE_PAL_INFO_BLOCK;\r
207\r
208//\r
209// SAL System Table Definitions\r
210//\r
211#pragma pack(1)\r
212typedef struct {\r
213 UINT32 Signature;\r
214 UINT32 Length;\r
215 UINT16 SalRevision;\r
216 UINT16 EntryCount;\r
217 UINT8 CheckSum;\r
218 UINT8 Reserved[7];\r
219 UINT16 SalAVersion;\r
220 UINT16 SalBVersion;\r
221 UINT8 OemId[32];\r
222 UINT8 ProductId[32];\r
223 UINT8 Reserved2[8];\r
224} SAL_SYSTEM_TABLE_HEADER;\r
225#pragma pack()\r
226\r
227#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
228#define EFI_SAL_REVISION 0x0300\r
229//\r
230// SAL System Types\r
231//\r
232#define EFI_SAL_ST_ENTRY_POINT 0\r
233#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
234#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
235#define EFI_SAL_ST_TR_USAGE 3\r
236#define EFI_SAL_ST_PTC 4\r
237#define EFI_SAL_ST_AP_WAKEUP 5\r
238\r
239#pragma pack(1)\r
240typedef struct {\r
241 UINT8 Type; // Type == 0\r
242 UINT8 Reserved[7];\r
243 UINT64 PalProcEntry;\r
244 UINT64 SalProcEntry;\r
245 UINT64 SalGlobalDataPointer;\r
246 UINT64 Reserved2[2];\r
247} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
248\r
249//\r
250// Not needed for Itanium-based OS boot\r
251//\r
252typedef struct {\r
253 UINT8 Type; // Type == 1\r
254 UINT8 NeedVirtualRegistration;\r
255 UINT8 MemoryAttributes;\r
256 UINT8 PageAccessRights;\r
257 UINT8 SupportedAttributes;\r
258 UINT8 Reserved;\r
259 UINT8 MemoryType;\r
260 UINT8 MemoryUsage;\r
261 UINT64 PhysicalMemoryAddress;\r
262 UINT32 Length;\r
263 UINT32 Reserved1;\r
264 UINT64 OemReserved;\r
265} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;\r
266\r
267#pragma pack()\r
268//\r
269// Memory Attributes\r
270//\r
271#define SAL_MDT_ATTRIB_WB 0x00\r
272//\r
273// #define SAL_MDT_ATTRIB_UC 0x02\r
274//\r
275#define SAL_MDT_ATTRIB_UC 0x04\r
276#define SAL_MDT_ATTRIB_UCE 0x05\r
277#define SAL_MDT_ATTRIB_WC 0x06\r
278\r
279//\r
280// Supported memory Attributes\r
281//\r
282#define SAL_MDT_SUPPORT_WB 0x1\r
283#define SAL_MDT_SUPPORT_UC 0x2\r
284#define SAL_MDT_SUPPORT_UCE 0x4\r
285#define SAL_MDT_SUPPORT_WC 0x8\r
286\r
287//\r
288// Virtual address registration\r
289//\r
290#define SAL_MDT_NO_VA 0x00\r
291#define SAL_MDT_NEED_VA 0x01\r
292//\r
293// MemoryType info\r
294//\r
295#define SAL_REGULAR_MEMORY 0x0000\r
296#define SAL_MMIO_MAPPING 0x0001\r
297#define SAL_SAPIC_IPI_BLOCK 0x0002\r
298#define SAL_IO_PORT_MAPPING 0x0003\r
299#define SAL_FIRMWARE_MEMORY 0x0004\r
300#define SAL_BLACK_HOLE 0x000A\r
301//\r
302// Memory Usage info\r
303//\r
304#define SAL_MDT_USAGE_UNSPECIFIED 0x00\r
305#define SAL_PAL_CODE 0x01\r
306#define SAL_BOOTSERVICE_CODE 0x02\r
307#define SAL_BOOTSERVICE_DATA 0x03\r
308#define SAL_RUNTIMESERVICE_CODE 0x04\r
309#define SAL_RUNTIMESERVICE_DATA 0x05\r
310#define SAL_IA32_OPTIONROM 0x06\r
311#define SAL_IA32_SYSTEMROM 0x07\r
312#define SAL_PMI_CODE 0x0a\r
313#define SAL_PMI_DATA 0x0b\r
314\r
315#pragma pack(1)\r
316typedef struct {\r
317 UINT8 Type; // Type == 2\r
318 UINT8 PlatformFeatures;\r
319 UINT8 Reserved[14];\r
320} SAL_ST_PLATFORM_FEATURES;\r
321#pragma pack()\r
322\r
323#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
324#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
325#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
326\r
327#pragma pack(1)\r
328typedef struct {\r
329 UINT8 Type; // Type == 3\r
330 UINT8 TRType;\r
331 UINT8 TRNumber;\r
332 UINT8 Reserved[5];\r
333 UINT64 VirtualAddress;\r
334 UINT64 EncodedPageSize;\r
335 UINT64 Reserved1;\r
336} SAL_ST_TR_DECRIPTOR;\r
337#pragma pack()\r
338\r
339#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
340#define EFI_SAL_ST_TR_USAGE_DATA 01\r
341\r
342#pragma pack(1)\r
343typedef struct {\r
344 UINT64 NumberOfProcessors;\r
345 UINT64 LocalIDRegister;\r
346} SAL_COHERENCE_DOMAIN_INFO;\r
347#pragma pack()\r
348\r
349#pragma pack(1)\r
350typedef struct {\r
351 UINT8 Type; // Type == 4\r
352 UINT8 Reserved[3];\r
353 UINT32 NumberOfDomains;\r
354 SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
355} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
356#pragma pack()\r
357\r
358#pragma pack(1)\r
359typedef struct {\r
360 UINT8 Type; // Type == 5\r
361 UINT8 WakeUpType;\r
362 UINT8 Reserved[6];\r
363 UINT64 ExternalInterruptVector;\r
364} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
365#pragma pack()\r
366//\r
367// FIT Entry\r
368//\r
369#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
370#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
371#define EFI_SAL_FIT_PALB_TYPE 01\r
372\r
373typedef struct {\r
374 UINT64 Address;\r
375 UINT8 Size[3];\r
376 UINT8 Reserved;\r
377 UINT16 Revision;\r
378 UINT8 Type : 7;\r
379 UINT8 CheckSumValid : 1;\r
380 UINT8 CheckSum;\r
381} EFI_SAL_FIT_ENTRY;\r
382\r
383//\r
384// SAL Common Record Header\r
385//\r
386typedef struct {\r
387 UINT16 Length;\r
388 UINT8 Data[1024];\r
389} SAL_OEM_DATA;\r
390\r
391typedef struct {\r
392 UINT8 Seconds;\r
393 UINT8 Minutes;\r
394 UINT8 Hours;\r
395 UINT8 Reserved;\r
396 UINT8 Day;\r
397 UINT8 Month;\r
398 UINT8 Year;\r
399 UINT8 Century;\r
400} SAL_TIME_STAMP;\r
401\r
402typedef struct {\r
403 UINT64 RecordId;\r
404 UINT16 Revision;\r
405 UINT8 ErrorSeverity;\r
406 UINT8 ValidationBits;\r
407 UINT32 RecordLength;\r
408 SAL_TIME_STAMP TimeStamp;\r
409 UINT8 OemPlatformId[16];\r
410} SAL_RECORD_HEADER;\r
411\r
412typedef struct {\r
413 EFI_GUID Guid;\r
414 UINT16 Revision;\r
415 UINT8 ErrorRecoveryInfo;\r
416 UINT8 Reserved;\r
417 UINT32 SectionLength;\r
418} SAL_SEC_HEADER;\r
419\r
420//\r
421// SAL Processor Record\r
422//\r
423#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
424 { \\r
425 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
426 }\r
427\r
428#define CHECK_INFO_VALID_BIT_MASK 0x1\r
429#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
430#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
431#define TARGER_ID_VALID_BIT_MASK 0x8\r
432#define PRECISE_IP_VALID_BIT_MASK 0x10\r
433\r
434typedef struct {\r
435 UINT64 InfoValid : 1;\r
436 UINT64 ReqValid : 1;\r
437 UINT64 RespValid : 1;\r
438 UINT64 TargetValid : 1;\r
439 UINT64 IpValid : 1;\r
440 UINT64 Reserved : 59;\r
441 UINT64 Info;\r
442 UINT64 Req;\r
443 UINT64 Resp;\r
444 UINT64 Target;\r
445 UINT64 Ip;\r
446} MOD_ERROR_INFO;\r
447\r
448typedef struct {\r
449 UINT8 CpuidInfo[40];\r
450 UINT8 Reserved;\r
451} CPUID_INFO;\r
452\r
453typedef struct {\r
454 UINT64 FrLow;\r
455 UINT64 FrHigh;\r
456} FR_STRUCT;\r
457\r
458#define MIN_STATE_VALID_BIT_MASK 0x1\r
459#define BR_VALID_BIT_MASK 0x2\r
460#define CR_VALID_BIT_MASK 0x4\r
461#define AR_VALID_BIT_MASK 0x8\r
462#define RR_VALID_BIT_MASK 0x10\r
463#define FR_VALID_BIT_MASK 0x20\r
464\r
465typedef struct {\r
466 UINT64 ValidFieldBits;\r
467 UINT8 MinStateInfo[1024];\r
468 UINT64 Br[8];\r
469 UINT64 Cr[128];\r
470 UINT64 Ar[128];\r
471 UINT64 Rr[8];\r
472 FR_STRUCT Fr[128];\r
473} PSI_STATIC_STRUCT;\r
474\r
475#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
476#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
477#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
478#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
479#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
480\r
481typedef struct {\r
482 SAL_SEC_HEADER SectionHeader;\r
483 UINT64 ValidationBits;\r
484 UINT64 ProcErrorMap;\r
485 UINT64 ProcStateParameter;\r
486 UINT64 ProcCrLid;\r
487 MOD_ERROR_INFO CacheError[15];\r
488 MOD_ERROR_INFO TlbError[15];\r
489 MOD_ERROR_INFO BusError[15];\r
490 MOD_ERROR_INFO RegFileCheck[15];\r
491 MOD_ERROR_INFO MsCheck[15];\r
492 CPUID_INFO CpuInfo;\r
493 PSI_STATIC_STRUCT PsiValidData;\r
494} SAL_PROCESSOR_ERROR_RECORD;\r
495\r
496//\r
497// Sal Platform memory Error Record\r
498//\r
499#define SAL_MEMORY_ERROR_RECORD_INFO \\r
500 { \\r
501 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
502 }\r
503\r
504#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
505#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
506#define MEMORY_ADDR_BIT_MASK 0x4\r
507#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
508#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
509#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
510#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
511#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
512#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
513#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
514#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
515#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
516#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
517#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
518#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
519#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
520#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
521\r
522typedef struct {\r
523 SAL_SEC_HEADER SectionHeader;\r
524 UINT64 ValidationBits;\r
525 UINT64 MemErrorStatus;\r
526 UINT64 MemPhysicalAddress;\r
527 UINT64 MemPhysicalAddressMask;\r
528 UINT16 MemNode;\r
529 UINT16 MemCard;\r
530 UINT16 MemModule;\r
531 UINT16 MemBank;\r
532 UINT16 MemDevice;\r
533 UINT16 MemRow;\r
534 UINT16 MemColumn;\r
535 UINT16 MemBitPosition;\r
536 UINT64 ModRequestorId;\r
537 UINT64 ModResponderId;\r
538 UINT64 ModTargetId;\r
539 UINT64 BusSpecificData;\r
540 UINT8 MemPlatformOemId[16];\r
541} SAL_MEMORY_ERROR_RECORD;\r
542\r
543//\r
544// PCI BUS Errors\r
545//\r
546#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
547 { \\r
548 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
549 }\r
550\r
551#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
552#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
553#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
554#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
555#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
556#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
557#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
558#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
559#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
560#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
561#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
562\r
563typedef struct {\r
564 UINT8 BusNumber;\r
565 UINT8 SegmentNumber;\r
566} PCI_BUS_ID;\r
567\r
568typedef struct {\r
569 SAL_SEC_HEADER SectionHeader;\r
570 UINT64 ValidationBits;\r
571 UINT64 PciBusErrorStatus;\r
572 UINT16 PciBusErrorType;\r
573 PCI_BUS_ID PciBusId;\r
574 UINT32 Reserved;\r
575 UINT64 PciBusAddress;\r
576 UINT64 PciBusData;\r
577 UINT64 PciBusCommand;\r
578 UINT64 PciBusRequestorId;\r
579 UINT64 PciBusResponderId;\r
580 UINT64 PciBusTargetId;\r
581 UINT8 PciBusOemId[16];\r
582} SAL_PCI_BUS_ERROR_RECORD;\r
583\r
584//\r
585// PCI Component Errors\r
586//\r
587#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
588 { \\r
589 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
590 }\r
591\r
592#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
593#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
594#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
595#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
596#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
597#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
598\r
599typedef struct {\r
600 UINT16 VendorId;\r
601 UINT16 DeviceId;\r
602 UINT8 ClassCode[3];\r
603 UINT8 FunctionNumber;\r
604 UINT8 DeviceNumber;\r
605 UINT8 BusNumber;\r
606 UINT8 SegmentNumber;\r
607 UINT8 Reserved[5];\r
608} PCI_COMP_INFO;\r
609\r
610typedef struct {\r
611 SAL_SEC_HEADER SectionHeader;\r
612 UINT64 ValidationBits;\r
613 UINT64 PciComponentErrorStatus;\r
614 PCI_COMP_INFO PciComponentInfo;\r
615 UINT32 PciComponentMemNum;\r
616 UINT32 PciComponentIoNum;\r
617 UINT8 PciBusOemId[16];\r
618} SAL_PCI_COMPONENT_ERROR_RECORD;\r
619\r
620//\r
621// Sal Device Errors Info.\r
622//\r
623#define SAL_DEVICE_ERROR_RECORD_INFO \\r
624 { \\r
625 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
626 }\r
627\r
628#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
629#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
630#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
631#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
632#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
633#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
634#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
635#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
636#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
637#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
638\r
639typedef struct {\r
640 SAL_SEC_HEADER SectionHeader;\r
641 UINT64 ValidationBits;\r
642 UINT16 SelRecordId;\r
643 UINT8 SelRecordType;\r
644 UINT32 TimeStamp;\r
645 UINT16 GeneratorId;\r
646 UINT8 EvmRevision;\r
647 UINT8 SensorType;\r
648 UINT8 SensorNum;\r
649 UINT8 EventDirType;\r
650 UINT8 Data1;\r
651 UINT8 Data2;\r
652 UINT8 Data3;\r
653} SAL_DEVICE_ERROR_RECORD;\r
654\r
655//\r
656// Sal SMBIOS Device Errors Info.\r
657//\r
658#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
659 { \\r
660 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
661 }\r
662\r
663#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
664#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
665#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
666#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
667\r
668typedef struct {\r
669 SAL_SEC_HEADER SectionHeader;\r
670 UINT64 ValidationBits;\r
671 UINT8 SmbiosEventType;\r
672 UINT8 SmbiosLength;\r
673 UINT8 SmbiosBcdTimeStamp[6];\r
674} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
675\r
676//\r
677// Sal Platform Specific Errors Info.\r
678//\r
679#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
680 { \\r
681 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
682 }\r
683\r
684#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
685#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
686#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
687#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
688#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
689#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
690#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
691#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
692\r
693typedef struct {\r
694 SAL_SEC_HEADER SectionHeader;\r
695 UINT64 ValidationBits;\r
696 UINT64 PlatformErrorStatus;\r
697 UINT64 PlatformRequestorId;\r
698 UINT64 PlatformResponderId;\r
699 UINT64 PlatformTargetId;\r
700 UINT64 PlatformBusSpecificData;\r
701 UINT8 OemComponentId[16];\r
702} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
703\r
704//\r
705// Union of all the possible Sal Record Types\r
706//\r
707typedef union {\r
708 SAL_RECORD_HEADER *RecordHeader;\r
709 SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
710 SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
711 SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
712 SAL_DEVICE_ERROR_RECORD *ImpiRecord;\r
713 SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
714 SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
715 SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
716 UINT8 *Raw;\r
717} SAL_ERROR_RECORDS_POINTERS;\r
718\r
719#pragma pack()\r
720\r
721#endif\r
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