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1 | /** @file\r |
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2 | PCI CF8 Library Services for PCI Segment #0\r |
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3 | \r |
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4 | Copyright (c) 2006, Intel Corporation\r |
| 5 | All rights reserved. This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
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9 | \r |
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10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
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12 | \r |
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13 | Module Name: PciCf8Lib.h\r |
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14 | \r |
| 15 | **/\r |
| 16 | \r |
| 17 | #ifndef __PCI_CF8_LIB_H__\r |
| 18 | #define __PCI_CF8_LIB_H__\r |
| 19 | \r |
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20 | \r |
| 21 | /**\r |
| 22 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r |
| 23 | address that can be passed to the PCI Library functions.\r |
| 24 | \r |
| 25 | Computes an address that is compatible with the PCI Library functions. The\r |
| 26 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r |
| 27 | the generation of the address.\r |
| 28 | \r |
| 29 | @param Bus PCI Bus number. Range 0..255.\r |
| 30 | @param Device PCI Device number. Range 0..31.\r |
| 31 | @param Function PCI Function number. Range 0..7.\r |
| 32 | @param Register PCI Register number. Range 0..255.\r |
| 33 | \r |
| 34 | @return The encode PCI address.\r |
| 35 | \r |
| 36 | **/\r |
| 37 | #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r |
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38 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r |
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39 | \r |
| 40 | /**\r |
| 41 | Reads an 8-bit PCI configuration register.\r |
| 42 | \r |
| 43 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 44 | This function must guarantee that all PCI read and write operations are\r |
| 45 | serialized.\r |
| 46 | \r |
| 47 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 48 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 49 | \r |
| 50 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 51 | Register.\r |
| 52 | \r |
| 53 | @return The read value from the PCI configuration register.\r |
| 54 | \r |
| 55 | **/\r |
| 56 | UINT8\r |
| 57 | EFIAPI\r |
| 58 | PciCf8Read8 (\r |
| 59 | IN UINTN Address\r |
| 60 | );\r |
| 61 | \r |
| 62 | /**\r |
| 63 | Writes an 8-bit PCI configuration register.\r |
| 64 | \r |
| 65 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 66 | value specified by Value. Value is returned. This function must guarantee\r |
| 67 | that all PCI read and write operations are serialized.\r |
| 68 | \r |
| 69 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 70 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 71 | \r |
| 72 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 73 | Register.\r |
| 74 | @param Value The value to write.\r |
| 75 | \r |
| 76 | @return The value written to the PCI configuration register.\r |
| 77 | \r |
| 78 | **/\r |
| 79 | UINT8\r |
| 80 | EFIAPI\r |
| 81 | PciCf8Write8 (\r |
| 82 | IN UINTN Address,\r |
| 83 | IN UINT8 Data\r |
| 84 | );\r |
| 85 | \r |
| 86 | /**\r |
| 87 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 88 | an 8-bit value.\r |
| 89 | \r |
| 90 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 91 | bitwise inclusive OR between the read result and the value specified by\r |
| 92 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 93 | specified by Address. The value written to the PCI configuration register is\r |
| 94 | returned. This function must guarantee that all PCI read and write operations\r |
| 95 | are serialized.\r |
| 96 | \r |
| 97 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 98 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 99 | \r |
| 100 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 101 | Register.\r |
| 102 | @param OrData The value to OR with the PCI configuration register.\r |
| 103 | \r |
| 104 | @return The value written back to the PCI configuration register.\r |
| 105 | \r |
| 106 | **/\r |
| 107 | UINT8\r |
| 108 | EFIAPI\r |
| 109 | PciCf8Or8 (\r |
| 110 | IN UINTN Address,\r |
| 111 | IN UINT8 OrData\r |
| 112 | );\r |
| 113 | \r |
| 114 | /**\r |
| 115 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 116 | value.\r |
| 117 | \r |
| 118 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 119 | bitwise AND between the read result and the value specified by AndData, and\r |
| 120 | writes the result to the 8-bit PCI configuration register specified by\r |
| 121 | Address. The value written to the PCI configuration register is returned.\r |
| 122 | This function must guarantee that all PCI read and write operations are\r |
| 123 | serialized.\r |
| 124 | \r |
| 125 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 126 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 127 | \r |
| 128 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 129 | Register.\r |
| 130 | @param AndData The value to AND with the PCI configuration register.\r |
| 131 | \r |
| 132 | @return The value written back to the PCI configuration register.\r |
| 133 | \r |
| 134 | **/\r |
| 135 | UINT8\r |
| 136 | EFIAPI\r |
| 137 | PciCf8And8 (\r |
| 138 | IN UINTN Address,\r |
| 139 | IN UINT8 AndData\r |
| 140 | );\r |
| 141 | \r |
| 142 | /**\r |
| 143 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 144 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 145 | \r |
| 146 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 147 | bitwise AND between the read result and the value specified by AndData,\r |
| 148 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 149 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 150 | configuration register specified by Address. The value written to the PCI\r |
| 151 | configuration register is returned. This function must guarantee that all PCI\r |
| 152 | read and write operations are serialized.\r |
| 153 | \r |
| 154 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 155 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 156 | \r |
| 157 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 158 | Register.\r |
| 159 | @param AndData The value to AND with the PCI configuration register.\r |
| 160 | @param OrData The value to OR with the result of the AND operation.\r |
| 161 | \r |
| 162 | @return The value written back to the PCI configuration register.\r |
| 163 | \r |
| 164 | **/\r |
| 165 | UINT8\r |
| 166 | EFIAPI\r |
| 167 | PciCf8AndThenOr8 (\r |
| 168 | IN UINTN Address,\r |
| 169 | IN UINT8 AndData,\r |
| 170 | IN UINT8 OrData\r |
| 171 | );\r |
| 172 | \r |
| 173 | /**\r |
| 174 | Reads a bit field of a PCI configuration register.\r |
| 175 | \r |
| 176 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 177 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 178 | returned.\r |
| 179 | \r |
| 180 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 181 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 182 | If StartBit is greater than 7, then ASSERT().\r |
| 183 | If EndBit is greater than 7, then ASSERT().\r |
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184 | If EndBit is less than StartBit, then ASSERT().\r |
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185 | \r |
| 186 | @param Address PCI configuration register to read.\r |
| 187 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 188 | Range 0..7.\r |
| 189 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 190 | Range 0..7.\r |
| 191 | \r |
| 192 | @return The value of the bit field read from the PCI configuration register.\r |
| 193 | \r |
| 194 | **/\r |
| 195 | UINT8\r |
| 196 | EFIAPI\r |
| 197 | PciCf8BitFieldRead8 (\r |
| 198 | IN UINTN Address,\r |
| 199 | IN UINTN StartBit,\r |
| 200 | IN UINTN EndBit\r |
| 201 | );\r |
| 202 | \r |
| 203 | /**\r |
| 204 | Writes a bit field to a PCI configuration register.\r |
| 205 | \r |
| 206 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 207 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 208 | destination PCI configuration register are preserved. The new value of the\r |
| 209 | 8-bit register is returned.\r |
| 210 | \r |
| 211 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 212 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 213 | If StartBit is greater than 7, then ASSERT().\r |
| 214 | If EndBit is greater than 7, then ASSERT().\r |
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215 | If EndBit is less than StartBit, then ASSERT().\r |
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216 | \r |
| 217 | @param Address PCI configuration register to write.\r |
| 218 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 219 | Range 0..7.\r |
| 220 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 221 | Range 0..7.\r |
| 222 | @param Value New value of the bit field.\r |
| 223 | \r |
| 224 | @return The value written back to the PCI configuration register.\r |
| 225 | \r |
| 226 | **/\r |
| 227 | UINT8\r |
| 228 | EFIAPI\r |
| 229 | PciCf8BitFieldWrite8 (\r |
| 230 | IN UINTN Address,\r |
| 231 | IN UINTN StartBit,\r |
| 232 | IN UINTN EndBit,\r |
| 233 | IN UINT8 Value\r |
| 234 | );\r |
| 235 | \r |
| 236 | /**\r |
| 237 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 238 | writes the result back to the bit field in the 8-bit port.\r |
| 239 | \r |
| 240 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 241 | bitwise inclusive OR between the read result and the value specified by\r |
| 242 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 243 | specified by Address. The value written to the PCI configuration register is\r |
| 244 | returned. This function must guarantee that all PCI read and write operations\r |
| 245 | are serialized. Extra left bits in OrData are stripped.\r |
| 246 | \r |
| 247 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 248 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 249 | If StartBit is greater than 7, then ASSERT().\r |
| 250 | If EndBit is greater than 7, then ASSERT().\r |
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251 | If EndBit is less than StartBit, then ASSERT().\r |
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252 | \r |
| 253 | @param Address PCI configuration register to write.\r |
| 254 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 255 | Range 0..7.\r |
| 256 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 257 | Range 0..7.\r |
| 258 | @param OrData The value to OR with the PCI configuration register.\r |
| 259 | \r |
| 260 | @return The value written back to the PCI configuration register.\r |
| 261 | \r |
| 262 | **/\r |
| 263 | UINT8\r |
| 264 | EFIAPI\r |
| 265 | PciCf8BitFieldOr8 (\r |
| 266 | IN UINTN Address,\r |
| 267 | IN UINTN StartBit,\r |
| 268 | IN UINTN EndBit,\r |
| 269 | IN UINT8 OrData\r |
| 270 | );\r |
| 271 | \r |
| 272 | /**\r |
| 273 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 274 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 275 | \r |
| 276 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 277 | bitwise AND between the read result and the value specified by AndData, and\r |
| 278 | writes the result to the 8-bit PCI configuration register specified by\r |
| 279 | Address. The value written to the PCI configuration register is returned.\r |
| 280 | This function must guarantee that all PCI read and write operations are\r |
| 281 | serialized. Extra left bits in AndData are stripped.\r |
| 282 | \r |
| 283 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 284 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 285 | If StartBit is greater than 7, then ASSERT().\r |
| 286 | If EndBit is greater than 7, then ASSERT().\r |
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287 | If EndBit is less than StartBit, then ASSERT().\r |
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288 | \r |
| 289 | @param Address PCI configuration register to write.\r |
| 290 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 291 | Range 0..7.\r |
| 292 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 293 | Range 0..7.\r |
| 294 | @param AndData The value to AND with the PCI configuration register.\r |
| 295 | \r |
| 296 | @return The value written back to the PCI configuration register.\r |
| 297 | \r |
| 298 | **/\r |
| 299 | UINT8\r |
| 300 | EFIAPI\r |
| 301 | PciCf8BitFieldAnd8 (\r |
| 302 | IN UINTN Address,\r |
| 303 | IN UINTN StartBit,\r |
| 304 | IN UINTN EndBit,\r |
| 305 | IN UINT8 AndData\r |
| 306 | );\r |
| 307 | \r |
| 308 | /**\r |
| 309 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 310 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 311 | 8-bit port.\r |
| 312 | \r |
| 313 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 314 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 315 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 316 | configuration register specified by Address. The value written to the PCI\r |
| 317 | configuration register is returned. This function must guarantee that all PCI\r |
| 318 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 319 | OrData are stripped.\r |
| 320 | \r |
| 321 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 322 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 323 | If StartBit is greater than 7, then ASSERT().\r |
| 324 | If EndBit is greater than 7, then ASSERT().\r |
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325 | If EndBit is less than StartBit, then ASSERT().\r |
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326 | \r |
| 327 | @param Address PCI configuration register to write.\r |
| 328 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 329 | Range 0..7.\r |
| 330 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 331 | Range 0..7.\r |
| 332 | @param AndData The value to AND with the PCI configuration register.\r |
| 333 | @param OrData The value to OR with the result of the AND operation.\r |
| 334 | \r |
| 335 | @return The value written back to the PCI configuration register.\r |
| 336 | \r |
| 337 | **/\r |
| 338 | UINT8\r |
| 339 | EFIAPI\r |
| 340 | PciCf8BitFieldAndThenOr8 (\r |
| 341 | IN UINTN Address,\r |
| 342 | IN UINTN StartBit,\r |
| 343 | IN UINTN EndBit,\r |
| 344 | IN UINT8 AndData,\r |
| 345 | IN UINT8 OrData\r |
| 346 | );\r |
| 347 | \r |
| 348 | /**\r |
| 349 | Reads a 16-bit PCI configuration register.\r |
| 350 | \r |
| 351 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 352 | This function must guarantee that all PCI read and write operations are\r |
| 353 | serialized.\r |
| 354 | \r |
| 355 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 356 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 357 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 358 | \r |
| 359 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 360 | Register.\r |
| 361 | \r |
| 362 | @return The read value from the PCI configuration register.\r |
| 363 | \r |
| 364 | **/\r |
| 365 | UINT16\r |
| 366 | EFIAPI\r |
| 367 | PciCf8Read16 (\r |
| 368 | IN UINTN Address\r |
| 369 | );\r |
| 370 | \r |
| 371 | /**\r |
| 372 | Writes a 16-bit PCI configuration register.\r |
| 373 | \r |
| 374 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 375 | value specified by Value. Value is returned. This function must guarantee\r |
| 376 | that all PCI read and write operations are serialized.\r |
| 377 | \r |
| 378 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 379 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 380 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 381 | \r |
| 382 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 383 | Register.\r |
| 384 | @param Value The value to write.\r |
| 385 | \r |
| 386 | @return The value written to the PCI configuration register.\r |
| 387 | \r |
| 388 | **/\r |
| 389 | UINT16\r |
| 390 | EFIAPI\r |
| 391 | PciCf8Write16 (\r |
| 392 | IN UINTN Address,\r |
| 393 | IN UINT16 Data\r |
| 394 | );\r |
| 395 | \r |
| 396 | /**\r |
| 397 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 398 | a 16-bit value.\r |
| 399 | \r |
| 400 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 401 | bitwise inclusive OR between the read result and the value specified by\r |
| 402 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 403 | specified by Address. The value written to the PCI configuration register is\r |
| 404 | returned. This function must guarantee that all PCI read and write operations\r |
| 405 | are serialized.\r |
| 406 | \r |
| 407 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 408 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 409 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 410 | \r |
| 411 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 412 | Register.\r |
| 413 | @param OrData The value to OR with the PCI configuration register.\r |
| 414 | \r |
| 415 | @return The value written back to the PCI configuration register.\r |
| 416 | \r |
| 417 | **/\r |
| 418 | UINT16\r |
| 419 | EFIAPI\r |
| 420 | PciCf8Or16 (\r |
| 421 | IN UINTN Address,\r |
| 422 | IN UINT16 OrData\r |
| 423 | );\r |
| 424 | \r |
| 425 | /**\r |
| 426 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 427 | value.\r |
| 428 | \r |
| 429 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 430 | bitwise AND between the read result and the value specified by AndData, and\r |
| 431 | writes the result to the 16-bit PCI configuration register specified by\r |
| 432 | Address. The value written to the PCI configuration register is returned.\r |
| 433 | This function must guarantee that all PCI read and write operations are\r |
| 434 | serialized.\r |
| 435 | \r |
| 436 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 437 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 438 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 439 | \r |
| 440 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 441 | Register.\r |
| 442 | @param AndData The value to AND with the PCI configuration register.\r |
| 443 | \r |
| 444 | @return The value written back to the PCI configuration register.\r |
| 445 | \r |
| 446 | **/\r |
| 447 | UINT16\r |
| 448 | EFIAPI\r |
| 449 | PciCf8And16 (\r |
| 450 | IN UINTN Address,\r |
| 451 | IN UINT16 AndData\r |
| 452 | );\r |
| 453 | \r |
| 454 | /**\r |
| 455 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 456 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 457 | \r |
| 458 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 459 | bitwise AND between the read result and the value specified by AndData,\r |
| 460 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 461 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 462 | configuration register specified by Address. The value written to the PCI\r |
| 463 | configuration register is returned. This function must guarantee that all PCI\r |
| 464 | read and write operations are serialized.\r |
| 465 | \r |
| 466 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 467 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 468 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 469 | \r |
| 470 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 471 | Register.\r |
| 472 | @param AndData The value to AND with the PCI configuration register.\r |
| 473 | @param OrData The value to OR with the result of the AND operation.\r |
| 474 | \r |
| 475 | @return The value written back to the PCI configuration register.\r |
| 476 | \r |
| 477 | **/\r |
| 478 | UINT16\r |
| 479 | EFIAPI\r |
| 480 | PciCf8AndThenOr16 (\r |
| 481 | IN UINTN Address,\r |
| 482 | IN UINT16 AndData,\r |
| 483 | IN UINT16 OrData\r |
| 484 | );\r |
| 485 | \r |
| 486 | /**\r |
| 487 | Reads a bit field of a PCI configuration register.\r |
| 488 | \r |
| 489 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 490 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 491 | returned.\r |
| 492 | \r |
| 493 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 494 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 495 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 496 | If StartBit is greater than 15, then ASSERT().\r |
| 497 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
498 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
499 | \r |
| 500 | @param Address PCI configuration register to read.\r |
| 501 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 502 | Range 0..15.\r |
| 503 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 504 | Range 0..15.\r |
| 505 | \r |
| 506 | @return The value of the bit field read from the PCI configuration register.\r |
| 507 | \r |
| 508 | **/\r |
| 509 | UINT16\r |
| 510 | EFIAPI\r |
| 511 | PciCf8BitFieldRead16 (\r |
| 512 | IN UINTN Address,\r |
| 513 | IN UINTN StartBit,\r |
| 514 | IN UINTN EndBit\r |
| 515 | );\r |
| 516 | \r |
| 517 | /**\r |
| 518 | Writes a bit field to a PCI configuration register.\r |
| 519 | \r |
| 520 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 521 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 522 | destination PCI configuration register are preserved. The new value of the\r |
| 523 | 16-bit register is returned.\r |
| 524 | \r |
| 525 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 526 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 527 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 528 | If StartBit is greater than 15, then ASSERT().\r |
| 529 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
530 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
531 | \r |
| 532 | @param Address PCI configuration register to write.\r |
| 533 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 534 | Range 0..15.\r |
| 535 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 536 | Range 0..15.\r |
| 537 | @param Value New value of the bit field.\r |
| 538 | \r |
| 539 | @return The value written back to the PCI configuration register.\r |
| 540 | \r |
| 541 | **/\r |
| 542 | UINT16\r |
| 543 | EFIAPI\r |
| 544 | PciCf8BitFieldWrite16 (\r |
| 545 | IN UINTN Address,\r |
| 546 | IN UINTN StartBit,\r |
| 547 | IN UINTN EndBit,\r |
| 548 | IN UINT16 Value\r |
| 549 | );\r |
| 550 | \r |
| 551 | /**\r |
| 552 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 553 | writes the result back to the bit field in the 16-bit port.\r |
| 554 | \r |
| 555 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 556 | bitwise inclusive OR between the read result and the value specified by\r |
| 557 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 558 | specified by Address. The value written to the PCI configuration register is\r |
| 559 | returned. This function must guarantee that all PCI read and write operations\r |
| 560 | are serialized. Extra left bits in OrData are stripped.\r |
| 561 | \r |
| 562 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 563 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 564 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 565 | If StartBit is greater than 15, then ASSERT().\r |
| 566 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
567 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
568 | \r |
| 569 | @param Address PCI configuration register to write.\r |
| 570 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 571 | Range 0..15.\r |
| 572 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 573 | Range 0..15.\r |
| 574 | @param OrData The value to OR with the PCI configuration register.\r |
| 575 | \r |
| 576 | @return The value written back to the PCI configuration register.\r |
| 577 | \r |
| 578 | **/\r |
| 579 | UINT16\r |
| 580 | EFIAPI\r |
| 581 | PciCf8BitFieldOr16 (\r |
| 582 | IN UINTN Address,\r |
| 583 | IN UINTN StartBit,\r |
| 584 | IN UINTN EndBit,\r |
| 585 | IN UINT16 OrData\r |
| 586 | );\r |
| 587 | \r |
| 588 | /**\r |
| 589 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 590 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 591 | \r |
| 592 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 593 | bitwise AND between the read result and the value specified by AndData, and\r |
| 594 | writes the result to the 16-bit PCI configuration register specified by\r |
| 595 | Address. The value written to the PCI configuration register is returned.\r |
| 596 | This function must guarantee that all PCI read and write operations are\r |
| 597 | serialized. Extra left bits in AndData are stripped.\r |
| 598 | \r |
| 599 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 600 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 601 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 602 | If StartBit is greater than 15, then ASSERT().\r |
| 603 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
604 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
605 | \r |
| 606 | @param Address PCI configuration register to write.\r |
| 607 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 608 | Range 0..15.\r |
| 609 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 610 | Range 0..15.\r |
| 611 | @param AndData The value to AND with the PCI configuration register.\r |
| 612 | \r |
| 613 | @return The value written back to the PCI configuration register.\r |
| 614 | \r |
| 615 | **/\r |
| 616 | UINT16\r |
| 617 | EFIAPI\r |
| 618 | PciCf8BitFieldAnd16 (\r |
| 619 | IN UINTN Address,\r |
| 620 | IN UINTN StartBit,\r |
| 621 | IN UINTN EndBit,\r |
| 622 | IN UINT16 AndData\r |
| 623 | );\r |
| 624 | \r |
| 625 | /**\r |
| 626 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 627 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 628 | 16-bit port.\r |
| 629 | \r |
| 630 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 631 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 632 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 633 | configuration register specified by Address. The value written to the PCI\r |
| 634 | configuration register is returned. This function must guarantee that all PCI\r |
| 635 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 636 | OrData are stripped.\r |
| 637 | \r |
| 638 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 639 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 640 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 641 | If StartBit is greater than 15, then ASSERT().\r |
| 642 | If EndBit is greater than 15, then ASSERT().\r |
| 0ffa1286 |
643 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
644 | \r |
| 645 | @param Address PCI configuration register to write.\r |
| 646 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 647 | Range 0..15.\r |
| 648 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 649 | Range 0..15.\r |
| 650 | @param AndData The value to AND with the PCI configuration register.\r |
| 651 | @param OrData The value to OR with the result of the AND operation.\r |
| 652 | \r |
| 653 | @return The value written back to the PCI configuration register.\r |
| 654 | \r |
| 655 | **/\r |
| 656 | UINT16\r |
| 657 | EFIAPI\r |
| 658 | PciCf8BitFieldAndThenOr16 (\r |
| 659 | IN UINTN Address,\r |
| 660 | IN UINTN StartBit,\r |
| 661 | IN UINTN EndBit,\r |
| 662 | IN UINT16 AndData,\r |
| 663 | IN UINT16 OrData\r |
| 664 | );\r |
| 665 | \r |
| 666 | /**\r |
| 667 | Reads a 32-bit PCI configuration register.\r |
| 668 | \r |
| 669 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 670 | This function must guarantee that all PCI read and write operations are\r |
| 671 | serialized.\r |
| 672 | \r |
| 673 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 674 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 675 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 676 | \r |
| 677 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 678 | Register.\r |
| 679 | \r |
| 680 | @return The read value from the PCI configuration register.\r |
| 681 | \r |
| 682 | **/\r |
| 683 | UINT32\r |
| 684 | EFIAPI\r |
| 685 | PciCf8Read32 (\r |
| 686 | IN UINTN Address\r |
| 687 | );\r |
| 688 | \r |
| 689 | /**\r |
| 690 | Writes a 32-bit PCI configuration register.\r |
| 691 | \r |
| 692 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 693 | value specified by Value. Value is returned. This function must guarantee\r |
| 694 | that all PCI read and write operations are serialized.\r |
| 695 | \r |
| 696 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 697 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 698 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 699 | \r |
| 700 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 701 | Register.\r |
| 702 | @param Value The value to write.\r |
| 703 | \r |
| 704 | @return The value written to the PCI configuration register.\r |
| 705 | \r |
| 706 | **/\r |
| 707 | UINT32\r |
| 708 | EFIAPI\r |
| 709 | PciCf8Write32 (\r |
| 710 | IN UINTN Address,\r |
| 711 | IN UINT32 Data\r |
| 712 | );\r |
| 713 | \r |
| 714 | /**\r |
| 715 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 716 | a 32-bit value.\r |
| 717 | \r |
| 718 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 719 | bitwise inclusive OR between the read result and the value specified by\r |
| 720 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 721 | specified by Address. The value written to the PCI configuration register is\r |
| 722 | returned. This function must guarantee that all PCI read and write operations\r |
| 723 | are serialized.\r |
| 724 | \r |
| 725 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 726 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 727 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 728 | \r |
| 729 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 730 | Register.\r |
| 731 | @param OrData The value to OR with the PCI configuration register.\r |
| 732 | \r |
| 733 | @return The value written back to the PCI configuration register.\r |
| 734 | \r |
| 735 | **/\r |
| 736 | UINT32\r |
| 737 | EFIAPI\r |
| 738 | PciCf8Or32 (\r |
| 739 | IN UINTN Address,\r |
| 740 | IN UINT32 OrData\r |
| 741 | );\r |
| 742 | \r |
| 743 | /**\r |
| 744 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 745 | value.\r |
| 746 | \r |
| 747 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 748 | bitwise AND between the read result and the value specified by AndData, and\r |
| 749 | writes the result to the 32-bit PCI configuration register specified by\r |
| 750 | Address. The value written to the PCI configuration register is returned.\r |
| 751 | This function must guarantee that all PCI read and write operations are\r |
| 752 | serialized.\r |
| 753 | \r |
| 754 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 755 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 756 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 757 | \r |
| 758 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 759 | Register.\r |
| 760 | @param AndData The value to AND with the PCI configuration register.\r |
| 761 | \r |
| 762 | @return The value written back to the PCI configuration register.\r |
| 763 | \r |
| 764 | **/\r |
| 765 | UINT32\r |
| 766 | EFIAPI\r |
| 767 | PciCf8And32 (\r |
| 768 | IN UINTN Address,\r |
| 769 | IN UINT32 AndData\r |
| 770 | );\r |
| 771 | \r |
| 772 | /**\r |
| 773 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 774 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 775 | \r |
| 776 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 777 | bitwise AND between the read result and the value specified by AndData,\r |
| 778 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 779 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 780 | configuration register specified by Address. The value written to the PCI\r |
| 781 | configuration register is returned. This function must guarantee that all PCI\r |
| 782 | read and write operations are serialized.\r |
| 783 | \r |
| 784 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 785 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 786 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 787 | \r |
| 788 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 789 | Register.\r |
| 790 | @param AndData The value to AND with the PCI configuration register.\r |
| 791 | @param OrData The value to OR with the result of the AND operation.\r |
| 792 | \r |
| 793 | @return The value written back to the PCI configuration register.\r |
| 794 | \r |
| 795 | **/\r |
| 796 | UINT32\r |
| 797 | EFIAPI\r |
| 798 | PciCf8AndThenOr32 (\r |
| 799 | IN UINTN Address,\r |
| 800 | IN UINT32 AndData,\r |
| 801 | IN UINT32 OrData\r |
| 802 | );\r |
| 803 | \r |
| 804 | /**\r |
| 805 | Reads a bit field of a PCI configuration register.\r |
| 806 | \r |
| 807 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 808 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 809 | returned.\r |
| 810 | \r |
| 811 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 812 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 813 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 814 | If StartBit is greater than 31, then ASSERT().\r |
| 815 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
816 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
817 | \r |
| 818 | @param Address PCI configuration register to read.\r |
| 819 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 820 | Range 0..31.\r |
| 821 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 822 | Range 0..31.\r |
| 823 | \r |
| 824 | @return The value of the bit field read from the PCI configuration register.\r |
| 825 | \r |
| 826 | **/\r |
| 827 | UINT32\r |
| 828 | EFIAPI\r |
| 829 | PciCf8BitFieldRead32 (\r |
| 830 | IN UINTN Address,\r |
| 831 | IN UINTN StartBit,\r |
| 832 | IN UINTN EndBit\r |
| 833 | );\r |
| 834 | \r |
| 835 | /**\r |
| 836 | Writes a bit field to a PCI configuration register.\r |
| 837 | \r |
| 838 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 839 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 840 | destination PCI configuration register are preserved. The new value of the\r |
| 841 | 32-bit register is returned.\r |
| 842 | \r |
| 843 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 844 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 845 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 846 | If StartBit is greater than 31, then ASSERT().\r |
| 847 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
848 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
849 | \r |
| 850 | @param Address PCI configuration register to write.\r |
| 851 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 852 | Range 0..31.\r |
| 853 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 854 | Range 0..31.\r |
| 855 | @param Value New value of the bit field.\r |
| 856 | \r |
| 857 | @return The value written back to the PCI configuration register.\r |
| 858 | \r |
| 859 | **/\r |
| 860 | UINT32\r |
| 861 | EFIAPI\r |
| 862 | PciCf8BitFieldWrite32 (\r |
| 863 | IN UINTN Address,\r |
| 864 | IN UINTN StartBit,\r |
| 865 | IN UINTN EndBit,\r |
| 866 | IN UINT32 Value\r |
| 867 | );\r |
| 868 | \r |
| 869 | /**\r |
| 870 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 871 | writes the result back to the bit field in the 32-bit port.\r |
| 872 | \r |
| 873 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 874 | bitwise inclusive OR between the read result and the value specified by\r |
| 875 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 876 | specified by Address. The value written to the PCI configuration register is\r |
| 877 | returned. This function must guarantee that all PCI read and write operations\r |
| 878 | are serialized. Extra left bits in OrData are stripped.\r |
| 879 | \r |
| 880 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 881 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 882 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 883 | If StartBit is greater than 31, then ASSERT().\r |
| 884 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
885 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
886 | \r |
| 887 | @param Address PCI configuration register to write.\r |
| 888 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 889 | Range 0..31.\r |
| 890 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 891 | Range 0..31.\r |
| 892 | @param OrData The value to OR with the PCI configuration register.\r |
| 893 | \r |
| 894 | @return The value written back to the PCI configuration register.\r |
| 895 | \r |
| 896 | **/\r |
| 897 | UINT32\r |
| 898 | EFIAPI\r |
| 899 | PciCf8BitFieldOr32 (\r |
| 900 | IN UINTN Address,\r |
| 901 | IN UINTN StartBit,\r |
| 902 | IN UINTN EndBit,\r |
| 903 | IN UINT32 OrData\r |
| 904 | );\r |
| 905 | \r |
| 906 | /**\r |
| 907 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 908 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 909 | \r |
| 910 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 911 | bitwise AND between the read result and the value specified by AndData, and\r |
| 912 | writes the result to the 32-bit PCI configuration register specified by\r |
| 913 | Address. The value written to the PCI configuration register is returned.\r |
| 914 | This function must guarantee that all PCI read and write operations are\r |
| 915 | serialized. Extra left bits in AndData are stripped.\r |
| 916 | \r |
| 917 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 918 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 919 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 920 | If StartBit is greater than 31, then ASSERT().\r |
| 921 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
922 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
923 | \r |
| 924 | @param Address PCI configuration register to write.\r |
| 925 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 926 | Range 0..31.\r |
| 927 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 928 | Range 0..31.\r |
| 929 | @param AndData The value to AND with the PCI configuration register.\r |
| 930 | \r |
| 931 | @return The value written back to the PCI configuration register.\r |
| 932 | \r |
| 933 | **/\r |
| 934 | UINT32\r |
| 935 | EFIAPI\r |
| 936 | PciCf8BitFieldAnd32 (\r |
| 937 | IN UINTN Address,\r |
| 938 | IN UINTN StartBit,\r |
| 939 | IN UINTN EndBit,\r |
| 940 | IN UINT32 AndData\r |
| 941 | );\r |
| 942 | \r |
| 943 | /**\r |
| 944 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 945 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 946 | 32-bit port.\r |
| 947 | \r |
| 948 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 949 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 950 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 951 | configuration register specified by Address. The value written to the PCI\r |
| 952 | configuration register is returned. This function must guarantee that all PCI\r |
| 953 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 954 | OrData are stripped.\r |
| 955 | \r |
| 956 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 957 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 958 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 959 | If StartBit is greater than 31, then ASSERT().\r |
| 960 | If EndBit is greater than 31, then ASSERT().\r |
| 0ffa1286 |
961 | If EndBit is less than StartBit, then ASSERT().\r |
| 878ddf1f |
962 | \r |
| 963 | @param Address PCI configuration register to write.\r |
| 964 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 965 | Range 0..31.\r |
| 966 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 967 | Range 0..31.\r |
| 968 | @param AndData The value to AND with the PCI configuration register.\r |
| 969 | @param OrData The value to OR with the result of the AND operation.\r |
| 970 | \r |
| 971 | @return The value written back to the PCI configuration register.\r |
| 972 | \r |
| 973 | **/\r |
| 974 | UINT32\r |
| 975 | EFIAPI\r |
| 976 | PciCf8BitFieldAndThenOr32 (\r |
| 977 | IN UINTN Address,\r |
| 978 | IN UINTN StartBit,\r |
| 979 | IN UINTN EndBit,\r |
| 980 | IN UINT32 AndData,\r |
| 981 | IN UINT32 OrData\r |
| 982 | );\r |
| 983 | \r |
| 984 | /**\r |
| 985 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 986 | \r |
| 987 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 988 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 989 | configuration registers from a single PCI function to be read. Size is\r |
| 990 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 991 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 992 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 993 | end of the range.\r |
| 994 | \r |
| 995 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 996 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 997 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| add13dc2 |
998 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 878ddf1f |
999 | \r |
| 1000 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1001 | Function and Register.\r |
| 1002 | @param Size Size in bytes of the transfer.\r |
| 1003 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1004 | \r |
| 1005 | @return Size\r |
| 1006 | \r |
| 1007 | **/\r |
| 1008 | UINTN\r |
| 1009 | EFIAPI\r |
| 1010 | PciCf8ReadBuffer (\r |
| 1011 | IN UINTN StartAddress,\r |
| 1012 | IN UINTN Size,\r |
| 1013 | OUT VOID *Buffer\r |
| 1014 | );\r |
| 1015 | \r |
| 1016 | /**\r |
| 1017 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1018 | configuration space.\r |
| 1019 | \r |
| 1020 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1021 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1022 | configuration registers from a single PCI function to be written. Size is\r |
| 1023 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1024 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1025 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1026 | and the end of the range.\r |
| 1027 | \r |
| 1028 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1029 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 1030 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| add13dc2 |
1031 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 878ddf1f |
1032 | \r |
| 1033 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1034 | Function and Register.\r |
| 1035 | @param Size Size in bytes of the transfer.\r |
| 1036 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1037 | \r |
| 1038 | @return Size\r |
| 1039 | \r |
| 1040 | **/\r |
| 1041 | UINTN\r |
| 1042 | EFIAPI\r |
| 1043 | PciCf8WriteBuffer (\r |
| 1044 | IN UINTN StartAddress,\r |
| 1045 | IN UINTN Size,\r |
| 1046 | IN VOID *Buffer\r |
| 1047 | );\r |
| 1048 | \r |
| 1049 | #endif\r |
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