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1 | /** @file\r |
2 | \r |
3 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r |
4 | \r |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r |
8 | http://opensource.org/licenses/bsd-license.php\r |
9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
12 | \r |
13 | **/\r |
14 | \r |
15 | #ifndef __OMAP3530DMA_H__\r |
16 | #define __OMAP3530DMA_H__\r |
17 | \r |
18 | \r |
19 | #define DMA4_MAX_CHANNEL 31\r |
20 | \r |
21 | #define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i)))\r |
22 | \r |
23 | #define DMA4_CCR(_i) (0x48056080 + (0x60*(_i)))\r |
24 | #define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))\r |
25 | #define DMA4_CSR(_i) (0x4805608c + (0x60*(_i)))\r |
26 | #define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))\r |
27 | #define DMA4_CEN(_i) (0x48056094 + (0x60*(_i)))\r |
28 | #define DMA4_CFN(_i) (0x48056098 + (0x60*(_i)))\r |
29 | #define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i)))\r |
30 | #define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i)))\r |
31 | #define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i)))\r |
32 | #define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i)))\r |
33 | #define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i)))\r |
34 | #define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i)))\r |
35 | \r |
36 | #define DMA4_GCR (0x48056078)\r |
37 | \r |
38 | // Channel Source Destination parameters\r |
39 | #define DMA4_CSDP_DATA_TYPE8 0\r |
40 | #define DMA4_CSDP_DATA_TYPE16 1\r |
41 | #define DMA4_CSDP_DATA_TYPE32 2\r |
42 | \r |
43 | #define DMA4_CSDP_SRC_PACKED BIT6\r |
44 | #define DMA4_CSDP_SRC_NONPACKED 0\r |
45 | \r |
46 | #define DMA4_CSDP_SRC_BURST_EN (0x0 << 7)\r |
47 | #define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7)\r |
48 | #define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7)\r |
49 | #define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7)\r |
50 | \r |
51 | #define DMA4_CSDP_DST_PACKED BIT13\r |
52 | #define DMA4_CSDP_DST_NONPACKED 0\r |
53 | \r |
54 | #define DMA4_CSDP_BURST_EN (0x0 << 14)\r |
55 | #define DMA4_CSDP_BURST_EN16 (0x1 << 14)\r |
56 | #define DMA4_CSDP_BURST_EN32 (0x2 << 14)\r |
57 | #define DMA4_CSDP_BURST_EN64 (0x3 << 14)\r |
58 | \r |
3402aac7 |
59 | #define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16)\r |
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60 | #define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16)\r |
3402aac7 |
61 | #define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16)\r |
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62 | \r |
63 | #define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18\r |
64 | #define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0\r |
65 | \r |
66 | #define DMA4_CSDP_DST_ENDIAN_BIG BIT19\r |
67 | #define DMA4_CSDP_DST_ENDIAN_LITTLE 0\r |
68 | \r |
69 | #define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20\r |
70 | #define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0\r |
71 | \r |
72 | #define DMA4_CSDP_SRC_ENDIAN_BIG BIT21\r |
73 | #define DMA4_CSDP_SRC_ENDIAN_LITTLE 0\r |
74 | \r |
3402aac7 |
75 | // Channel Control\r |
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76 | #define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f\r |
77 | \r |
78 | #define DMA4_CCR_FS_ELEMENT (0 | 0)\r |
79 | #define DMA4_CCR_FS_BLOCK (0 | BIT18)\r |
80 | #define DMA4_CCR_FS_FRAME (BIT5 | 0)\r |
81 | #define DMA4_CCR_FS_PACKET (BIT5 | BIT18)\r |
82 | \r |
83 | #define DMA4_CCR_READ_PRIORITY_HIGH BIT6\r |
84 | #define DMA4_CCR_READ_PRIORITY_LOW 0\r |
85 | \r |
86 | #define DMA4_CCR_ENABLE BIT7\r |
87 | #define DMA4_CCR_DISABLE 0\r |
88 | \r |
89 | #define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8\r |
90 | #define DMA4_CCR_SUSPEND_SENSITIVE 0\r |
91 | \r |
92 | #define DMA4_CCR_RD_ACTIVE BIT9\r |
93 | #define DMA4_CCR_WR_ACTIVE BIT10\r |
94 | \r |
95 | #define DMA4_CCR_SRC_AMODE (0 | 0)\r |
96 | #define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12)\r |
97 | #define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0)\r |
98 | #define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12)\r |
99 | \r |
100 | #define DMA4_CCR_DST_AMODE (0 | 0)\r |
101 | #define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)\r |
102 | #define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)\r |
103 | #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)\r |
104 | \r |
105 | #define DMA4_CCR_CONST_FILL_ENABLE BIT16\r |
106 | #define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17\r |
3402aac7 |
107 | \r |
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108 | #define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24\r |
109 | \r |
110 | #define DMA4_CSR_DROP BIT1\r |
111 | #define DMA4_CSR_HALF BIT2\r |
112 | #define DMA4_CSR_FRAME BIT3\r |
113 | #define DMA4_CSR_LAST BIT4\r |
114 | #define DMA4_CSR_BLOCK BIT5\r |
115 | #define DMA4_CSR_SYNC BIT6\r |
116 | #define DMA4_CSR_PKT BIT7\r |
117 | #define DMA4_CSR_TRANS_ERR BIT8\r |
118 | #define DMA4_CSR_SECURE_ERR BIT9\r |
119 | #define DMA4_CSR_SUPERVISOR_ERR BIT10\r |
120 | #define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11\r |
121 | #define DMA4_CSR_DRAIN_END BIT12\r |
122 | #define DMA4_CSR_RESET 0x1FE\r |
123 | #define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR)\r |
124 | \r |
125 | // same mapping as CSR except for SYNC. Enable all since we are polling\r |
126 | #define DMA4_CICR_ENABLE_ALL 0x1FBE\r |
127 | \r |
128 | \r |
3402aac7 |
129 | #endif\r |
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130 | \r |