| 1e57a462 |
1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r |
| 4 | \r |
| 538311f7 |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 1e57a462 |
6 | \r |
| 7 | **/\r |
| 8 | \r |
| 9 | #ifndef __OMAP3530DMA_H__\r |
| 10 | #define __OMAP3530DMA_H__\r |
| 11 | \r |
| 12 | \r |
| 13 | #define DMA4_MAX_CHANNEL 31\r |
| 14 | \r |
| 15 | #define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i)))\r |
| 16 | \r |
| 17 | #define DMA4_CCR(_i) (0x48056080 + (0x60*(_i)))\r |
| 18 | #define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))\r |
| 19 | #define DMA4_CSR(_i) (0x4805608c + (0x60*(_i)))\r |
| 20 | #define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))\r |
| 21 | #define DMA4_CEN(_i) (0x48056094 + (0x60*(_i)))\r |
| 22 | #define DMA4_CFN(_i) (0x48056098 + (0x60*(_i)))\r |
| 23 | #define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i)))\r |
| 24 | #define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i)))\r |
| 25 | #define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i)))\r |
| 26 | #define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i)))\r |
| 27 | #define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i)))\r |
| 28 | #define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i)))\r |
| 29 | \r |
| 30 | #define DMA4_GCR (0x48056078)\r |
| 31 | \r |
| 32 | // Channel Source Destination parameters\r |
| 33 | #define DMA4_CSDP_DATA_TYPE8 0\r |
| 34 | #define DMA4_CSDP_DATA_TYPE16 1\r |
| 35 | #define DMA4_CSDP_DATA_TYPE32 2\r |
| 36 | \r |
| 37 | #define DMA4_CSDP_SRC_PACKED BIT6\r |
| 38 | #define DMA4_CSDP_SRC_NONPACKED 0\r |
| 39 | \r |
| 40 | #define DMA4_CSDP_SRC_BURST_EN (0x0 << 7)\r |
| 41 | #define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7)\r |
| 42 | #define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7)\r |
| 43 | #define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7)\r |
| 44 | \r |
| 45 | #define DMA4_CSDP_DST_PACKED BIT13\r |
| 46 | #define DMA4_CSDP_DST_NONPACKED 0\r |
| 47 | \r |
| 48 | #define DMA4_CSDP_BURST_EN (0x0 << 14)\r |
| 49 | #define DMA4_CSDP_BURST_EN16 (0x1 << 14)\r |
| 50 | #define DMA4_CSDP_BURST_EN32 (0x2 << 14)\r |
| 51 | #define DMA4_CSDP_BURST_EN64 (0x3 << 14)\r |
| 52 | \r |
| 3402aac7 |
53 | #define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16)\r |
| 1e57a462 |
54 | #define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16)\r |
| 3402aac7 |
55 | #define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16)\r |
| 1e57a462 |
56 | \r |
| 57 | #define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18\r |
| 58 | #define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0\r |
| 59 | \r |
| 60 | #define DMA4_CSDP_DST_ENDIAN_BIG BIT19\r |
| 61 | #define DMA4_CSDP_DST_ENDIAN_LITTLE 0\r |
| 62 | \r |
| 63 | #define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20\r |
| 64 | #define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0\r |
| 65 | \r |
| 66 | #define DMA4_CSDP_SRC_ENDIAN_BIG BIT21\r |
| 67 | #define DMA4_CSDP_SRC_ENDIAN_LITTLE 0\r |
| 68 | \r |
| 3402aac7 |
69 | // Channel Control\r |
| 1e57a462 |
70 | #define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f\r |
| 71 | \r |
| 72 | #define DMA4_CCR_FS_ELEMENT (0 | 0)\r |
| 73 | #define DMA4_CCR_FS_BLOCK (0 | BIT18)\r |
| 74 | #define DMA4_CCR_FS_FRAME (BIT5 | 0)\r |
| 75 | #define DMA4_CCR_FS_PACKET (BIT5 | BIT18)\r |
| 76 | \r |
| 77 | #define DMA4_CCR_READ_PRIORITY_HIGH BIT6\r |
| 78 | #define DMA4_CCR_READ_PRIORITY_LOW 0\r |
| 79 | \r |
| 80 | #define DMA4_CCR_ENABLE BIT7\r |
| 81 | #define DMA4_CCR_DISABLE 0\r |
| 82 | \r |
| 83 | #define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8\r |
| 84 | #define DMA4_CCR_SUSPEND_SENSITIVE 0\r |
| 85 | \r |
| 86 | #define DMA4_CCR_RD_ACTIVE BIT9\r |
| 87 | #define DMA4_CCR_WR_ACTIVE BIT10\r |
| 88 | \r |
| 89 | #define DMA4_CCR_SRC_AMODE (0 | 0)\r |
| 90 | #define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12)\r |
| 91 | #define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0)\r |
| 92 | #define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12)\r |
| 93 | \r |
| 94 | #define DMA4_CCR_DST_AMODE (0 | 0)\r |
| 95 | #define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)\r |
| 96 | #define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)\r |
| 97 | #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)\r |
| 98 | \r |
| 99 | #define DMA4_CCR_CONST_FILL_ENABLE BIT16\r |
| 100 | #define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17\r |
| 3402aac7 |
101 | \r |
| 1e57a462 |
102 | #define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24\r |
| 103 | \r |
| 104 | #define DMA4_CSR_DROP BIT1\r |
| 105 | #define DMA4_CSR_HALF BIT2\r |
| 106 | #define DMA4_CSR_FRAME BIT3\r |
| 107 | #define DMA4_CSR_LAST BIT4\r |
| 108 | #define DMA4_CSR_BLOCK BIT5\r |
| 109 | #define DMA4_CSR_SYNC BIT6\r |
| 110 | #define DMA4_CSR_PKT BIT7\r |
| 111 | #define DMA4_CSR_TRANS_ERR BIT8\r |
| 112 | #define DMA4_CSR_SECURE_ERR BIT9\r |
| 113 | #define DMA4_CSR_SUPERVISOR_ERR BIT10\r |
| 114 | #define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11\r |
| 115 | #define DMA4_CSR_DRAIN_END BIT12\r |
| 116 | #define DMA4_CSR_RESET 0x1FE\r |
| 117 | #define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR)\r |
| 118 | \r |
| 119 | // same mapping as CSR except for SYNC. Enable all since we are polling\r |
| 120 | #define DMA4_CICR_ENABLE_ALL 0x1FBE\r |
| 121 | \r |
| 122 | \r |
| 3402aac7 |
123 | #endif\r |
| 1e57a462 |
124 | \r |
projects / mirror_edk2.git / blame