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1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | \r |
| 538311f7 |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 1e57a462 |
6 | \r |
| 7 | **/\r |
| 8 | \r |
| 9 | #ifndef __OMAP3530GPIO_H__\r |
| 10 | #define __OMAP3530GPIO_H__\r |
| 11 | \r |
| 12 | #define GPIO1_BASE (0x48310000)\r |
| 13 | #define GPIO2_BASE (0x49050000)\r |
| 14 | #define GPIO3_BASE (0x49052000)\r |
| 15 | #define GPIO4_BASE (0x49054000)\r |
| 16 | #define GPIO5_BASE (0x49056000)\r |
| 17 | #define GPIO6_BASE (0x49058000)\r |
| 18 | \r |
| 19 | #define GPIO_SYSCONFIG (0x0010)\r |
| 20 | #define GPIO_SYSSTATUS (0x0014)\r |
| 21 | #define GPIO_IRQSTATUS1 (0x0018)\r |
| 22 | #define GPIO_IRQENABLE1 (0x001C)\r |
| 23 | #define GPIO_WAKEUPENABLE (0x0020)\r |
| 24 | #define GPIO_IRQSTATUS2 (0x0028)\r |
| 25 | #define GPIO_IRQENABLE2 (0x002C)\r |
| 26 | #define GPIO_CTRL (0x0030)\r |
| 27 | #define GPIO_OE (0x0034)\r |
| 28 | #define GPIO_DATAIN (0x0038)\r |
| 29 | #define GPIO_DATAOUT (0x003C)\r |
| 30 | #define GPIO_LEVELDETECT0 (0x0040)\r |
| 31 | #define GPIO_LEVELDETECT1 (0x0044)\r |
| 32 | #define GPIO_RISINGDETECT (0x0048)\r |
| 33 | #define GPIO_FALLINGDETECT (0x004C)\r |
| 34 | #define GPIO_DEBOUNCENABLE (0x0050)\r |
| 35 | #define GPIO_DEBOUNCINGTIME (0x0054)\r |
| 36 | #define GPIO_CLEARIRQENABLE1 (0x0060)\r |
| 37 | #define GPIO_SETIRQENABLE1 (0x0064)\r |
| 38 | #define GPIO_CLEARIRQENABLE2 (0x0070)\r |
| 39 | #define GPIO_SETIRQENABLE2 (0x0074)\r |
| 40 | #define GPIO_CLEARWKUENA (0x0080)\r |
| 41 | #define GPIO_SETWKUENA (0x0084)\r |
| 42 | #define GPIO_CLEARDATAOUT (0x0090)\r |
| 43 | #define GPIO_SETDATAOUT (0x0094)\r |
| 44 | \r |
| 45 | #define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)\r |
| 46 | #define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)\r |
| 47 | #define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3\r |
| 48 | #define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)\r |
| 49 | #define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2\r |
| 50 | #define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)\r |
| 51 | #define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2\r |
| 52 | #define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1\r |
| 53 | #define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)\r |
| 54 | #define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1\r |
| 55 | #define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0\r |
| 56 | #define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)\r |
| 57 | #define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0\r |
| 58 | \r |
| 59 | #define GPIO_SYSSTATUS_RESETDONE_MASK BIT0\r |
| 60 | #define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)\r |
| 61 | #define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0\r |
| 62 | \r |
| 63 | #define GPIO_IRQSTATUS_MASK(x) (1UL << (x))\r |
| 64 | #define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))\r |
| 65 | #define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))\r |
| 66 | #define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))\r |
| 67 | \r |
| 68 | #define GPIO_IRQENABLE_MASK(x) (1UL << (x))\r |
| 69 | #define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))\r |
| 70 | #define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))\r |
| 71 | \r |
| 72 | #define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))\r |
| 73 | #define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))\r |
| 74 | #define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))\r |
| 75 | \r |
| 76 | #define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)\r |
| 77 | #define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)\r |
| 78 | #define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1\r |
| 79 | #define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)\r |
| 80 | #define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)\r |
| 81 | #define GPIO_CTRL_DISABLEMODULE_MASK BIT0\r |
| 82 | #define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)\r |
| 83 | #define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0\r |
| 84 | \r |
| 85 | #define GPIO_OE_MASK(x) (1UL << (x))\r |
| 86 | #define GPIO_OE_OUTPUT(x) (0UL << (x))\r |
| 87 | #define GPIO_OE_INPUT(x) (1UL << (x))\r |
| 88 | \r |
| 89 | #define GPIO_DATAIN_MASK(x) (1UL << (x))\r |
| 90 | \r |
| 91 | #define GPIO_DATAOUT_MASK(x) (1UL << (x))\r |
| 92 | \r |
| 93 | #define GPIO_LEVELDETECT_MASK(x) (1UL << (x))\r |
| 94 | #define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))\r |
| 95 | #define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))\r |
| 96 | \r |
| 97 | #define GPIO_RISINGDETECT_MASK(x) (1UL << (x))\r |
| 98 | #define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))\r |
| 99 | #define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))\r |
| 100 | \r |
| 101 | #define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))\r |
| 102 | #define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))\r |
| 103 | #define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))\r |
| 104 | \r |
| 105 | #define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))\r |
| 106 | #define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))\r |
| 107 | #define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))\r |
| 108 | \r |
| 109 | #define GPIO_DEBOUNCINGTIME_MASK (0xFF)\r |
| 110 | #define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)\r |
| 111 | \r |
| 112 | #define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))\r |
| 113 | \r |
| 114 | #define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))\r |
| 115 | \r |
| 116 | #define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))\r |
| 117 | \r |
| 118 | #define GPIO_SETWKUENA_BIT(x) (1UL << (x))\r |
| 119 | \r |
| 120 | #define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))\r |
| 121 | \r |
| 122 | #define GPIO_SETDATAOUT_BIT(x) (1UL << (x))\r |
| 123 | \r |
| 124 | #endif // __OMAP3530GPIO_H__\r |
| 125 | \r |
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