projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1e57a462 | 1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
| 209b8f3c | 4 | Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>\r |
| 1e57a462 | 5 | \r |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef __OMAP3530INTERRUPT_H__\r | |
| 17 | #define __OMAP3530INTERRUPT_H__\r | |
| 18 | \r | |
| 209b8f3c LL |
19 | #include <Library/PcdLib.h>\r |
| 20 | \r | |
| 21 | #define INTERRUPT_BASE (PcdGet32 (PcdInterruptBaseAddress))\r | |
| 1e57a462 | 22 | \r |
| 23 | #define INT_NROF_VECTORS (96)\r | |
| 24 | #define MAX_VECTOR (INT_NROF_VECTORS - 1)\r | |
| 25 | #define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)\r | |
| 26 | #define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)\r | |
| 27 | #define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)\r | |
| 28 | #define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)\r | |
| 29 | #define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)\r | |
| 30 | #define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)\r | |
| 31 | #define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)\r | |
| 32 | #define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)\r | |
| 33 | #define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)\r | |
| 34 | #define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)\r | |
| 35 | #define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))\r | |
| 36 | #define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))\r | |
| 37 | #define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))\r | |
| 38 | #define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))\r | |
| 39 | #define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))\r | |
| 40 | #define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))\r | |
| 41 | #define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))\r | |
| 42 | #define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))\r | |
| 43 | #define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))\r | |
| 44 | \r | |
| 45 | #define INTCPS_ILR_FIQ BIT0\r | |
| 46 | #define INTCPS_SIR_IRQ_MASK (0x7F)\r | |
| 47 | #define INTCPS_CONTROL_NEWIRQAGR BIT0\r | |
| 48 | #define INTCPS_CONTROL_NEWFIQAGR BIT1\r | |
| 49 | \r | |
| 50 | #endif // __OMAP3530INTERRUPT_H__\r | |
| 51 | \r |