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a3f98646 | 1 | /** @file |
2 | ||
3 | Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR> | |
4 | ||
5 | All rights reserved. This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #ifndef __OMAP3530INTERRUPT_H__ | |
16 | #define __OMAP3530INTERRUPT_H__ | |
17 | ||
18 | #define INTERRUPT_BASE (0x48200000) | |
19 | ||
20 | #define INT_NROF_VECTORS (96) | |
21 | #define MAX_VECTOR (INT_NROF_VECTORS - 1) | |
22 | #define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010) | |
23 | #define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014) | |
24 | #define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040) | |
25 | #define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044) | |
26 | #define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048) | |
27 | #define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C) | |
28 | #define INTCPS_IDLE (INTERRUPT_BASE + 0x0050) | |
29 | #define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060) | |
30 | #define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064) | |
31 | #define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068) | |
32 | #define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n))) | |
33 | #define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n))) | |
34 | #define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n))) | |
35 | #define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n))) | |
36 | #define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n))) | |
37 | #define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n))) | |
38 | #define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n))) | |
39 | #define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n))) | |
40 | #define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m))) | |
41 | ||
e9fc14b6 | 42 | #define INTCPS_ILR_FIQ BIT0 |
a3f98646 | 43 | #define INTCPS_SIR_IRQ_MASK (0x7F) |
43263288 | 44 | #define INTCPS_CONTROL_NEWIRQAGR BIT0 |
45 | #define INTCPS_CONTROL_NEWFIQAGR BIT1 | |
a3f98646 | 46 | |
47 | #endif // __OMAP3530INTERRUPT_H__ | |
48 |