[mirror_edk2.git] / Omap35xxPkg / Include / Omap3530 / Omap3530MMCHS.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __OMAP3530SDIO_H__\r
#define __OMAP3530SDIO_H__\r
\r
//MMC/SD/SDIO1 register definitions.\r
#define MMCHS1BASE        0x4809C000\r
#define MMC_REFERENCE_CLK (96000000)\r
\r
#define MMCHS_SYSCONFIG   (MMCHS1BASE + 0x10)\r
#define SOFTRESET         BIT1\r
#define ENAWAKEUP         BIT2\r
\r
#define MMCHS_SYSSTATUS   (MMCHS1BASE + 0x14)\r
#define RESETDONE_MASK    BIT0\r
#define RESETDONE         BIT0\r
\r
#define MMCHS_CSRE        (MMCHS1BASE + 0x24)\r
#define MMCHS_SYSTEST     (MMCHS1BASE + 0x28)\r
\r
#define MMCHS_CON         (MMCHS1BASE + 0x2C)\r
#define OD                BIT0\r
#define NOINIT            (0x0UL << 1)\r
#define INIT              BIT1\r
#define HR                BIT2\r
#define STR               BIT3\r
#define MODE              BIT4\r
#define DW8_1_4_BIT       (0x0UL << 5)\r
#define DW8_8_BIT         BIT5\r
#define MIT               BIT6\r
#define CDP               BIT7\r
#define WPP               BIT8\r
#define CTPL              BIT11\r
#define CEATA_OFF         (0x0UL << 12)\r
#define CEATA_ON          BIT12\r
\r
#define MMCHS_PWCNT       (MMCHS1BASE + 0x30)\r
\r
#define MMCHS_BLK         (MMCHS1BASE + 0x104)\r
#define BLEN_512BYTES     (0x200UL << 0)\r
\r
#define MMCHS_ARG         (MMCHS1BASE + 0x108)\r
\r
#define MMCHS_CMD         (MMCHS1BASE + 0x10C)\r
#define DE_ENABLE         BIT0\r
#define BCE_ENABLE        BIT1\r
#define ACEN_ENABLE       BIT2\r
#define DDIR_READ         BIT4\r
#define DDIR_WRITE        (0x0UL << 4)\r
#define MSBS_SGLEBLK      (0x0UL << 5)\r
#define MSBS_MULTBLK      BIT5\r
#define RSP_TYPE_MASK     (0x3UL << 16)\r
#define RSP_TYPE_136BITS  BIT16\r
#define RSP_TYPE_48BITS   (0x2UL << 16)\r
#define CCCE_ENABLE       BIT19\r
#define CICE_ENABLE       BIT20\r
#define DP_ENABLE         BIT21\r
#define INDX(CMD_INDX)    ((CMD_INDX & 0x3F) << 24)\r
\r
#define MMCHS_RSP10       (MMCHS1BASE + 0x110)\r
#define MMCHS_RSP32       (MMCHS1BASE + 0x114)\r
#define MMCHS_RSP54       (MMCHS1BASE + 0x118)\r
#define MMCHS_RSP76       (MMCHS1BASE + 0x11C)\r
#define MMCHS_DATA        (MMCHS1BASE + 0x120)\r
\r
#define MMCHS_PSTATE      (MMCHS1BASE + 0x124)\r
#define CMDI_MASK         BIT0\r
#define CMDI_ALLOWED      (0x0UL << 0)\r
#define CMDI_NOT_ALLOWED  BIT0\r
#define DATI_MASK         BIT1\r
#define DATI_ALLOWED      (0x0UL << 1)\r
#define DATI_NOT_ALLOWED  BIT1\r
\r
#define MMCHS_HCTL        (MMCHS1BASE + 0x128)\r
#define DTW_1_BIT         (0x0UL << 1)\r
#define DTW_4_BIT         BIT1\r
#define SDBP_MASK         BIT8\r
#define SDBP_OFF          (0x0UL << 8)\r
#define SDBP_ON           BIT8\r
#define SDVS_1_8_V        (0x5UL << 9)\r
#define SDVS_3_0_V        (0x6UL << 9)\r
#define IWE               BIT24\r
\r
#define MMCHS_SYSCTL      (MMCHS1BASE + 0x12C)\r
#define ICE               BIT0\r
#define ICS_MASK          BIT1\r
#define ICS               BIT1\r
#define CEN               BIT2\r
#define CLKD_MASK         (0x3FFUL << 6)\r
#define CLKD_80KHZ        (0x258UL) //(96*1000/80)/2\r
#define CLKD_400KHZ       (0xF0UL)\r
#define DTO_MASK          (0xFUL << 16)\r
#define DTO_VAL           (0xEUL << 16)\r
#define SRA               BIT24\r
#define SRC_MASK          BIT25\r
#define SRC               BIT25\r
#define SRD               BIT26\r
\r
#define MMCHS_STAT        (MMCHS1BASE + 0x130)\r
#define CC                BIT0\r
#define TC                BIT1\r
#define BWR               BIT4\r
#define BRR               BIT5\r
#define ERRI              BIT15\r
#define CTO               BIT16\r
#define DTO               BIT20\r
#define DCRC              BIT21\r
#define DEB               BIT22\r
\r
#define MMCHS_IE          (MMCHS1BASE + 0x134)\r
#define CC_EN             BIT0\r
#define TC_EN             BIT1\r
#define BWR_EN            BIT4\r
#define BRR_EN            BIT5\r
#define CTO_EN            BIT16\r
#define CCRC_EN           BIT17\r
#define CEB_EN            BIT18\r
#define CIE_EN            BIT19\r
#define DTO_EN            BIT20\r
#define DCRC_EN           BIT21\r
#define DEB_EN            BIT22\r
#define CERR_EN           BIT28\r
#define BADA_EN           BIT29\r
\r
#define MMCHS_ISE         (MMCHS1BASE + 0x138)\r
#define CC_SIGEN          BIT0\r
#define TC_SIGEN          BIT1\r
#define BWR_SIGEN         BIT4\r
#define BRR_SIGEN         BIT5\r
#define CTO_SIGEN         BIT16\r
#define CCRC_SIGEN        BIT17\r
#define CEB_SIGEN         BIT18\r
#define CIE_SIGEN         BIT19\r
#define DTO_SIGEN         BIT20\r
#define DCRC_SIGEN        BIT21\r
#define DEB_SIGEN         BIT22\r
#define CERR_SIGEN        BIT28\r
#define BADA_SIGEN        BIT29\r
\r
#define MMCHS_AC12        (MMCHS1BASE + 0x13C)\r
\r
#define MMCHS_CAPA        (MMCHS1BASE + 0x140)\r
#define VS30              BIT25\r
#define VS18              BIT26\r
\r
#define MMCHS_CUR_CAPA    (MMCHS1BASE + 0x148)\r
#define MMCHS_REV         (MMCHS1BASE + 0x1FC)\r
\r
#define CMD0              INDX(0)\r
#define CMD0_INT_EN       (CC_EN | CEB_EN)\r
\r
#define CMD1              (INDX(1) | RSP_TYPE_48BITS)\r
#define CMD1_INT_EN       (CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD2              (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)\r
#define CMD2_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD3              (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)\r
#define CMD3_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD5              (INDX(5) | RSP_TYPE_48BITS)\r
#define CMD5_INT_EN       (CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD7              (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)\r
#define CMD7_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD8              (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)\r
#define CMD8_INT_EN       (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE\r
#define CMD8_ARG          (0x0UL << 12 | BIT8 | 0xCEUL << 0)\r
\r
#define CMD9              (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)\r
#define CMD9_INT_EN       (CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD16             (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)\r
#define CMD16_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD17             (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)\r
#define CMD17_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)\r
\r
#define CMD18             (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)\r
#define CMD18_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)\r
\r
#define CMD23             (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)\r
#define CMD23_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define CMD24             (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)\r
#define CMD24_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)\r
\r
#define CMD25             (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)\r
#define CMD25_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)\r
\r
#define CMD55             (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)\r
#define CMD55_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define ACMD41            (INDX(41) | RSP_TYPE_48BITS)\r
#define ACMD41_INT_EN     (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#define ACMD6             (INDX(6) | RSP_TYPE_48BITS)\r
#define ACMD6_INT_EN      (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)\r
\r
#endif //__OMAP3530SDIO_H__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
	4	\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __OMAP3530SDIO_H__\r
	16	#define __OMAP3530SDIO_H__\r
	17	\r
	18	//MMC/SD/SDIO1 register definitions.\r
	19	#define MMCHS1BASE 0x4809C000\r
	20	#define MMC_REFERENCE_CLK (96000000)\r
	21	\r
	22	#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)\r
	23	#define SOFTRESET BIT1\r
	24	#define ENAWAKEUP BIT2\r
	25	\r
	26	#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)\r
	27	#define RESETDONE_MASK BIT0\r
	28	#define RESETDONE BIT0\r
	29	\r
	30	#define MMCHS_CSRE (MMCHS1BASE + 0x24)\r
	31	#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)\r
	32	\r
	33	#define MMCHS_CON (MMCHS1BASE + 0x2C)\r
	34	#define OD BIT0\r
	35	#define NOINIT (0x0UL << 1)\r
	36	#define INIT BIT1\r
	37	#define HR BIT2\r
	38	#define STR BIT3\r
	39	#define MODE BIT4\r
	40	#define DW8_1_4_BIT (0x0UL << 5)\r
	41	#define DW8_8_BIT BIT5\r
	42	#define MIT BIT6\r
	43	#define CDP BIT7\r
	44	#define WPP BIT8\r
	45	#define CTPL BIT11\r
	46	#define CEATA_OFF (0x0UL << 12)\r
	47	#define CEATA_ON BIT12\r
	48	\r
	49	#define MMCHS_PWCNT (MMCHS1BASE + 0x30)\r
	50	\r
	51	#define MMCHS_BLK (MMCHS1BASE + 0x104)\r
	52	#define BLEN_512BYTES (0x200UL << 0)\r
	53	\r
	54	#define MMCHS_ARG (MMCHS1BASE + 0x108)\r
	55	\r
	56	#define MMCHS_CMD (MMCHS1BASE + 0x10C)\r
	57	#define DE_ENABLE BIT0\r
	58	#define BCE_ENABLE BIT1\r
	59	#define ACEN_ENABLE BIT2\r
	60	#define DDIR_READ BIT4\r
	61	#define DDIR_WRITE (0x0UL << 4)\r
	62	#define MSBS_SGLEBLK (0x0UL << 5)\r
	63	#define MSBS_MULTBLK BIT5\r
	64	#define RSP_TYPE_MASK (0x3UL << 16)\r
65	#define RSP_TYPE_136BITS BIT16\r
66	#define RSP_TYPE_48BITS (0x2UL << 16)\r
67	#define CCCE_ENABLE BIT19\r
68	#define CICE_ENABLE BIT20\r
3402aac7	69	#define DP_ENABLE BIT21\r
1e57a462	70	#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)\r
	71	\r
	72	#define MMCHS_RSP10 (MMCHS1BASE + 0x110)\r
	73	#define MMCHS_RSP32 (MMCHS1BASE + 0x114)\r
	74	#define MMCHS_RSP54 (MMCHS1BASE + 0x118)\r
	75	#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)\r
	76	#define MMCHS_DATA (MMCHS1BASE + 0x120)\r
	77	\r
	78	#define MMCHS_PSTATE (MMCHS1BASE + 0x124)\r
	79	#define CMDI_MASK BIT0\r
	80	#define CMDI_ALLOWED (0x0UL << 0)\r
	81	#define CMDI_NOT_ALLOWED BIT0\r
	82	#define DATI_MASK BIT1\r
	83	#define DATI_ALLOWED (0x0UL << 1)\r
	84	#define DATI_NOT_ALLOWED BIT1\r
	85	\r
	86	#define MMCHS_HCTL (MMCHS1BASE + 0x128)\r
	87	#define DTW_1_BIT (0x0UL << 1)\r
	88	#define DTW_4_BIT BIT1\r
	89	#define SDBP_MASK BIT8\r
	90	#define SDBP_OFF (0x0UL << 8)\r
	91	#define SDBP_ON BIT8\r
	92	#define SDVS_1_8_V (0x5UL << 9)\r
	93	#define SDVS_3_0_V (0x6UL << 9)\r
	94	#define IWE BIT24\r
	95	\r
	96	#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)\r
	97	#define ICE BIT0\r
	98	#define ICS_MASK BIT1\r
	99	#define ICS BIT1\r
	100	#define CEN BIT2\r
	101	#define CLKD_MASK (0x3FFUL << 6)\r
	102	#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2\r
	103	#define CLKD_400KHZ (0xF0UL)\r
	104	#define DTO_MASK (0xFUL << 16)\r
	105	#define DTO_VAL (0xEUL << 16)\r
	106	#define SRA BIT24\r
	107	#define SRC_MASK BIT25\r
	108	#define SRC BIT25\r
	109	#define SRD BIT26\r
	110	\r
	111	#define MMCHS_STAT (MMCHS1BASE + 0x130)\r
	112	#define CC BIT0\r
	113	#define TC BIT1\r
	114	#define BWR BIT4\r
	115	#define BRR BIT5\r
	116	#define ERRI BIT15\r
	117	#define CTO BIT16\r
	118	#define DTO BIT20\r
	119	#define DCRC BIT21\r
	120	#define DEB BIT22\r
	121	\r
	122	#define MMCHS_IE (MMCHS1BASE + 0x134)\r
	123	#define CC_EN BIT0\r
	124	#define TC_EN BIT1\r
	125	#define BWR_EN BIT4\r
	126	#define BRR_EN BIT5\r
	127	#define CTO_EN BIT16\r
	128	#define CCRC_EN BIT17\r
	129	#define CEB_EN BIT18\r
	130	#define CIE_EN BIT19\r
	131	#define DTO_EN BIT20\r
	132	#define DCRC_EN BIT21\r
	133	#define DEB_EN BIT22\r
134	#define CERR_EN BIT28\r
135	#define BADA_EN BIT29\r
136	\r
137	#define MMCHS_ISE (MMCHS1BASE + 0x138)\r
138	#define CC_SIGEN BIT0\r
139	#define TC_SIGEN BIT1\r
140	#define BWR_SIGEN BIT4\r
141	#define BRR_SIGEN BIT5\r
142	#define CTO_SIGEN BIT16\r
143	#define CCRC_SIGEN BIT17\r
144	#define CEB_SIGEN BIT18\r
145	#define CIE_SIGEN BIT19\r
146	#define DTO_SIGEN BIT20\r
147	#define DCRC_SIGEN BIT21\r
148	#define DEB_SIGEN BIT22\r
149	#define CERR_SIGEN BIT28\r
150	#define BADA_SIGEN BIT29\r
151	\r
152	#define MMCHS_AC12 (MMCHS1BASE + 0x13C)\r
153	\r
154	#define MMCHS_CAPA (MMCHS1BASE + 0x140)\r
155	#define VS30 BIT25\r
156	#define VS18 BIT26\r
157	\r
158	#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)\r
159	#define MMCHS_REV (MMCHS1BASE + 0x1FC)\r
160	\r
161	#define CMD0 INDX(0)\r
162	#define CMD0_INT_EN (CC_EN \| CEB_EN)\r
163	\r
164	#define CMD1 (INDX(1) \| RSP_TYPE_48BITS)\r
165	#define CMD1_INT_EN (CC_EN \| CEB_EN \| CTO_EN)\r
166	\r
167	#define CMD2 (INDX(2) \| CCCE_ENABLE \| RSP_TYPE_136BITS)\r
168	#define CMD2_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
169	\r
170	#define CMD3 (INDX(3) \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS)\r
171	#define CMD3_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
172	\r
173	#define CMD5 (INDX(5) \| RSP_TYPE_48BITS)\r
174	#define CMD5_INT_EN (CC_EN \| CEB_EN \| CTO_EN)\r
175	\r
176	#define CMD7 (INDX(7) \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS)\r
177	#define CMD7_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
178	\r
179	#define CMD8 (INDX(8) \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS)\r
180	#define CMD8_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
181	//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE\r
182	#define CMD8_ARG (0x0UL << 12 \| BIT8 \| 0xCEUL << 0)\r
183	\r
184	#define CMD9 (INDX(9) \| CCCE_ENABLE \| RSP_TYPE_136BITS)\r
185	#define CMD9_INT_EN (CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
186	\r
187	#define CMD16 (INDX(16) \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS)\r
188	#define CMD16_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
189	\r
190	#define CMD17 (INDX(17) \| DP_ENABLE \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS \| DDIR_READ)\r
191	#define CMD17_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| TC_EN \| BRR_EN \| CTO_EN \| DTO_EN \| DCRC_EN \| DEB_EN \| CEB_EN)\r
192	\r
193	#define CMD18 (INDX(18) \| DP_ENABLE \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS \| MSBS_MULTBLK \| DDIR_READ \| BCE_ENABLE \| DE_ENABLE)\r
194	#define CMD18_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| TC_EN \| BRR_EN \| CTO_EN \| DTO_EN \| DCRC_EN \| DEB_EN \| CEB_EN)\r
195	\r
196	#define CMD23 (INDX(23) \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS)\r
197	#define CMD23_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
198	\r
199	#define CMD24 (INDX(24) \| DP_ENABLE \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS \| DDIR_WRITE)\r
200	#define CMD24_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| TC_EN \| BWR_EN \| CTO_EN \| DTO_EN \| DCRC_EN \| DEB_EN \| CEB_EN)\r
201	\r
202	#define CMD25 (INDX(25) \| DP_ENABLE \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS \| MSBS_MULTBLK \| DDIR_READ \| BCE_ENABLE \| DE_ENABLE)\r
203	#define CMD25_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| TC_EN \| BRR_EN \| CTO_EN \| DTO_EN \| DCRC_EN \| DEB_EN \| CEB_EN)\r
204	\r
205	#define CMD55 (INDX(55) \| CICE_ENABLE \| CCCE_ENABLE \| RSP_TYPE_48BITS)\r
206	#define CMD55_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
207	\r
208	#define ACMD41 (INDX(41) \| RSP_TYPE_48BITS)\r
209	#define ACMD41_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
210	\r
211	#define ACMD6 (INDX(6) \| RSP_TYPE_48BITS)\r
212	#define ACMD6_INT_EN (CERR_EN \| CIE_EN \| CCRC_EN \| CC_EN \| CEB_EN \| CTO_EN)\r
213	\r
214	#endif //__OMAP3530SDIO_H__\r