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1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | \r |
| 5 | This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | \r |
| 13 | **/\r |
| 14 | \r |
| 15 | #ifndef __OMAP3530PRCM_H__\r |
| 16 | #define __OMAP3530PRCM_H__\r |
| 17 | \r |
| 18 | #define CM_FCLKEN1_CORE (0x48004A00)\r |
| 19 | #define CM_FCLKEN3_CORE (0x48004A08)\r |
| 20 | #define CM_ICLKEN1_CORE (0x48004A10)\r |
| 21 | #define CM_ICLKEN3_CORE (0x48004A18)\r |
| 22 | #define CM_CLKEN2_PLL (0x48004D04)\r |
| 23 | #define CM_CLKSEL4_PLL (0x48004D4C)\r |
| 24 | #define CM_CLKSEL5_PLL (0x48004D50)\r |
| 25 | #define CM_FCLKEN_USBHOST (0x48005400)\r |
| 26 | #define CM_ICLKEN_USBHOST (0x48005410)\r |
| 27 | #define CM_CLKSTST_USBHOST (0x4800544c)\r |
| 28 | \r |
| 29 | //Wakeup clock defintion\r |
| 30 | #define CM_FCLKEN_WKUP (0x48004C00)\r |
| 31 | #define CM_ICLKEN_WKUP (0x48004C10)\r |
| 32 | \r |
| 33 | //Peripheral clock definition\r |
| 34 | #define CM_FCLKEN_PER (0x48005000)\r |
| 35 | #define CM_ICLKEN_PER (0x48005010)\r |
| 36 | #define CM_CLKSEL_PER (0x48005040)\r |
| 37 | \r |
| 38 | //Reset management definition\r |
| 39 | #define PRM_RSTCTRL (0x48307250)\r |
| 40 | #define PRM_RSTST (0x48307258)\r |
| 41 | \r |
| 42 | //CORE clock\r |
| 43 | #define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15\r |
| 44 | #define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)\r |
| 45 | #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15\r |
| 46 | \r |
| 47 | #define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15\r |
| 48 | #define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)\r |
| 49 | #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15\r |
| 50 | \r |
| 51 | #define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24\r |
| 52 | #define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)\r |
| 53 | #define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24\r |
| 54 | \r |
| 55 | #define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2\r |
| 56 | #define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)\r |
| 57 | #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2\r |
| 58 | \r |
| 59 | #define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24\r |
| 60 | #define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)\r |
| 61 | #define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24\r |
| 62 | \r |
| 63 | #define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2\r |
| 64 | #define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)\r |
| 65 | #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2\r |
| 66 | \r |
| 67 | #define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)\r |
| 68 | #define CM_CLKEN_ENABLE (7UL << 0)\r |
| 69 | \r |
| 70 | #define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)\r |
| 71 | #define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)\r |
| 3402aac7 |
72 | \r |
| 1e57a462 |
73 | #define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)\r |
| 74 | \r |
| 75 | #define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1\r |
| 76 | #define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)\r |
| 77 | #define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1\r |
| 78 | \r |
| 79 | #define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0\r |
| 80 | #define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)\r |
| 81 | #define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0\r |
| 82 | \r |
| 83 | #define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0\r |
| 84 | #define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)\r |
| 85 | #define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0\r |
| 86 | \r |
| 87 | //Wakeup functional clock\r |
| 88 | #define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)\r |
| 89 | #define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3\r |
| 90 | \r |
| 91 | #define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)\r |
| 92 | #define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5\r |
| 93 | \r |
| 94 | //Wakeup interface clock\r |
| 95 | #define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)\r |
| 96 | #define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3\r |
| 97 | \r |
| 98 | #define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)\r |
| 99 | #define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5\r |
| 100 | \r |
| 101 | //Peripheral functional clock\r |
| 102 | #define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)\r |
| 103 | #define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4\r |
| 104 | \r |
| 105 | #define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)\r |
| 106 | #define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5\r |
| 107 | \r |
| 108 | #define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)\r |
| 109 | #define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11\r |
| 110 | \r |
| 111 | #define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)\r |
| 112 | #define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13\r |
| 113 | \r |
| 114 | #define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)\r |
| 115 | #define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14\r |
| 116 | \r |
| 117 | #define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)\r |
| 118 | #define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15\r |
| 119 | \r |
| 120 | #define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)\r |
| 121 | #define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16\r |
| 122 | \r |
| 123 | #define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)\r |
| 124 | #define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17\r |
| 125 | \r |
| 126 | //Peripheral interface clock\r |
| 127 | #define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)\r |
| 128 | #define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4\r |
| 129 | \r |
| 130 | #define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)\r |
| 131 | #define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5\r |
| 132 | \r |
| 133 | #define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)\r |
| 134 | #define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11\r |
| 135 | \r |
| 136 | #define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)\r |
| 137 | #define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13\r |
| 138 | \r |
| 139 | #define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)\r |
| 140 | #define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14\r |
| 141 | \r |
| 142 | #define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)\r |
| 143 | #define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15\r |
| 144 | \r |
| 145 | #define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)\r |
| 146 | #define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16\r |
| 147 | \r |
| 148 | #define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)\r |
| 149 | #define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17\r |
| 150 | \r |
| 151 | //Timer source clock selection\r |
| 152 | #define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)\r |
| 153 | #define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1\r |
| 154 | \r |
| 155 | #define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)\r |
| 156 | #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2\r |
| 157 | \r |
| 158 | //Reset management (Global and Cold reset)\r |
| 159 | #define RST_GS BIT1\r |
| 160 | #define RST_DPLL3 BIT2\r |
| 161 | #define GLOBAL_SW_RST BIT1\r |
| 162 | #define GLOBAL_COLD_RST (0x0UL << 0)\r |
| 163 | \r |
| 164 | #endif // __OMAP3530PRCM_H__\r |
| 165 | \r |
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