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1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | \r |
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5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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6 | \r |
| 7 | **/\r |
| 8 | \r |
| 9 | #ifndef __TPS65950_H__\r |
| 10 | #define __TPS65950_H__\r |
| 11 | \r |
| 12 | #define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x) (((x) >> 8) & 0xFF)\r |
| 13 | #define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x) ((x) & 0xFF)\r |
| 14 | #define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF))\r |
| 15 | \r |
| 16 | // I2C Address group\r |
| 17 | #define I2C_ADDR_GRP_ID1 0x48\r |
| 18 | #define I2C_ADDR_GRP_ID2 0x49\r |
| 19 | #define I2C_ADDR_GRP_ID3 0x4A\r |
| 20 | #define I2C_ADDR_GRP_ID4 0x4B\r |
| 21 | #define I2C_ADDR_GRP_ID5 0x12\r |
| 22 | \r |
| 23 | // MMC definitions.\r |
| 24 | #define VMMC1_DEV_GRP 0x82\r |
| 25 | #define DEV_GRP_P1 BIT5\r |
| 26 | \r |
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27 | #define VMMC1_DEDICATED_REG 0x85\r |
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28 | #define VSEL_1_85V 0x0\r |
| 29 | #define VSEL_2_85V 0x1\r |
| 30 | #define VSEL_3_00V 0x2\r |
| 31 | #define VSEL_3_15V 0x3\r |
| 32 | \r |
| 33 | #define TPS65950_GPIO_CTRL 0xaa //I2C_ADDR_GRP_ID2\r |
| 34 | #define CARD_DETECT_ENABLE (BIT2 | BIT0) // GPIO ON + GPIO CD1 enabled\r |
| 35 | \r |
| 36 | \r |
| 37 | #define GPIODATAIN1 0x98 //I2C_ADDR_GRP_ID2\r |
| 38 | #define CARD_DETECT_BIT BIT0\r |
| 39 | \r |
| 40 | // LEDEN register\r |
| 41 | #define LEDEN 0xEE\r |
| 42 | #define LEDAON BIT0\r |
| 43 | #define LEDBON BIT1\r |
| 44 | #define LEDAPWM BIT4\r |
| 45 | #define LEDBPWM BIT5\r |
| 46 | \r |
| 47 | // RTC registers\r |
| 48 | #define SECONDS_REG 0x1C\r |
| 49 | #define MINUTES_REG 0x1D\r |
| 50 | #define HOURS_REG 0x1E\r |
| 51 | #define DAYS_REG 0x1F\r |
| 52 | #define MONTHS_REG 0x20\r |
| 53 | #define YEARS_REG 0x21\r |
| 54 | #define WEEKS_REG 0x22\r |
| 55 | #define RTC_CTRL_REG 0x29\r |
| 56 | \r |
| 57 | // USB PHY power\r |
| 58 | #define VAUX2_DEDICATED 0x79\r |
| 59 | #define VAUX2_DEV_GRP 0x76\r |
| 60 | \r |
| 61 | #define VAUX_DEV_GRP_NONE 0x00\r |
| 62 | #define VAUX_DEV_GRP_P1 0x20\r |
| 63 | #define VAUX_DEV_GRP_P2 0x40\r |
| 64 | #define VAUX_DEV_GRP_P3 0x80\r |
| 65 | #define VAUX_DEDICATED_18V 0x05\r |
| 66 | \r |
| 67 | // Display subsystem\r |
| 68 | #define VPLL2_DEDICATED 0x91\r |
| 69 | #define VPLL2_DEV_GRP 0x8E\r |
| 70 | \r |
| 71 | #define GPIODATADIR1 0x9B\r |
| 72 | #define SETGPIODATAOUT1 0xA4\r |
| 73 | \r |
| 74 | #endif //__TPS65950_H__\r |
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