| 1e57a462 |
1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r |
| 4 | This program and the accompanying materials\r |
| 5 | are licensed and made available under the terms and conditions of the BSD License\r |
| 6 | which accompanies this distribution. The full text of the license may be found at\r |
| 7 | http://opensource.org/licenses/bsd-license.php\r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 11 | \r |
| 12 | **/\r |
| 13 | \r |
| 14 | #ifndef __OMAP3_DSS_GRAPHICS__\r |
| 15 | #define __OMAP3_DSS_GRAPHICS__\r |
| 16 | \r |
| 17 | #include <Library/UefiBootServicesTableLib.h>\r |
| 18 | #include <Library/UefiLib.h>\r |
| 19 | #include <Library/DebugLib.h>\r |
| 20 | #include <Library/MemoryAllocationLib.h>\r |
| 21 | #include <Library/IoLib.h>\r |
| 22 | \r |
| 23 | #include <Protocol/DevicePathToText.h>\r |
| 24 | #include <Protocol/EmbeddedExternalDevice.h>\r |
| 25 | #include <Protocol/Cpu.h>\r |
| 26 | \r |
| 27 | #include <Guid/GlobalVariable.h>\r |
| 28 | \r |
| 29 | #include <Omap3530/Omap3530.h>\r |
| 30 | #include <TPS65950.h>\r |
| 31 | \r |
| 32 | typedef struct {\r |
| 33 | VENDOR_DEVICE_PATH Guid;\r |
| 34 | EFI_DEVICE_PATH_PROTOCOL End;\r |
| 35 | } LCD_GRAPHICS_DEVICE_PATH;\r |
| 36 | \r |
| 37 | typedef struct {\r |
| 38 | UINTN Signature;\r |
| 39 | EFI_HANDLE Handle;\r |
| 40 | EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;\r |
| 41 | EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode;\r |
| 42 | EFI_GRAPHICS_OUTPUT_PROTOCOL Gop;\r |
| 43 | LCD_GRAPHICS_DEVICE_PATH DevicePath;\r |
| 44 | // EFI_EVENT ExitBootServicesEvent;\r |
| 45 | } LCD_INSTANCE;\r |
| 46 | \r |
| 47 | #define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0')\r |
| 48 | #define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE)\r |
| 49 | \r |
| 50 | typedef struct {\r |
| 51 | UINTN Mode;\r |
| 52 | UINTN HorizontalResolution;\r |
| 53 | UINTN VerticalResolution;\r |
| 54 | \r |
| 55 | UINT32 DssDivisor;\r |
| 56 | UINT32 DispcDivisor;\r |
| 57 | \r |
| 58 | UINT32 HSync;\r |
| 59 | UINT32 HFrontPorch;\r |
| 60 | UINT32 HBackPorch;\r |
| 61 | \r |
| 62 | UINT32 VSync;\r |
| 63 | UINT32 VFrontPorch;\r |
| 64 | UINT32 VBackPorch;\r |
| 65 | } LCD_MODE;\r |
| 66 | \r |
| 67 | EFI_STATUS\r |
| 68 | InitializeDisplay (\r |
| 69 | IN LCD_INSTANCE* Instance\r |
| 70 | );\r |
| 71 | \r |
| 72 | EFI_STATUS\r |
| 73 | EFIAPI\r |
| 74 | LcdGraphicsQueryMode (\r |
| 75 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,\r |
| 76 | IN UINT32 ModeNumber,\r |
| 77 | OUT UINTN *SizeOfInfo,\r |
| 78 | OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info\r |
| 79 | );\r |
| 80 | \r |
| 81 | EFI_STATUS\r |
| 82 | EFIAPI\r |
| 83 | LcdGraphicsSetMode (\r |
| 84 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,\r |
| 85 | IN UINT32 ModeNumber\r |
| 86 | );\r |
| 87 | \r |
| 88 | EFI_STATUS\r |
| 89 | EFIAPI\r |
| 90 | LcdGraphicsBlt (\r |
| 91 | IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,\r |
| 92 | IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL\r |
| 93 | IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,\r |
| 94 | IN UINTN SourceX,\r |
| 95 | IN UINTN SourceY,\r |
| 96 | IN UINTN DestinationX,\r |
| 97 | IN UINTN DestinationY,\r |
| 98 | IN UINTN Width,\r |
| 99 | IN UINTN Height,\r |
| 100 | IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer\r |
| 101 | );\r |
| 102 | \r |
| 103 | // HW registers\r |
| 104 | #define CM_FCLKEN_DSS 0x48004E00\r |
| 105 | #define CM_ICLKEN_DSS 0x48004E10\r |
| 106 | \r |
| 107 | #define DSS_CONTROL 0x48050040\r |
| 108 | #define DSS_SYSCONFIG 0x48050010\r |
| 109 | #define DSS_SYSSTATUS 0x48050014\r |
| 110 | \r |
| 111 | #define DISPC_CONTROL 0x48050440\r |
| 112 | #define DISPC_CONFIG 0x48050444\r |
| 113 | #define DISPC_SIZE_LCD 0x4805047C\r |
| 114 | #define DISPC_TIMING_H 0x48050464\r |
| 115 | #define DISPC_TIMING_V 0x48050468\r |
| 116 | \r |
| 117 | #define CM_CLKSEL_DSS 0x48004E40\r |
| 118 | #define DISPC_DIVISOR 0x48050470\r |
| 119 | #define DISPC_POL_FREQ 0x4805046C\r |
| 120 | \r |
| 121 | #define DISPC_GFX_TABLE_BA 0x480504B8\r |
| 122 | #define DISPC_GFX_BA0 0x48050480\r |
| 123 | #define DISPC_GFX_BA1 0x48050484\r |
| 124 | #define DISPC_GFX_POS 0x48050488\r |
| 125 | #define DISPC_GFX_SIZE 0x4805048C\r |
| 126 | #define DISPC_GFX_ATTR 0x480504A0\r |
| 127 | #define DISPC_GFX_PRELD 0x4805062C\r |
| 128 | \r |
| 129 | #define DISPC_DEFAULT_COLOR_0 0x4805044C\r |
| 130 | \r |
| 131 | //#define DISPC_IRQSTATUS\r |
| 132 | \r |
| 133 | // Bits\r |
| 134 | #define EN_TV 0x4\r |
| 135 | #define EN_DSS2 0x2\r |
| 136 | #define EN_DSS1 0x1\r |
| 137 | #define EN_DSS 0x1\r |
| 138 | \r |
| 139 | #define DSS_SOFTRESET 0x2\r |
| 140 | #define DSS_RESETDONE 0x1\r |
| 141 | \r |
| 142 | #define BYPASS_MODE (BIT15 | BIT16)\r |
| 143 | \r |
| 144 | #define LCDENABLE BIT0\r |
| 145 | #define ACTIVEMATRIX BIT3\r |
| 146 | #define GOLCD BIT5\r |
| 147 | #define DATALINES24 (BIT8 | BIT9) \r |
| 148 | #define LCDENABLESIGNAL BIT28\r |
| 149 | \r |
| 150 | #define GFXENABLE BIT0\r |
| 151 | #define RGB16 (0x6 << 1)\r |
| 152 | #define BURSTSIZE16 (0x2 << 6)\r |
| 153 | \r |
| 154 | #define CLEARLOADMODE ~(BIT2 | BIT1)\r |
| 155 | #define LOAD_FRAME_ONLY BIT2\r |
| 156 | \r |
| 157 | #endif\r |
projects / mirror_edk2.git / blame