[mirror_edk2.git] / Omap35xxPkg / Library / OmapDmaLib / OmapDmaLib.c

/** @file\r
  OMAP35xx DMA abstractions modeled on PCI IO protocol. EnableDma()/DisableDma()\r
  are from OMAP35xx TRM. \r
\r
  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
  \r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Base.h>\r
#include <Library/DebugLib.h>\r
#include <Library/OmapDmaLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UncachedMemoryAllocationLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ArmLib.h>\r
#include <Omap3530/Omap3530.h>\r
\r
#include <Protocol/Cpu.h>\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS      HostAddress;\r
  EFI_PHYSICAL_ADDRESS      DeviceAddress;\r
  UINTN                     NumberOfBytes;\r
  DMA_MAP_OPERATION         Operation;\r
  BOOLEAN                   DoubleBuffer;\r
} MAP_INFO_INSTANCE;\r
\r
\r
\r
EFI_CPU_ARCH_PROTOCOL      *gCpu;\r
UINTN                      gCacheAlignment = 0;\r
\r
/**                                                                 \r
  Configure OMAP DMA Channel\r
            \r
  @param  Channel               DMA Channel to configure\r
  @param  Dma4                  Pointer to structure used to initialize DMA registers for the Channel                                                \r
                                  \r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_INVALID_PARAMETER Channel is not valid\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.\r
                                   \r
**/\r
EFI_STATUS\r
EFIAPI\r
EnableDmaChannel (\r
  IN  UINTN       Channel,\r
  IN  OMAP_DMA4   *DMA4\r
  )\r
{\r
  UINT32  RegVal;\r
\r
\r
  if (Channel > DMA4_MAX_CHANNEL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  /* 1) Configure the transfer parameters in the logical DMA registers */\r
  /*-------------------------------------------------------------------*/\r
\r
  /* a) Set the data type CSDP[1:0], the Read/Write Port access type \r
        CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19], \r
        write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */\r
  \r
  // Read CSDP\r
  RegVal = MmioRead32 (DMA4_CSDP (Channel));\r
  \r
  // Build reg\r
  RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );\r
  RegVal = ((RegVal & ~(0x3 <<  7)) | (DMA4->ReadPortAccessType << 7));\r
  RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));\r
  RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));\r
  RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));\r
  RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));\r
  RegVal = ((RegVal & ~(0x1 <<  6)) | (DMA4->SourcePacked << 6));\r
  RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));\r
  // Write CSDP\r
  MmioWrite32 (DMA4_CSDP (Channel), RegVal);\r
  \r
  /* b) Set the number of element per frame CEN[23:0]*/\r
  MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);\r
 \r
  /* c) Set the number of frame per block CFN[15:0]*/\r
  MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);\r
  \r
  /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/\r
  MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);\r
  MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);\r
  \r
  /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],\r
        read/write priority CCR[6]/CCR[26]\r
        I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to \r
        LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber\r
  */\r
  \r
  // Read CCR\r
  RegVal = MmioRead32 (DMA4_CCR (Channel));\r
\r
  // Build reg\r
  RegVal  = ((RegVal &  ~0x1f)            | DMA4->ReadRequestNumber);\r
  RegVal  = ((RegVal &  ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);\r
  RegVal  = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));\r
  RegVal  = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));\r
  RegVal  = ((RegVal & ~(0x1 <<  6)) | (DMA4->ReadPriority << 6));\r
  RegVal  = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));\r
  \r
  // Write CCR\r
  MmioWrite32 (DMA4_CCR (Channel), RegVal);\r
  \r
  /* f)- Set the source element index CSEI[15:0]*/\r
  MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);\r
  \r
  /* - Set the source frame index CSFI[15:0]*/\r
  MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);\r
\r
\r
  /* - Set the destination element index CDEI[15:0]*/\r
  MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);\r
\r
  /* - Set the destination frame index CDFI[31:0]*/\r
  MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
 \r
  MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
\r
  // Enable all the status bits since we are polling\r
  MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);\r
  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);\r
\r
  /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */\r
  /*--------------------------------------------------------------*/\r
  //write enable bit\r
  MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**                                                                 \r
  Turn of DMA channel configured by EnableDma().\r
            \r
  @param  Channel               DMA Channel to configure\r
  @param  SuccesMask            Bits in DMA4_CSR register indicate EFI_SUCCESS\r
  @param  ErrorMask             Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r
                                  \r
  @retval EFI_SUCCESS           DMA hardware disabled\r
  @retval EFI_INVALID_PARAMETER Channel is not valid\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested information.\r
                                   \r
**/\r
EFI_STATUS\r
EFIAPI\r
DisableDmaChannel (\r
  IN  UINTN       Channel,\r
  IN  UINT32      SuccessMask,\r
  IN  UINT32      ErrorMask\r
  )\r
{\r
  EFI_STATUS  Status = EFI_SUCCESS;\r
  UINT32      Reg;\r
\r
\r
  if (Channel > DMA4_MAX_CHANNEL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  do {\r
    Reg = MmioRead32 (DMA4_CSR(Channel));\r
    if ((Reg & ErrorMask) != 0) {\r
      Status = EFI_DEVICE_ERROR;\r
      DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));\r
      break;\r
    }\r
  } while ((Reg & SuccessMask) != SuccessMask);\r
\r
\r
  // Disable all status bits and clear them\r
  MmioWrite32 (DMA4_CICR (Channel), 0);\r
  MmioWrite32 (DMA4_CSR (Channel),  DMA4_CSR_RESET);\r
\r
  MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE)); \r
  return Status;\r
}\r
\r
\r
\r
/**                                                                 \r
  Provides the DMA controller-specific addresses needed to access system memory.\r
  \r
  Operation is relative to the DMA bus master.\r
            \r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the DMA controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.                                                 \r
  @param  DeviceAddress         The resulting map address for the bus master controller to use to\r
                                access the hosts HostAddress.                                        \r
  @param  Mapping               A resulting value to pass to Unmap().\r
                                  \r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.                                \r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
                                   \r
**/\r
EFI_STATUS\r
EFIAPI\r
DmaMap (\r
  IN     DMA_MAP_OPERATION              Operation,\r
  IN     VOID                           *HostAddress,\r
  IN OUT UINTN                          *NumberOfBytes,\r
  OUT    PHYSICAL_ADDRESS               *DeviceAddress,\r
  OUT    VOID                           **Mapping\r
  )\r
{\r
  EFI_STATUS            Status;\r
  MAP_INFO_INSTANCE     *Map;\r
  VOID                  *Buffer;\r
\r
  if ( HostAddress == NULL || NumberOfBytes == NULL || \r
       DeviceAddress == NULL || Mapping == NULL ) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
\r
  if (Operation >= MapOperationMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  *DeviceAddress = ConvertToPhysicalAddress (HostAddress);\r
\r
  // Remember range so we can flush on the other side\r
  Map = AllocatePool (sizeof (MAP_INFO_INSTANCE));\r
  if (Map == NULL) {\r
    return  EFI_OUT_OF_RESOURCES;\r
  }\r
  \r
  *Mapping = Map;\r
\r
  if (((UINTN)HostAddress & (gCacheAlignment - 1)) != 0) {\r
    Map->DoubleBuffer  = TRUE;\r
    Status = DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (*NumberOfBytes), &Buffer);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    \r
    *DeviceAddress = (PHYSICAL_ADDRESS)(UINTN)Buffer;\r
    \r
  } else {\r
    Map->DoubleBuffer  = FALSE;\r
  }\r
\r
  *NumberOfBytes &= *NumberOfBytes & ~(gCacheAlignment - 1); // Only do it on full cache lines\r
  \r
  Map->HostAddress   = (UINTN)HostAddress;\r
  Map->DeviceAddress = *DeviceAddress;\r
  Map->NumberOfBytes = *NumberOfBytes;\r
  Map->Operation     = Operation;\r
\r
  if (Map->DoubleBuffer) {\r
    if (Map->Operation == MapOperationBusMasterWrite) {\r
      CopyMem ((VOID *)(UINTN)Map->DeviceAddress, (VOID *)(UINTN)Map->HostAddress, Map->NumberOfBytes);\r
    }\r
  } else {\r
    // EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate\r
    if (Map->Operation == MapOperationBusMasterWrite || Map->Operation == MapOperationBusMasterRead) {\r
      gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress,  Map->NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);\r
    }\r
  }\r
  \r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**                                                                 \r
  Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()\r
  operation and releases any corresponding resources.\r
            \r
  @param  Mapping               The mapping value returned from DmaMap*().\r
                                  \r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
                                   \r
**/\r
EFI_STATUS\r
EFIAPI\r
DmaUnmap (\r
  IN  VOID                         *Mapping\r
  )\r
{\r
  MAP_INFO_INSTANCE *Map;\r
  \r
  if (Mapping == NULL) {\r
    ASSERT (FALSE);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  Map = (MAP_INFO_INSTANCE *)Mapping;\r
  \r
  if (Map->DoubleBuffer) {\r
    if (Map->Operation == MapOperationBusMasterRead) {\r
      CopyMem ((VOID *)(UINTN)Map->HostAddress, (VOID *)(UINTN)Map->DeviceAddress, Map->NumberOfBytes);\r
    }\r
    \r
    DmaFreeBuffer (EFI_SIZE_TO_PAGES (Map->NumberOfBytes), (VOID *)(UINTN)Map->DeviceAddress);\r
  \r
  } else {\r
    if (Map->Operation == MapOperationBusMasterWrite) {\r
      //\r
      // Make sure we read buffer from uncached memory and not the cache\r
      //\r
      gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);\r
    }\r
  }\r
  \r
  FreePool (Map);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**                                                                 \r
  Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.\r
  mapping.                                                                       \r
            \r
  @param  MemoryType            The type of memory to allocate, EfiBootServicesData or\r
                                EfiRuntimeServicesData.                               \r
  @param  Pages                 The number of pages to allocate.                                \r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.                                        \r
\r
                                @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.                     \r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.  \r
                                   \r
**/\r
EFI_STATUS\r
EFIAPI\r
DmaAllocateBuffer (\r
  IN  EFI_MEMORY_TYPE              MemoryType,\r
  IN  UINTN                        Pages,\r
  OUT VOID                         **HostAddress\r
  )\r
{\r
  if (HostAddress == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
  //\r
  // We used uncached memory to keep coherency\r
  //\r
  if (MemoryType == EfiBootServicesData) {\r
    *HostAddress = UncachedAllocatePages (Pages);\r
  } else if (MemoryType != EfiRuntimeServicesData) {\r
    *HostAddress = UncachedAllocateRuntimePages (Pages);\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**                                                                 \r
  Frees memory that was allocated with DmaAllocateBuffer().\r
            \r
  @param  Pages                 The number of pages to free.                                \r
  @param  HostAddress           The base system memory address of the allocated range.                                    \r
                                  \r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with DmaAllocateBuffer().\r
                                     \r
**/\r
EFI_STATUS\r
EFIAPI\r
DmaFreeBuffer (\r
  IN  UINTN                        Pages,\r
  IN  VOID                         *HostAddress\r
  )\r
{\r
  if (HostAddress == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
  } \r
  \r
  UncachedFreePages (HostAddress, Pages);\r
  return EFI_SUCCESS;\r
}\r
\r
\r
EFI_STATUS\r
EFIAPI\r
OmapDmaLibConstructor (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  )\r
{\r
  EFI_STATUS              Status;\r
\r
  // Get the Cpu protocol for later use\r
  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  gCacheAlignment = ArmDataCacheLineLength ();\r
  \r
  return Status;\r
}\r
\r
Commit	Line	Data
7f814ffd	1	/** @file\r
	2	OMAP35xx DMA abstractions modeled on PCI IO protocol. EnableDma()/DisableDma()\r
	3	are from OMAP35xx TRM. \r
	4	\r
	5	Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
	6	\r
	7	This program and the accompanying materials\r
	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	#include <Base.h>\r
	18	#include <Library/DebugLib.h>\r
	19	#include <Library/OmapDmaLib.h>\r
	20	#include <Library/MemoryAllocationLib.h>\r
	21	#include <Library/UefiBootServicesTableLib.h>\r
	22	#include <Library/UncachedMemoryAllocationLib.h>\r
	23	#include <Library/IoLib.h>\r
8e7c9e03	24	#include <Library/BaseMemoryLib.h>\r
8e7c9e03	25	#include <Library/ArmLib.h>\r
7f814ffd	26	#include <Omap3530/Omap3530.h>\r
	27	\r
	28	#include <Protocol/Cpu.h>\r
	29	\r
	30	typedef struct {\r
	31	EFI_PHYSICAL_ADDRESS HostAddress;\r
	32	EFI_PHYSICAL_ADDRESS DeviceAddress;\r
	33	UINTN NumberOfBytes;\r
	34	DMA_MAP_OPERATION Operation;\r
8e7c9e03	35	BOOLEAN DoubleBuffer;\r
7f814ffd	36	} MAP_INFO_INSTANCE;\r
	37	\r
	38	\r
	39	\r
8e7c9e03	40	EFI_CPU_ARCH_PROTOCOL *gCpu;\r
8e7c9e03	41	UINTN gCacheAlignment = 0;\r
7f814ffd	42	\r
	43	/** \r
	44	Configure OMAP DMA Channel\r
	45	\r
	46	@param Channel DMA Channel to configure\r
	47	@param Dma4 Pointer to structure used to initialize DMA registers for the Channel \r
	48	\r
	49	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
	50	@retval EFI_INVALID_PARAMETER Channel is not valid\r
	51	@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.\r
	52	\r
8e7c9e03	53	**/\r
	54	EFI_STATUS\r
	55	EFIAPI\r
	56	EnableDmaChannel (\r
	57	IN UINTN Channel,\r
	58	IN OMAP_DMA4 *DMA4\r
	59	)\r
	60	{\r
	61	UINT32 RegVal;\r
	62	\r
	63	\r
	64	if (Channel > DMA4_MAX_CHANNEL) {\r
	65	return EFI_INVALID_PARAMETER;\r
	66	}\r
	67	\r
7f814ffd	68	/* 1) Configure the transfer parameters in the logical DMA registers */\r
	69	/-------------------------------------------------------------------/\r
	70	\r
	71	/* a) Set the data type CSDP[1:0], the Read/Write Port access type \r
	72	CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19], \r
	73	write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */\r
	74	\r
	75	// Read CSDP\r
	76	RegVal = MmioRead32 (DMA4_CSDP (Channel));\r
	77	\r
	78	// Build reg\r
	79	RegVal = ((RegVal & ~ 0x3) \| DMA4->DataType );\r
	80	RegVal = ((RegVal & ~(0x3 << 7)) \| (DMA4->ReadPortAccessType << 7));\r
	81	RegVal = ((RegVal & ~(0x3 << 14)) \| (DMA4->WritePortAccessType << 14));\r
	82	RegVal = ((RegVal & ~(0x1 << 21)) \| (DMA4->SourceEndiansim << 21));\r
	83	RegVal = ((RegVal & ~(0x1 << 19)) \| (DMA4->DestinationEndianism << 19));\r
	84	RegVal = ((RegVal & ~(0x3 << 16)) \| (DMA4->WriteMode << 16));\r
	85	RegVal = ((RegVal & ~(0x1 << 6)) \| (DMA4->SourcePacked << 6));\r
	86	RegVal = ((RegVal & ~(0x1 << 13)) \| (DMA4->DestinationPacked << 13));\r
	87	// Write CSDP\r
	88	MmioWrite32 (DMA4_CSDP (Channel), RegVal);\r
	89	\r
	90	/* b) Set the number of element per frame CEN[23:0]*/\r
	91	MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);\r
	92	\r
	93	/* c) Set the number of frame per block CFN[15:0]*/\r
	94	MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);\r
	95	\r
	96	/* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/\r
	97	MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);\r
	98	MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);\r
	99	\r
	100	/* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],\r
	101	read/write priority CCR[6]/CCR[26]\r
	102	I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to \r
	103	LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber\r
	104	*/\r
	105	\r
	106	// Read CCR\r
	107	RegVal = MmioRead32 (DMA4_CCR (Channel));\r
	108	\r
	109	// Build reg\r
	110	RegVal = ((RegVal & ~0x1f) \| DMA4->ReadRequestNumber);\r
	111	RegVal = ((RegVal & ~(BIT20 \| BIT19)) \| DMA4->WriteRequestNumber << 19);\r
	112	RegVal = ((RegVal & ~(0x3 << 12)) \| (DMA4->ReadPortAccessMode << 12));\r
	113	RegVal = ((RegVal & ~(0x3 << 14)) \| (DMA4->WritePortAccessMode << 14));\r
	114	RegVal = ((RegVal & ~(0x1 << 6)) \| (DMA4->ReadPriority << 6));\r
	115	RegVal = ((RegVal & ~(0x1 << 26)) \| (DMA4->WritePriority << 26));\r
	116	\r
	117	// Write CCR\r
	118	MmioWrite32 (DMA4_CCR (Channel), RegVal);\r
	119	\r
	120	/* f)- Set the source element index CSEI[15:0]*/\r
	121	MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);\r
	122	\r
	123	/* - Set the source frame index CSFI[15:0]*/\r
	124	MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);\r
	125	\r
	126	\r
	127	/* - Set the destination element index CDEI[15:0]*/\r
	128	MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);\r
	129	\r
	130	/* - Set the destination frame index CDFI[31:0]*/\r
	131	MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
9f6b977f	132	\r
	133	MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);\r
	134	\r
	135	// Enable all the status bits since we are polling\r
	136	MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);\r
	137	MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);\r
	138	\r
7f814ffd	139	/* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */\r
	140	/--------------------------------------------------------------/\r
	141	//write enable bit\r
8e7c9e03	142	MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer\r
	143	\r
	144	return EFI_SUCCESS;\r
	145	}\r
	146	\r
7f814ffd	147	/** \r
	148	Turn of DMA channel configured by EnableDma().\r
	149	\r
	150	@param Channel DMA Channel to configure\r
9f6b977f	151	@param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS\r
9f6b977f	152	@param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r
7f814ffd	153	\r
	154	@retval EFI_SUCCESS DMA hardware disabled\r
	155	@retval EFI_INVALID_PARAMETER Channel is not valid\r
	156	@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.\r
	157	\r
8e7c9e03	158	**/\r
	159	EFI_STATUS\r
	160	EFIAPI\r
	161	DisableDmaChannel (\r
	162	IN UINTN Channel,\r
	163	IN UINT32 SuccessMask,\r
	164	IN UINT32 ErrorMask\r
	165	)\r
	166	{\r
	167	EFI_STATUS Status = EFI_SUCCESS;\r
	168	UINT32 Reg;\r
	169	\r
	170	\r
	171	if (Channel > DMA4_MAX_CHANNEL) {\r
	172	return EFI_INVALID_PARAMETER;\r
	173	}\r
	174	\r
	175	do {\r
	176	Reg = MmioRead32 (DMA4_CSR(Channel));\r
	177	if ((Reg & ErrorMask) != 0) {\r
	178	Status = EFI_DEVICE_ERROR;\r
	179	DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));\r
	180	break;\r
	181	}\r
	182	} while ((Reg & SuccessMask) != SuccessMask);\r
	183	\r
	184	\r
	185	// Disable all status bits and clear them\r
9f6b977f	186	MmioWrite32 (DMA4_CICR (Channel), 0);\r
8e7c9e03	187	MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);\r
	188	\r
	189	MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE \| DMA4_CCR_RD_ACTIVE \| DMA4_CCR_WR_ACTIVE)); \r
	190	return Status;\r
	191	}\r
	192	\r
	193	\r
	194	\r
7f814ffd	195	/** \r
	196	Provides the DMA controller-specific addresses needed to access system memory.\r
	197	\r
	198	Operation is relative to the DMA bus master.\r
	199	\r
	200	@param Operation Indicates if the bus master is going to read or write to system memory.\r
	201	@param HostAddress The system memory address to map to the DMA controller.\r
	202	@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
	203	that were mapped. \r
	204	@param DeviceAddress The resulting map address for the bus master controller to use to\r
	205	access the hosts HostAddress. \r
	206	@param Mapping A resulting value to pass to Unmap().\r
	207	\r
	208	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
	209	@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
	210	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	211	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	212	@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
	213	\r
8e7c9e03	214	**/\r
	215	EFI_STATUS\r
	216	EFIAPI\r
	217	DmaMap (\r
	218	IN DMA_MAP_OPERATION Operation,\r
7f814ffd	219	IN VOID *HostAddress,\r
	220	IN OUT UINTN *NumberOfBytes,\r
	221	OUT PHYSICAL_ADDRESS *DeviceAddress,\r
	222	OUT VOID **Mapping\r
8e7c9e03	223	)\r
	224	{\r
	225	EFI_STATUS Status;\r
	226	MAP_INFO_INSTANCE *Map;\r
	227	VOID *Buffer;\r
	228	\r
	229	if ( HostAddress == NULL \|\| NumberOfBytes == NULL \|\| \r
	230	DeviceAddress == NULL \|\| Mapping == NULL ) {\r
	231	return EFI_INVALID_PARAMETER;\r
	232	}\r
	233	\r
	234	\r
	235	if (Operation >= MapOperationMaximum) {\r
	236	return EFI_INVALID_PARAMETER;\r
	237	}\r
	238	\r
	239	*DeviceAddress = ConvertToPhysicalAddress (HostAddress);\r
	240	\r
	241	// Remember range so we can flush on the other side\r
	242	Map = AllocatePool (sizeof (MAP_INFO_INSTANCE));\r
	243	if (Map == NULL) {\r
	244	return EFI_OUT_OF_RESOURCES;\r
	245	}\r
	246	\r
	247	*Mapping = Map;\r
	248	\r
	249	if (((UINTN)HostAddress & (gCacheAlignment - 1)) != 0) {\r
	250	Map->DoubleBuffer = TRUE;\r
	251	Status = DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (*NumberOfBytes), &Buffer);\r
	252	if (EFI_ERROR (Status)) {\r
	253	return Status;\r
	254	}\r
	255	\r
	256	*DeviceAddress = (PHYSICAL_ADDRESS)(UINTN)Buffer;\r
	257	\r
	258	} else {\r
	259	Map->DoubleBuffer = FALSE;\r
	260	}\r
	261	\r
	262	NumberOfBytes &= NumberOfBytes & ~(gCacheAlignment - 1); // Only do it on full cache lines\r
	263	\r
	264	Map->HostAddress = (UINTN)HostAddress;\r
	265	Map->DeviceAddress = *DeviceAddress;\r
	266	Map->NumberOfBytes = *NumberOfBytes;\r
	267	Map->Operation = Operation;\r
	268	\r
	269	if (Map->DoubleBuffer) {\r
	270	if (Map->Operation == MapOperationBusMasterWrite) {\r
	271	CopyMem ((VOID )(UINTN)Map->DeviceAddress, (VOID )(UINTN)Map->HostAddress, Map->NumberOfBytes);\r
	272	}\r
	273	} else {\r
	274	// EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate\r
	275	if (Map->Operation == MapOperationBusMasterWrite \|\| Map->Operation == MapOperationBusMasterRead) {\r
	276	gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);\r
	277	}\r
	278	}\r
	279	\r
	280	return EFI_SUCCESS;\r
	281	}\r
	282	\r
	283	\r
7f814ffd	284	/** \r
	285	Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()\r
	286	operation and releases any corresponding resources.\r
	287	\r
	288	@param Mapping The mapping value returned from DmaMap*().\r
	289	\r
	290	@retval EFI_SUCCESS The range was unmapped.\r
	291	@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
	292	\r
8e7c9e03	293	**/\r
	294	EFI_STATUS\r
	295	EFIAPI\r
	296	DmaUnmap (\r
7f814ffd	297	IN VOID *Mapping\r
8e7c9e03	298	)\r
	299	{\r
	300	MAP_INFO_INSTANCE *Map;\r
	301	\r
	302	if (Mapping == NULL) {\r
	303	ASSERT (FALSE);\r
	304	return EFI_INVALID_PARAMETER;\r
	305	}\r
	306	\r
	307	Map = (MAP_INFO_INSTANCE *)Mapping;\r
	308	\r
	309	if (Map->DoubleBuffer) {\r
	310	if (Map->Operation == MapOperationBusMasterRead) {\r
	311	CopyMem ((VOID )(UINTN)Map->HostAddress, (VOID )(UINTN)Map->DeviceAddress, Map->NumberOfBytes);\r
	312	}\r
	313	\r
	314	DmaFreeBuffer (EFI_SIZE_TO_PAGES (Map->NumberOfBytes), (VOID *)(UINTN)Map->DeviceAddress);\r
	315	\r
	316	} else {\r
	317	if (Map->Operation == MapOperationBusMasterWrite) {\r
	318	//\r
	319	// Make sure we read buffer from uncached memory and not the cache\r
	320	//\r
	321	gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);\r
	322	}\r
	323	}\r
	324	\r
	325	FreePool (Map);\r
	326	\r
	327	return EFI_SUCCESS;\r
	328	}\r
	329	\r
7f814ffd	330	/** \r
	331	Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.\r
	332	mapping. \r
	333	\r
	334	@param MemoryType The type of memory to allocate, EfiBootServicesData or\r
	335	EfiRuntimeServicesData. \r
	336	@param Pages The number of pages to allocate. \r
	337	@param HostAddress A pointer to store the base system memory address of the\r
	338	allocated range. \r
	339	\r
	340	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	341	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
	342	MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
	343	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	344	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
	345	\r
8e7c9e03	346	**/\r
	347	EFI_STATUS\r
	348	EFIAPI\r
	349	DmaAllocateBuffer (\r
	350	IN EFI_MEMORY_TYPE MemoryType,\r
7f814ffd	351	IN UINTN Pages,\r
	352	OUT VOID **HostAddress\r
	353	)\r
8e7c9e03	354	{\r
	355	if (HostAddress == NULL) {\r
	356	return EFI_INVALID_PARAMETER;\r
	357	}\r
	358	\r
	359	//\r
	360	// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
	361	//\r
	362	// We used uncached memory to keep coherency\r
	363	//\r
	364	if (MemoryType == EfiBootServicesData) {\r
	365	*HostAddress = UncachedAllocatePages (Pages);\r
	366	} else if (MemoryType != EfiRuntimeServicesData) {\r
	367	*HostAddress = UncachedAllocateRuntimePages (Pages);\r
	368	} else {\r
	369	return EFI_INVALID_PARAMETER;\r
	370	}\r
	371	\r
	372	return EFI_SUCCESS;\r
	373	}\r
	374	\r
	375	\r
7f814ffd	376	/** \r
	377	Frees memory that was allocated with DmaAllocateBuffer().\r
	378	\r
	379	@param Pages The number of pages to free. \r
	380	@param HostAddress The base system memory address of the allocated range. \r
	381	\r
	382	@retval EFI_SUCCESS The requested memory pages were freed.\r
	383	@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
	384	was not allocated with DmaAllocateBuffer().\r
	385	\r
	386	**/\r
8e7c9e03	387	EFI_STATUS\r
	388	EFIAPI\r
	389	DmaFreeBuffer (\r
7f814ffd	390	IN UINTN Pages,\r
	391	IN VOID *HostAddress\r
	392	)\r
8e7c9e03	393	{\r
	394	if (HostAddress == NULL) {\r
	395	return EFI_INVALID_PARAMETER;\r
	396	} \r
	397	\r
	398	UncachedFreePages (HostAddress, Pages);\r
	399	return EFI_SUCCESS;\r
	400	}\r
	401	\r
	402	\r
	403	EFI_STATUS\r
	404	EFIAPI\r
	405	OmapDmaLibConstructor (\r
	406	IN EFI_HANDLE ImageHandle,\r
	407	IN EFI_SYSTEM_TABLE *SystemTable\r
	408	)\r
	409	{\r
	410	EFI_STATUS Status;\r
	411	\r
	412	// Get the Cpu protocol for later use\r
	413	Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);\r
	414	ASSERT_EFI_ERROR(Status);\r
	415	\r
	416	gCacheAlignment = ArmDataCacheLineLength ();\r
	417	\r
	418	return Status;\r
	419	}\r
	420	\r