SecurityPkg: Tcg2Dxe: Report correct FinalEventLog size
[mirror_edk2.git] / Omap35xxPkg / PciEmulation / PciRootBridgeIo.c
CommitLineData
a3f98646 1/** @file\r
2\r
3d70643b 3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
3402aac7 4\r
3d70643b 5 This program and the accompanying materials\r
a3f98646 6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "PciEmulation.h"\r
16\r
17BOOLEAN\r
18PciRootBridgeMemAddressValid (\r
19 IN PCI_ROOT_BRIDGE *Private,\r
20 IN UINT64 Address\r
21 )\r
22{\r
23 if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {\r
24 return TRUE;\r
25 }\r
26\r
27 return FALSE;\r
28}\r
29\r
30\r
31EFI_STATUS\r
32PciRootBridgeIoMemRW (\r
33 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
34 IN UINTN Count,\r
35 IN BOOLEAN InStrideFlag,\r
36 IN PTR In,\r
37 IN BOOLEAN OutStrideFlag,\r
38 OUT PTR Out\r
39 )\r
40{\r
41 UINTN Stride;\r
42 UINTN InStride;\r
43 UINTN OutStride;\r
44\r
45\r
46 Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
47 Stride = (UINTN)1 << Width;\r
48 InStride = InStrideFlag ? Stride : 0;\r
49 OutStride = OutStrideFlag ? Stride : 0;\r
50\r
51 //\r
52 // Loop for each iteration and move the data\r
53 //\r
54 switch (Width) {\r
55 case EfiPciWidthUint8:\r
56 for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {\r
57 *In.ui8 = *Out.ui8;\r
58 }\r
59 break;\r
60 case EfiPciWidthUint16:\r
61 for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {\r
62 *In.ui16 = *Out.ui16;\r
63 }\r
64 break;\r
65 case EfiPciWidthUint32:\r
66 for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {\r
67 *In.ui32 = *Out.ui32;\r
68 }\r
69 break;\r
70 default:\r
71 return EFI_INVALID_PARAMETER;\r
72 }\r
73\r
74 return EFI_SUCCESS;\r
75}\r
76\r
77EFI_STATUS\r
78PciRootBridgeIoPciRW (\r
79 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
80 IN BOOLEAN Write,\r
81 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
82 IN UINT64 UserAddress,\r
83 IN UINTN Count,\r
84 IN OUT VOID *UserBuffer\r
85 )\r
86{\r
87 return EFI_SUCCESS;\r
88}\r
89\r
3402aac7 90/**\r
a3f98646 91 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
3402aac7 92\r
a3f98646 93 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
94 @param Width Signifies the width of the memory operations.\r
3402aac7 95 @param Address The base address of the memory operations.\r
a3f98646 96 @param Count The number of memory operations to perform.\r
97 @param Buffer For read operations, the destination buffer to store the results. For write\r
3402aac7
RC
98 operations, the source buffer to write data from.\r
99\r
100 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
a3f98646 101 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
102 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
3402aac7 103\r
a3f98646 104**/\r
105EFI_STATUS\r
106EFIAPI\r
107PciRootBridgeIoMemRead (\r
108 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
109 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
110 IN UINT64 Address,\r
111 IN UINTN Count,\r
112 IN OUT VOID *Buffer\r
113 )\r
114{\r
115 PCI_ROOT_BRIDGE *Private;\r
116 UINTN AlignMask;\r
117 PTR In;\r
118 PTR Out;\r
119\r
120 if ( Buffer == NULL ) {\r
121 return EFI_INVALID_PARAMETER;\r
122 }\r
3402aac7 123\r
a3f98646 124 Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
125\r
126 if (!PciRootBridgeMemAddressValid (Private, Address)) {\r
127 return EFI_INVALID_PARAMETER;\r
128 }\r
129\r
130 AlignMask = (1 << (Width & 0x03)) - 1;\r
131 if (Address & AlignMask) {\r
132 return EFI_INVALID_PARAMETER;\r
133 }\r
134\r
135 In.buf = Buffer;\r
136 Out.buf = (VOID *)(UINTN) Address;\r
137\r
138 switch (Width) {\r
139 case EfiPciWidthUint8:\r
140 case EfiPciWidthUint16:\r
141 case EfiPciWidthUint32:\r
142 case EfiPciWidthUint64:\r
143 return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);\r
144\r
145 case EfiPciWidthFifoUint8:\r
146 case EfiPciWidthFifoUint16:\r
147 case EfiPciWidthFifoUint32:\r
148 case EfiPciWidthFifoUint64:\r
149 return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);\r
150\r
151 case EfiPciWidthFillUint8:\r
152 case EfiPciWidthFillUint16:\r
153 case EfiPciWidthFillUint32:\r
154 case EfiPciWidthFillUint64:\r
155 return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);\r
3402aac7 156\r
a3f98646 157 default:\r
158 break;\r
159 }\r
3402aac7 160\r
a3f98646 161 return EFI_INVALID_PARAMETER;\r
162}\r
163\r
164\r
165\r
3402aac7 166/**\r
a3f98646 167 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
3402aac7 168\r
a3f98646 169 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
170 @param Width Signifies the width of the memory operations.\r
3402aac7 171 @param Address The base address of the memory operations.\r
a3f98646 172 @param Count The number of memory operations to perform.\r
173 @param Buffer For read operations, the destination buffer to store the results. For write\r
3402aac7
RC
174 operations, the source buffer to write data from.\r
175\r
176 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
a3f98646 177 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
178 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
3402aac7 179\r
a3f98646 180**/\r
181EFI_STATUS\r
182EFIAPI\r
183PciRootBridgeIoMemWrite (\r
184 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
185 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
186 IN UINT64 Address,\r
187 IN UINTN Count,\r
188 IN OUT VOID *Buffer\r
189 )\r
190{\r
191 PCI_ROOT_BRIDGE *Private;\r
192 UINTN AlignMask;\r
193 PTR In;\r
194 PTR Out;\r
195\r
196 if ( Buffer == NULL ) {\r
197 return EFI_INVALID_PARAMETER;\r
198 }\r
3402aac7 199\r
a3f98646 200 Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
201\r
202 if (!PciRootBridgeMemAddressValid (Private, Address)) {\r
203 return EFI_INVALID_PARAMETER;\r
204 }\r
205\r
206 AlignMask = (1 << (Width & 0x03)) - 1;\r
207 if (Address & AlignMask) {\r
208 return EFI_INVALID_PARAMETER;\r
209 }\r
210\r
211 In.buf = (VOID *)(UINTN) Address;\r
212 Out.buf = Buffer;\r
213\r
214 switch (Width) {\r
215 case EfiPciWidthUint8:\r
216 case EfiPciWidthUint16:\r
217 case EfiPciWidthUint32:\r
218 case EfiPciWidthUint64:\r
219 return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);\r
3402aac7 220\r
a3f98646 221 case EfiPciWidthFifoUint8:\r
222 case EfiPciWidthFifoUint16:\r
223 case EfiPciWidthFifoUint32:\r
224 case EfiPciWidthFifoUint64:\r
225 return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);\r
226\r
227 case EfiPciWidthFillUint8:\r
228 case EfiPciWidthFillUint16:\r
229 case EfiPciWidthFillUint32:\r
230 case EfiPciWidthFillUint64:\r
231 return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);\r
3402aac7 232\r
a3f98646 233 default:\r
234 break;\r
235 }\r
236\r
237 return EFI_INVALID_PARAMETER;\r
238}\r
239\r
3402aac7 240/**\r
a3f98646 241 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
3402aac7 242\r
a3f98646 243 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
244 @param Width Signifies the width of the memory operations.\r
3402aac7 245 @param Address The base address of the memory operations.\r
a3f98646 246 @param Count The number of memory operations to perform.\r
247 @param Buffer For read operations, the destination buffer to store the results. For write\r
3402aac7
RC
248 operations, the source buffer to write data from.\r
249\r
250 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
a3f98646 251 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
252 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
3402aac7 253\r
a3f98646 254**/\r
255EFI_STATUS\r
256EFIAPI\r
257PciRootBridgeIoPciRead (\r
258 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
259 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
260 IN UINT64 Address,\r
261 IN UINTN Count,\r
262 IN OUT VOID *Buffer\r
263 )\r
264{\r
265 if (Buffer == NULL) {\r
266 return EFI_INVALID_PARAMETER;\r
267 }\r
268\r
269 return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
270}\r
271\r
272\r
273\r
3402aac7 274/**\r
a3f98646 275 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
3402aac7 276\r
a3f98646 277 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
278 @param Width Signifies the width of the memory operations.\r
3402aac7 279 @param Address The base address of the memory operations.\r
a3f98646 280 @param Count The number of memory operations to perform.\r
281 @param Buffer For read operations, the destination buffer to store the results. For write\r
3402aac7
RC
282 operations, the source buffer to write data from.\r
283\r
284 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
a3f98646 285 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
286 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
3402aac7 287\r
a3f98646 288**/\r
289EFI_STATUS\r
290EFIAPI\r
291PciRootBridgeIoPciWrite (\r
292 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
293 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
294 IN UINT64 Address,\r
295 IN UINTN Count,\r
296 IN OUT VOID *Buffer\r
297 )\r
298{\r
299 if (Buffer == NULL) {\r
300 return EFI_INVALID_PARAMETER;\r
301 }\r
3402aac7 302\r
a3f98646 303 return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
304}\r
305\r
306\r