OvmfPkg: SmmCpuFeaturesLib: customize state save map format
[mirror_edk2.git] / OvmfPkg / Include / Register / QemuSmramSaveStateMap.h
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1/** @file\r
2SMRAM Save State Map Definitions.\r
3\r
4SMRAM Save State Map definitions based on contents of the \r
5Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
6 Volume 3C, Section 34.4 SMRAM\r
7 Volume 3C, Section 34.5 SMI Handler Execution Environment\r
8 Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs\r
9\r
10and the AMD64 Architecture Programmer's Manual\r
11 Volume 2, Section 10.2 SMM Resources\r
12\r
13Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
14Copyright (c) 2015, Red Hat, Inc.<BR>\r
15This program and the accompanying materials\r
16are licensed and made available under the terms and conditions of the BSD License\r
17which accompanies this distribution. The full text of the license may be found at\r
18http://opensource.org/licenses/bsd-license.php\r
19\r
20THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
21WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
22\r
23**/\r
24\r
25#ifndef __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
26#define __QEMU_SMRAM_SAVE_STATE_MAP_H__\r
27\r
28#pragma pack (1)\r
29\r
30///\r
31/// 32-bit SMRAM Save State Map\r
32///\r
33typedef struct {\r
34 UINT8 Reserved0[0x200]; // 7c00h\r
35 UINT8 Reserved1[0xf8]; // 7e00h\r
36 UINT32 SMBASE; // 7ef8h\r
37 UINT32 SMMRevId; // 7efch\r
38 UINT16 IORestart; // 7f00h\r
39 UINT16 AutoHALTRestart; // 7f02h\r
40 UINT8 Reserved2[0x9C]; // 7f08h\r
41 UINT32 IOMemAddr; // 7fa0h\r
42 UINT32 IOMisc; // 7fa4h\r
43 UINT32 _ES; // 7fa8h\r
44 UINT32 _CS; // 7fach\r
45 UINT32 _SS; // 7fb0h\r
46 UINT32 _DS; // 7fb4h\r
47 UINT32 _FS; // 7fb8h\r
48 UINT32 _GS; // 7fbch\r
49 UINT32 Reserved3; // 7fc0h\r
50 UINT32 _TR; // 7fc4h\r
51 UINT32 _DR7; // 7fc8h\r
52 UINT32 _DR6; // 7fcch\r
53 UINT32 _EAX; // 7fd0h\r
54 UINT32 _ECX; // 7fd4h\r
55 UINT32 _EDX; // 7fd8h\r
56 UINT32 _EBX; // 7fdch\r
57 UINT32 _ESP; // 7fe0h\r
58 UINT32 _EBP; // 7fe4h\r
59 UINT32 _ESI; // 7fe8h\r
60 UINT32 _EDI; // 7fech\r
61 UINT32 _EIP; // 7ff0h\r
62 UINT32 _EFLAGS; // 7ff4h\r
63 UINT32 _CR3; // 7ff8h\r
64 UINT32 _CR0; // 7ffch\r
65} QEMU_SMRAM_SAVE_STATE_MAP32;\r
66\r
67///\r
68/// 64-bit SMRAM Save State Map\r
69///\r
70typedef struct {\r
71 UINT8 Reserved0[0x200]; // 7c00h\r
72\r
73 UINT16 _ES; // 7e00h\r
74 UINT16 _ESAccessRights; // 7e02h\r
75 UINT32 _ESLimit; // 7e04h\r
76 UINT64 _ESBase; // 7e08h\r
77\r
78 UINT16 _CS; // 7e10h\r
79 UINT16 _CSAccessRights; // 7e12h\r
80 UINT32 _CSLimit; // 7e14h\r
81 UINT64 _CSBase; // 7e18h\r
82\r
83 UINT16 _SS; // 7e20h\r
84 UINT16 _SSAccessRights; // 7e22h\r
85 UINT32 _SSLimit; // 7e24h\r
86 UINT64 _SSBase; // 7e28h\r
87\r
88 UINT16 _DS; // 7e30h\r
89 UINT16 _DSAccessRights; // 7e32h\r
90 UINT32 _DSLimit; // 7e34h\r
91 UINT64 _DSBase; // 7e38h\r
92\r
93 UINT16 _FS; // 7e40h\r
94 UINT16 _FSAccessRights; // 7e42h\r
95 UINT32 _FSLimit; // 7e44h\r
96 UINT64 _FSBase; // 7e48h\r
97\r
98 UINT16 _GS; // 7e50h\r
99 UINT16 _GSAccessRights; // 7e52h\r
100 UINT32 _GSLimit; // 7e54h\r
101 UINT64 _GSBase; // 7e58h\r
102\r
103 UINT32 _GDTRReserved1; // 7e60h\r
104 UINT16 _GDTRLimit; // 7e64h\r
105 UINT16 _GDTRReserved2; // 7e66h\r
106 UINT64 _GDTRBase; // 7e68h\r
107\r
108 UINT16 _LDTR; // 7e70h\r
109 UINT16 _LDTRAccessRights; // 7e72h\r
110 UINT32 _LDTRLimit; // 7e74h\r
111 UINT64 _LDTRBase; // 7e78h\r
112\r
113 UINT32 _IDTRReserved1; // 7e80h\r
114 UINT16 _IDTRLimit; // 7e84h\r
115 UINT16 _IDTRReserved2; // 7e86h\r
116 UINT64 _IDTRBase; // 7e88h\r
117\r
118 UINT16 _TR; // 7e90h\r
119 UINT16 _TRAccessRights; // 7e92h\r
120 UINT32 _TRLimit; // 7e94h\r
121 UINT64 _TRBase; // 7e98h\r
122\r
123 UINT64 IO_RIP; // 7ea0h\r
124 UINT64 IO_RCX; // 7ea8h\r
125 UINT64 IO_RSI; // 7eb0h\r
126 UINT64 IO_RDI; // 7eb8h\r
127 UINT32 IO_DWord; // 7ec0h\r
128 UINT8 Reserved1[0x04]; // 7ec4h\r
129 UINT8 IORestart; // 7ec8h\r
130 UINT8 AutoHALTRestart; // 7ec9h\r
131 UINT8 Reserved2[0x06]; // 7ecah\r
132\r
133 UINT64 IA32_EFER; // 7ed0h\r
134 UINT64 SVM_Guest; // 7ed8h\r
135 UINT64 SVM_GuestVMCB; // 7ee0h\r
136 UINT64 SVM_GuestVIntr; // 7ee8h\r
137 UINT8 Reserved3[0x0c]; // 7ef0h\r
138\r
139 UINT32 SMMRevId; // 7efch\r
140 UINT32 SMBASE; // 7f00h\r
141\r
142 UINT8 Reserved4[0x1c]; // 7f04h\r
143 UINT64 SVM_GuestPAT; // 7f20h\r
144 UINT64 SVM_HostIA32_EFER; // 7f28h\r
145 UINT64 SVM_HostCR4; // 7f30h\r
146 UINT64 SVM_HostCR3; // 7f38h\r
147 UINT64 SVM_HostCR0; // 7f40h\r
148\r
149 UINT64 _CR4; // 7f48h\r
150 UINT64 _CR3; // 7f50h\r
151 UINT64 _CR0; // 7f58h\r
152 UINT64 _DR7; // 7f60h\r
153 UINT64 _DR6; // 7f68h\r
154 UINT64 _RFLAGS; // 7f70h\r
155 UINT64 _RIP; // 7f78h\r
156 UINT64 _R15; // 7f80h\r
157 UINT64 _R14; // 7f88h\r
158 UINT64 _R13; // 7f90h\r
159 UINT64 _R12; // 7f98h\r
160 UINT64 _R11; // 7fa0h\r
161 UINT64 _R10; // 7fa8h\r
162 UINT64 _R9; // 7fb0h\r
163 UINT64 _R8; // 7fb8h\r
164 UINT64 _RDI; // 7fc0h\r
165 UINT64 _RSI; // 7fc8h\r
166 UINT64 _RBP; // 7fd0h\r
167 UINT64 _RSP; // 7fd8h\r
168 UINT64 _RBX; // 7fe0h\r
169 UINT64 _RDX; // 7fe8h\r
170 UINT64 _RCX; // 7ff0h\r
171 UINT64 _RAX; // 7ff8h\r
172} QEMU_SMRAM_SAVE_STATE_MAP64;\r
173\r
174///\r
175/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
176///\r
177typedef union {\r
178 QEMU_SMRAM_SAVE_STATE_MAP32 x86;\r
179 QEMU_SMRAM_SAVE_STATE_MAP64 x64;\r
180} QEMU_SMRAM_SAVE_STATE_MAP;\r
181\r
182#pragma pack ()\r
183\r
184#endif\r