[mirror_edk2.git] / OvmfPkg / Library / BaseMemEncryptSevLib / X64 / VirtualMemory.h

/** @file\r
\r
  Virtual Memory Management Services to set or clear the memory encryption bit\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
  This program and the accompanying materials are licensed and made available\r
  under the terms and conditions of the BSD License which accompanies this\r
  distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
  Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
\r
**/\r
\r
#ifndef __VIRTUAL_MEMORY__\r
#define __VIRTUAL_MEMORY__\r
\r
#include <Uefi.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
#include <Library/CacheMaintenanceLib.h>\r
#define SYS_CODE64_SEL 0x38\r
\r
#pragma pack(1)\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory,\r
                                      //   1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
                                      //   1 = Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed,\r
                                      //   1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 4KB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory,\r
                                      //   1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
                                      //   1 = Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed,\r
                                      //   1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
                                      //   processor on access to page\r
    UINT64  PAT:1;                    //\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
                                      //   TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code,\r
                                      //   1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory,\r
                                      //   1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
                                      //   1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed,\r
                                      //   1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
                                      //   processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
                                      //   TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code,\r
                                      //   1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory,\r
                                      //   1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching,\r
                                      //   1 = Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed,\r
                                      //   1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by\r
                                      //   processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page\r
                                      //   TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:17;            // Must be zero;\r
    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code,\r
                                      //   1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
#define IA32_PG_P                   BIT0\r
#define IA32_PG_RW                  BIT1\r
#define IA32_PG_PS                  BIT7\r
\r
#define PAGING_PAE_INDEX_MASK       0x1FF\r
\r
#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
\r
#define PAGING_L1_ADDRESS_SHIFT     12\r
#define PAGING_L2_ADDRESS_SHIFT     21\r
#define PAGING_L3_ADDRESS_SHIFT     30\r
#define PAGING_L4_ADDRESS_SHIFT     39\r
\r
#define PAGING_PML4E_NUMBER         4\r
\r
#define PAGETABLE_ENTRY_MASK        ((1UL << 9) - 1)\r
#define PML4_OFFSET(x)              ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
#define PDP_OFFSET(x)               ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
#define PDE_OFFSET(x)               ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
#define PTE_OFFSET(x)               ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
\r
#define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
#define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB\r
#define PAGE_TABLE_POOL_UNIT_PAGES  \\r
  EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
#define PAGE_TABLE_POOL_ALIGN_MASK  \\r
  (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
\r
typedef struct {\r
  VOID            *NextPool;\r
  UINTN           Offset;\r
  UINTN           FreePages;\r
} PAGE_TABLE_POOL;\r
\r
\r
\r
/**\r
  This function clears memory encryption bit for the memory region specified by\r
  PhysicalAddress and Length from the current page table context.\r
\r
  @param[in]  Cr3BaseAddress          Cr3 Base Address (if zero then use\r
                                      current CR3)\r
  @param[in]  PhysicalAddress         The physical address that is the start\r
                                      address of a memory region.\r
  @param[in]  Length                  The length of memory region\r
  @param[in]  Flush                   Flush the caches before applying the\r
                                      encryption mask\r
\r
  @retval RETURN_SUCCESS              The attributes were cleared for the\r
                                      memory region.\r
  @retval RETURN_INVALID_PARAMETER    Number of pages is zero.\r
  @retval RETURN_UNSUPPORTED          Clearing the memory encyrption attribute\r
                                      is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
InternalMemEncryptSevSetMemoryDecrypted (\r
  IN  PHYSICAL_ADDRESS        Cr3BaseAddress,\r
  IN  PHYSICAL_ADDRESS        PhysicalAddress,\r
  IN  UINTN                   Length,\r
  IN  BOOLEAN                 Flush\r
  );\r
\r
/**\r
  This function sets memory encryption bit for the memory region specified by\r
  PhysicalAddress and length from the current page table context.\r
\r
  @param[in]  PhysicalAddress         The physical address that is the start\r
                                      address of a memory region.\r
  @param[in]  Length                  The length of memory region\r
  @param[in]  Flush                   Flush the caches before applying the\r
                                      encryption mask\r
\r
  @retval RETURN_SUCCESS              The attributes were cleared for the\r
                                      memory region.\r
  @retval RETURN_INVALID_PARAMETER    Number of pages is zero.\r
  @retval RETURN_UNSUPPORTED          Setting the memory encyrption attribute\r
                                      is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
InternalMemEncryptSevSetMemoryEncrypted (\r
  IN  PHYSICAL_ADDRESS     Cr3BaseAddress,\r
  IN  PHYSICAL_ADDRESS     PhysicalAddress,\r
  IN  UINT64               Length,\r
  IN  BOOLEAN              CacheFlush\r
  );\r
\r
#endif\r
Commit	Line	Data
a1f22614 BS	1	/** @file\r
	2	\r
	3	Virtual Memory Management Services to set or clear the memory encryption bit\r
	4	\r
4bd6bf31 LE	5	Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
4bd6bf31 LE	6	Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
a1f22614	7	\r
4bd6bf31 LE	8	This program and the accompanying materials are licensed and made available\r
	9	under the terms and conditions of the BSD License which accompanies this\r
	10	distribution. The full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
a1f22614	12	\r
4bd6bf31 LE	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
4bd6bf31 LE	14	WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
a1f22614	15	\r
4bd6bf31	16	Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
a1f22614 BS	17	\r
	18	**/\r
	19	\r
	20	#ifndef __VIRTUAL_MEMORY__\r
	21	#define __VIRTUAL_MEMORY__\r
	22	\r
	23	#include <Uefi.h>\r
	24	#include <Library/BaseLib.h>\r
	25	#include <Library/BaseMemoryLib.h>\r
	26	#include <Library/DebugLib.h>\r
	27	#include <Library/MemoryAllocationLib.h>\r
	28	\r
	29	#include <Library/CacheMaintenanceLib.h>\r
	30	#define SYS_CODE64_SEL 0x38\r
	31	\r
	32	#pragma pack(1)\r
	33	\r
	34	//\r
	35	// Page-Map Level-4 Offset (PML4) and\r
	36	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	37	//\r
	38	\r
	39	typedef union {\r
	40	struct {\r
4bd6bf31 LE	41	UINT64 Present:1; // 0 = Not present in memory,\r
4bd6bf31 LE	42	// 1 = Present in memory\r
a1f22614 BS	43	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
a1f22614 BS	44	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
4bd6bf31 LE	45	UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
4bd6bf31 LE	46	// 1 = Write-Through caching\r
a1f22614	47	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
4bd6bf31 LE	48	UINT64 Accessed:1; // 0 = Not accessed,\r
4bd6bf31 LE	49	// 1 = Accessed (set by CPU)\r
a1f22614 BS	50	UINT64 Reserved:1; // Reserved\r
	51	UINT64 MustBeZero:2; // Must Be Zero\r
	52	UINT64 Available:3; // Available for use by system software\r
	53	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	54	UINT64 AvabilableHigh:11; // Available for use by system software\r
	55	UINT64 Nx:1; // No Execute bit\r
	56	} Bits;\r
	57	UINT64 Uint64;\r
	58	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	59	\r
	60	//\r
	61	// Page Table Entry 4KB\r
	62	//\r
	63	typedef union {\r
	64	struct {\r
4bd6bf31 LE	65	UINT64 Present:1; // 0 = Not present in memory,\r
4bd6bf31 LE	66	// 1 = Present in memory\r
a1f22614 BS	67	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
a1f22614 BS	68	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
4bd6bf31 LE	69	UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
4bd6bf31 LE	70	// 1 = Write-Through caching\r
a1f22614	71	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
4bd6bf31 LE	72	UINT64 Accessed:1; // 0 = Not accessed,\r
	73	// 1 = Accessed (set by CPU)\r
	74	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
	75	// processor on access to page\r
a1f22614	76	UINT64 PAT:1; //\r
4bd6bf31 LE	77	UINT64 Global:1; // 0 = Not global page, 1 = global page\r
4bd6bf31 LE	78	// TLB not cleared on CR3 write\r
a1f22614 BS	79	UINT64 Available:3; // Available for use by system software\r
	80	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	81	UINT64 AvabilableHigh:11; // Available for use by system software\r
4bd6bf31 LE	82	UINT64 Nx:1; // 0 = Execute Code,\r
4bd6bf31 LE	83	// 1 = No Code Execution\r
a1f22614 BS	84	} Bits;\r
	85	UINT64 Uint64;\r
	86	} PAGE_TABLE_4K_ENTRY;\r
	87	\r
	88	//\r
	89	// Page Table Entry 2MB\r
	90	//\r
	91	typedef union {\r
	92	struct {\r
4bd6bf31 LE	93	UINT64 Present:1; // 0 = Not present in memory,\r
4bd6bf31 LE	94	// 1 = Present in memory\r
a1f22614 BS	95	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
a1f22614 BS	96	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
4bd6bf31 LE	97	UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
4bd6bf31 LE	98	// 1=Write-Through caching\r
a1f22614	99	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
4bd6bf31 LE	100	UINT64 Accessed:1; // 0 = Not accessed,\r
	101	// 1 = Accessed (set by CPU)\r
	102	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
	103	// processor on access to page\r
a1f22614	104	UINT64 MustBe1:1; // Must be 1\r
4bd6bf31 LE	105	UINT64 Global:1; // 0 = Not global page, 1 = global page\r
4bd6bf31 LE	106	// TLB not cleared on CR3 write\r
a1f22614 BS	107	UINT64 Available:3; // Available for use by system software\r
	108	UINT64 PAT:1; //\r
	109	UINT64 MustBeZero:8; // Must be zero;\r
	110	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
	111	UINT64 AvabilableHigh:11; // Available for use by system software\r
4bd6bf31 LE	112	UINT64 Nx:1; // 0 = Execute Code,\r
4bd6bf31 LE	113	// 1 = No Code Execution\r
a1f22614 BS	114	} Bits;\r
	115	UINT64 Uint64;\r
	116	} PAGE_TABLE_ENTRY;\r
	117	\r
	118	//\r
	119	// Page Table Entry 1GB\r
	120	//\r
	121	typedef union {\r
	122	struct {\r
4bd6bf31 LE	123	UINT64 Present:1; // 0 = Not present in memory,\r
4bd6bf31 LE	124	// 1 = Present in memory\r
a1f22614 BS	125	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
a1f22614 BS	126	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
4bd6bf31 LE	127	UINT64 WriteThrough:1; // 0 = Write-Back caching,\r
4bd6bf31 LE	128	// 1 = Write-Through caching\r
a1f22614	129	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
4bd6bf31 LE	130	UINT64 Accessed:1; // 0 = Not accessed,\r
	131	// 1 = Accessed (set by CPU)\r
	132	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r
	133	// processor on access to page\r
a1f22614	134	UINT64 MustBe1:1; // Must be 1\r
4bd6bf31 LE	135	UINT64 Global:1; // 0 = Not global page, 1 = global page\r
4bd6bf31 LE	136	// TLB not cleared on CR3 write\r
a1f22614 BS	137	UINT64 Available:3; // Available for use by system software\r
	138	UINT64 PAT:1; //\r
	139	UINT64 MustBeZero:17; // Must be zero;\r
	140	UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
	141	UINT64 AvabilableHigh:11; // Available for use by system software\r
4bd6bf31 LE	142	UINT64 Nx:1; // 0 = Execute Code,\r
4bd6bf31 LE	143	// 1 = No Code Execution\r
a1f22614 BS	144	} Bits;\r
	145	UINT64 Uint64;\r
	146	} PAGE_TABLE_1G_ENTRY;\r
	147	\r
	148	#pragma pack()\r
	149	\r
	150	#define IA32_PG_P BIT0\r
	151	#define IA32_PG_RW BIT1\r
b721aa74 BS	152	#define IA32_PG_PS BIT7\r
	153	\r
	154	#define PAGING_PAE_INDEX_MASK 0x1FF\r
	155	\r
	156	#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
	157	#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
	158	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
	159	\r
	160	#define PAGING_L1_ADDRESS_SHIFT 12\r
	161	#define PAGING_L2_ADDRESS_SHIFT 21\r
	162	#define PAGING_L3_ADDRESS_SHIFT 30\r
	163	#define PAGING_L4_ADDRESS_SHIFT 39\r
	164	\r
	165	#define PAGING_PML4E_NUMBER 4\r
a1f22614 BS	166	\r
	167	#define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)\r
	168	#define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
	169	#define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
	170	#define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
	171	#define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
	172	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
	173	\r
b721aa74 BS	174	#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
b721aa74 BS	175	#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
4bd6bf31 LE	176	#define PAGE_TABLE_POOL_UNIT_PAGES \\r
4bd6bf31 LE	177	EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
b721aa74 BS	178	#define PAGE_TABLE_POOL_ALIGN_MASK \\r
	179	(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
	180	\r
	181	typedef struct {\r
	182	VOID *NextPool;\r
	183	UINTN Offset;\r
	184	UINTN FreePages;\r
	185	} PAGE_TABLE_POOL;\r
	186	\r
	187	\r
	188	\r
a1f22614	189	/**\r
4bd6bf31	190	This function clears memory encryption bit for the memory region specified by\r
1532e5d5	191	PhysicalAddress and Length from the current page table context.\r
a1f22614	192	\r
1532e5d5 LE	193	@param[in] Cr3BaseAddress Cr3 Base Address (if zero then use\r
1532e5d5 LE	194	current CR3)\r
4bd6bf31 LE	195	@param[in] PhysicalAddress The physical address that is the start\r
4bd6bf31 LE	196	address of a memory region.\r
a1f22614	197	@param[in] Length The length of memory region\r
4bd6bf31 LE	198	@param[in] Flush Flush the caches before applying the\r
4bd6bf31 LE	199	encryption mask\r
a1f22614	200	\r
4bd6bf31 LE	201	@retval RETURN_SUCCESS The attributes were cleared for the\r
4bd6bf31 LE	202	memory region.\r
a1f22614	203	@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
1532e5d5	204	@retval RETURN_UNSUPPORTED Clearing the memory encyrption attribute\r
4bd6bf31	205	is not supported\r
a1f22614 BS	206	**/\r
	207	RETURN_STATUS\r
	208	EFIAPI\r
	209	InternalMemEncryptSevSetMemoryDecrypted (\r
1532e5d5 LE	210	IN PHYSICAL_ADDRESS Cr3BaseAddress,\r
	211	IN PHYSICAL_ADDRESS PhysicalAddress,\r
	212	IN UINTN Length,\r
	213	IN BOOLEAN Flush\r
a1f22614 BS	214	);\r
	215	\r
	216	/**\r
	217	This function sets memory encryption bit for the memory region specified by\r
	218	PhysicalAddress and length from the current page table context.\r
	219	\r
4bd6bf31 LE	220	@param[in] PhysicalAddress The physical address that is the start\r
4bd6bf31 LE	221	address of a memory region.\r
a1f22614 BS	222	@param[in] Length The length of memory region\r
	223	@param[in] Flush Flush the caches before applying the\r
	224	encryption mask\r
	225	\r
4bd6bf31 LE	226	@retval RETURN_SUCCESS The attributes were cleared for the\r
4bd6bf31 LE	227	memory region.\r
a1f22614	228	@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
4bd6bf31 LE	229	@retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r
4bd6bf31 LE	230	is not supported\r
a1f22614 BS	231	**/\r
	232	RETURN_STATUS\r
	233	EFIAPI\r
	234	InternalMemEncryptSevSetMemoryEncrypted (\r
	235	IN PHYSICAL_ADDRESS Cr3BaseAddress,\r
	236	IN PHYSICAL_ADDRESS PhysicalAddress,\r
	237	IN UINT64 Length,\r
	238	IN BOOLEAN CacheFlush\r
	239	);\r
	240	\r
	241	#endif\r