[mirror_edk2.git] / OvmfPkg / Library / BaseMemEncryptSevLib / X64 / VirtualMemory.h

/** @file\r
\r
  Virtual Memory Management Services to set or clear the memory encryption bit\r
\r
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
\r
**/\r
\r
#ifndef __VIRTUAL_MEMORY__\r
#define __VIRTUAL_MEMORY__\r
\r
#include <Uefi.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
#include <Library/CacheMaintenanceLib.h>\r
#define SYS_CODE64_SEL 0x38\r
\r
#pragma pack(1)\r
\r
//\r
// Page-Map Level-4 Offset (PML4) and\r
// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
//\r
\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Reserved:1;               // Reserved\r
    UINT64  MustBeZero:2;             // Must Be Zero\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // No Execute bit\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_MAP_AND_DIRECTORY_POINTER;\r
\r
//\r
// Page Table Entry 4KB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  PAT:1;                    //\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_4K_ENTRY;\r
\r
//\r
// Page Table Entry 2MB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:8;             // Must be zero;\r
    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_ENTRY;\r
\r
//\r
// Page Table Entry 1GB\r
//\r
typedef union {\r
  struct {\r
    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
    UINT64  MustBe1:1;                // Must be 1\r
    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
    UINT64  Available:3;              // Available for use by system software\r
    UINT64  PAT:1;                    //\r
    UINT64  MustBeZero:17;            // Must be zero;\r
    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
    UINT64  AvabilableHigh:11;        // Available for use by system software\r
    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
  } Bits;\r
  UINT64    Uint64;\r
} PAGE_TABLE_1G_ENTRY;\r
\r
#pragma pack()\r
\r
#define IA32_PG_P                   BIT0\r
#define IA32_PG_RW                  BIT1\r
#define IA32_PG_PS                  BIT7\r
\r
#define PAGING_PAE_INDEX_MASK       0x1FF\r
\r
#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
\r
#define PAGING_L1_ADDRESS_SHIFT     12\r
#define PAGING_L2_ADDRESS_SHIFT     21\r
#define PAGING_L3_ADDRESS_SHIFT     30\r
#define PAGING_L4_ADDRESS_SHIFT     39\r
\r
#define PAGING_PML4E_NUMBER         4\r
\r
#define PAGETABLE_ENTRY_MASK        ((1UL << 9) - 1)\r
#define PML4_OFFSET(x)              ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
#define PDP_OFFSET(x)               ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
#define PDE_OFFSET(x)               ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
#define PTE_OFFSET(x)               ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
\r
#define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
#define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB\r
#define PAGE_TABLE_POOL_UNIT_PAGES  EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
#define PAGE_TABLE_POOL_ALIGN_MASK  \\r
  (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
\r
typedef struct {\r
  VOID            *NextPool;\r
  UINTN           Offset;\r
  UINTN           FreePages;\r
} PAGE_TABLE_POOL;\r
\r
\r
\r
/**\r
  This function clears memory encryption bit for the memory region specified by PhysicalAddress\r
  and length from the current page table context.\r
\r
  @param[in]  PhysicalAddress         The physical address that is the start address of a memory region.\r
  @param[in]  Length                  The length of memory region\r
  @param[in]  Flush                   Flush the caches before applying the encryption mask\r
\r
  @retval RETURN_SUCCESS              The attributes were cleared for the memory region.\r
  @retval RETURN_INVALID_PARAMETER    Number of pages is zero.\r
  @retval RETURN_UNSUPPORTED          Setting the memory encyrption attribute is not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
InternalMemEncryptSevSetMemoryDecrypted (\r
  IN  PHYSICAL_ADDRESS     Cr3BaseAddress,\r
  IN  PHYSICAL_ADDRESS     PhysicalAddress,\r
  IN  UINT64               Length,\r
  IN  BOOLEAN              CacheFlush\r
  );\r
\r
/**\r
  This function sets memory encryption bit for the memory region specified by\r
  PhysicalAddress and length from the current page table context.\r
\r
  @param[in]  PhysicalAddress         The physical address that is the start address\r
                                      of a memory region.\r
  @param[in]  Length                  The length of memory region\r
  @param[in]  Flush                   Flush the caches before applying the\r
                                      encryption mask\r
\r
  @retval RETURN_SUCCESS              The attributes were cleared for the memory region.\r
  @retval RETURN_INVALID_PARAMETER    Number of pages is zero.\r
  @retval RETURN_UNSUPPORTED          Setting the memory encyrption attribute is\r
                                      not supported\r
**/\r
RETURN_STATUS\r
EFIAPI\r
InternalMemEncryptSevSetMemoryEncrypted (\r
  IN  PHYSICAL_ADDRESS     Cr3BaseAddress,\r
  IN  PHYSICAL_ADDRESS     PhysicalAddress,\r
  IN  UINT64               Length,\r
  IN  BOOLEAN              CacheFlush\r
  );\r
\r
#endif\r
Commit	Line	Data
a1f22614 BS	1	/** @file\r
	2	\r
	3	Virtual Memory Management Services to set or clear the memory encryption bit\r
	4	\r
	5	Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
	6	Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
	7	\r
	8	This program and the accompanying materials\r
	9	are licensed and made available under the terms and conditions of the BSD License\r
	10	which accompanies this distribution. The full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r
	17	\r
	18	**/\r
	19	\r
	20	#ifndef __VIRTUAL_MEMORY__\r
	21	#define __VIRTUAL_MEMORY__\r
	22	\r
	23	#include <Uefi.h>\r
	24	#include <Library/BaseLib.h>\r
	25	#include <Library/BaseMemoryLib.h>\r
	26	#include <Library/DebugLib.h>\r
	27	#include <Library/MemoryAllocationLib.h>\r
	28	\r
	29	#include <Library/CacheMaintenanceLib.h>\r
	30	#define SYS_CODE64_SEL 0x38\r
	31	\r
	32	#pragma pack(1)\r
	33	\r
	34	//\r
	35	// Page-Map Level-4 Offset (PML4) and\r
	36	// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
	37	//\r
	38	\r
	39	typedef union {\r
	40	struct {\r
	41	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	42	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	43	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
	44	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
	45	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
	46	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
	47	UINT64 Reserved:1; // Reserved\r
	48	UINT64 MustBeZero:2; // Must Be Zero\r
	49	UINT64 Available:3; // Available for use by system software\r
	50	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
	51	UINT64 AvabilableHigh:11; // Available for use by system software\r
	52	UINT64 Nx:1; // No Execute bit\r
	53	} Bits;\r
	54	UINT64 Uint64;\r
	55	} PAGE_MAP_AND_DIRECTORY_POINTER;\r
	56	\r
	57	//\r
	58	// Page Table Entry 4KB\r
	59	//\r
	60	typedef union {\r
	61	struct {\r
	62	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
	63	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
	64	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
65	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
66	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
67	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
68	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
69	UINT64 PAT:1; //\r
70	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
71	UINT64 Available:3; // Available for use by system software\r
72	UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
73	UINT64 AvabilableHigh:11; // Available for use by system software\r
74	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
75	} Bits;\r
76	UINT64 Uint64;\r
77	} PAGE_TABLE_4K_ENTRY;\r
78	\r
79	//\r
80	// Page Table Entry 2MB\r
81	//\r
82	typedef union {\r
83	struct {\r
84	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
85	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
86	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
87	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
88	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
89	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
90	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
91	UINT64 MustBe1:1; // Must be 1\r
92	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
93	UINT64 Available:3; // Available for use by system software\r
94	UINT64 PAT:1; //\r
95	UINT64 MustBeZero:8; // Must be zero;\r
96	UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
97	UINT64 AvabilableHigh:11; // Available for use by system software\r
98	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
99	} Bits;\r
100	UINT64 Uint64;\r
101	} PAGE_TABLE_ENTRY;\r
102	\r
103	//\r
104	// Page Table Entry 1GB\r
105	//\r
106	typedef union {\r
107	struct {\r
108	UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
109	UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
110	UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
111	UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
112	UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
113	UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
114	UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
115	UINT64 MustBe1:1; // Must be 1\r
116	UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
117	UINT64 Available:3; // Available for use by system software\r
118	UINT64 PAT:1; //\r
119	UINT64 MustBeZero:17; // Must be zero;\r
120	UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
121	UINT64 AvabilableHigh:11; // Available for use by system software\r
122	UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
123	} Bits;\r
124	UINT64 Uint64;\r
125	} PAGE_TABLE_1G_ENTRY;\r
126	\r
127	#pragma pack()\r
128	\r
129	#define IA32_PG_P BIT0\r
130	#define IA32_PG_RW BIT1\r
b721aa74 BS	131	#define IA32_PG_PS BIT7\r
	132	\r
	133	#define PAGING_PAE_INDEX_MASK 0x1FF\r
	134	\r
	135	#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
	136	#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
	137	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
	138	\r
	139	#define PAGING_L1_ADDRESS_SHIFT 12\r
	140	#define PAGING_L2_ADDRESS_SHIFT 21\r
	141	#define PAGING_L3_ADDRESS_SHIFT 30\r
	142	#define PAGING_L4_ADDRESS_SHIFT 39\r
	143	\r
	144	#define PAGING_PML4E_NUMBER 4\r
a1f22614 BS	145	\r
	146	#define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)\r
	147	#define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r
	148	#define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r
	149	#define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r
	150	#define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r
	151	#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
	152	\r
b721aa74 BS	153	#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
	154	#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
	155	#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
	156	#define PAGE_TABLE_POOL_ALIGN_MASK \\r
	157	(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
	158	\r
	159	typedef struct {\r
	160	VOID *NextPool;\r
	161	UINTN Offset;\r
	162	UINTN FreePages;\r
	163	} PAGE_TABLE_POOL;\r
	164	\r
	165	\r
	166	\r
a1f22614 BS	167	/**\r
	168	This function clears memory encryption bit for the memory region specified by PhysicalAddress\r
	169	and length from the current page table context.\r
	170	\r
	171	@param[in] PhysicalAddress The physical address that is the start address of a memory region.\r
	172	@param[in] Length The length of memory region\r
	173	@param[in] Flush Flush the caches before applying the encryption mask\r
	174	\r
	175	@retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
	176	@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
	177	@retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is not supported\r
	178	**/\r
	179	RETURN_STATUS\r
	180	EFIAPI\r
	181	InternalMemEncryptSevSetMemoryDecrypted (\r
	182	IN PHYSICAL_ADDRESS Cr3BaseAddress,\r
	183	IN PHYSICAL_ADDRESS PhysicalAddress,\r
	184	IN UINT64 Length,\r
	185	IN BOOLEAN CacheFlush\r
	186	);\r
	187	\r
	188	/**\r
	189	This function sets memory encryption bit for the memory region specified by\r
	190	PhysicalAddress and length from the current page table context.\r
	191	\r
	192	@param[in] PhysicalAddress The physical address that is the start address\r
	193	of a memory region.\r
	194	@param[in] Length The length of memory region\r
	195	@param[in] Flush Flush the caches before applying the\r
	196	encryption mask\r
	197	\r
	198	@retval RETURN_SUCCESS The attributes were cleared for the memory region.\r
	199	@retval RETURN_INVALID_PARAMETER Number of pages is zero.\r
	200	@retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is\r
	201	not supported\r
	202	**/\r
	203	RETURN_STATUS\r
	204	EFIAPI\r
	205	InternalMemEncryptSevSetMemoryEncrypted (\r
	206	IN PHYSICAL_ADDRESS Cr3BaseAddress,\r
	207	IN PHYSICAL_ADDRESS PhysicalAddress,\r
	208	IN UINT64 Length,\r
	209	IN BOOLEAN CacheFlush\r
	210	);\r
	211	\r
	212	#endif\r