[mirror_edk2.git] / OvmfPkg / Library / PciHostBridgeLib / PciHostBridgeLib.c

/** @file\r
  OVMF's instance of the PCI Host Bridge Library.\r
\r
  Copyright (C) 2016, Red Hat, Inc.\r
  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
\r
  This program and the accompanying materials are licensed and made available\r
  under the terms and conditions of the BSD License which accompanies this\r
  distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#include <PiDxe.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PciHostBridgeLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
\r
\r
#pragma pack(1)\r
typedef struct {\r
  ACPI_HID_DEVICE_PATH     AcpiDevicePath;\r
  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
} OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
#pragma pack ()\r
\r
\r
GLOBAL_REMOVE_IF_UNREFERENCED\r
CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {\r
  L"Mem", L"I/O", L"Bus"\r
};\r
\r
\r
STATIC\r
CONST\r
OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {\r
  {\r
    {\r
      ACPI_DEVICE_PATH,\r
      ACPI_DP,\r
      {\r
        (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
        (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
      }\r
    },\r
    EISA_PNP_ID(0x0A03), // HID\r
    0                    // UID\r
  },\r
\r
  {\r
    END_DEVICE_PATH_TYPE,\r
    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
    {\r
      END_DEVICE_PATH_LENGTH,\r
      0\r
    }\r
  }\r
};\r
\r
\r
/**\r
  Initialize a PCI_ROOT_BRIDGE structure.\r
\r
  param[in]  RootBusNumber     The bus number to store in RootBus.\r
\r
  param[in]  MaxSubBusNumber   The inclusive maximum bus number that can be\r
                               assigned to any subordinate bus found behind any\r
                               PCI bridge hanging off this root bus.\r
\r
                               The caller is repsonsible for ensuring that\r
                               RootBusNumber <= MaxSubBusNumber. If\r
                               RootBusNumber equals MaxSubBusNumber, then the\r
                               root bus has no room for subordinate buses.\r
\r
  param[out] RootBus           The PCI_ROOT_BRIDGE structure (allocated by the\r
                               caller) that should be filled in by this\r
                               function.\r
\r
  @retval EFI_SUCCESS           Initialization successful. A device path\r
                                consisting of an ACPI device path node, with\r
                                UID = RootBusNumber, has been allocated and\r
                                linked into RootBus.\r
\r
  @retval EFI_OUT_OF_RESOURCES  Memory allocation failed.\r
**/\r
STATIC\r
EFI_STATUS\r
InitRootBridge (\r
  IN  UINT8           RootBusNumber,\r
  IN  UINT8           MaxSubBusNumber,\r
  OUT PCI_ROOT_BRIDGE *RootBus\r
  )\r
{\r
  OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
\r
  //\r
  // Be safe if other fields are added to PCI_ROOT_BRIDGE later.\r
  //\r
  ZeroMem (RootBus, sizeof *RootBus);\r
\r
  RootBus->Segment = 0;\r
\r
  RootBus->Supports   = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
                        EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
                        EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
                        EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
                        EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
                        EFI_PCI_ATTRIBUTE_VGA_IO_16  |\r
                        EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
  RootBus->Attributes = RootBus->Supports;\r
\r
  RootBus->DmaAbove4G = FALSE;\r
\r
  RootBus->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
  RootBus->PMem.Base            = MAX_UINT64;\r
  RootBus->PMem.Limit           = 0;\r
  RootBus->PMemAbove4G.Base     = MAX_UINT64;\r
  RootBus->PMemAbove4G.Limit    = 0;\r
  RootBus->MemAbove4G.Base      = MAX_UINT64;\r
  RootBus->MemAbove4G.Limit     = 0;\r
\r
  if (PcdGet64 (PcdPciMmio64Size) > 0) {\r
    RootBus->AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
    RootBus->MemAbove4G.Base       = PcdGet64 (PcdPciMmio64Base);\r
    RootBus->MemAbove4G.Limit      = PcdGet64 (PcdPciMmio64Base) +\r
                                     (PcdGet64 (PcdPciMmio64Size) - 1);\r
  }\r
\r
  RootBus->Bus.Base  = RootBusNumber;\r
  RootBus->Bus.Limit = MaxSubBusNumber;\r
  RootBus->Io.Base   = PcdGet64 (PcdPciIoBase);\r
  RootBus->Io.Limit  = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
  RootBus->Mem.Base  = PcdGet64 (PcdPciMmio32Base);\r
  RootBus->Mem.Limit = PcdGet64 (PcdPciMmio32Base) +\r
                       (PcdGet64 (PcdPciMmio32Size) - 1);\r
\r
  RootBus->NoExtendedConfigSpace = (PcdGet16 (PcdOvmfHostBridgePciDevId) !=\r
                                    INTEL_Q35_MCH_DEVICE_ID);\r
\r
  DevicePath = AllocateCopyPool (sizeof mRootBridgeDevicePathTemplate,\r
                 &mRootBridgeDevicePathTemplate);\r
  if (DevicePath == NULL) {\r
    DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
  DevicePath->AcpiDevicePath.UID = RootBusNumber;\r
  RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
\r
  DEBUG ((EFI_D_INFO,\r
    "%a: populated root bus %d, with room for %d subordinate bus(es)\n",\r
    __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  Uninitialize a PCI_ROOT_BRIDGE structure set up with InitRootBridge().\r
\r
  param[in] RootBus  The PCI_ROOT_BRIDGE structure, allocated by the caller and\r
                     initialized with InitRootBridge(), that should be\r
                     uninitialized. This function doesn't free RootBus.\r
**/\r
STATIC\r
VOID\r
UninitRootBridge (\r
  IN PCI_ROOT_BRIDGE *RootBus\r
  )\r
{\r
  FreePool (RootBus->DevicePath);\r
}\r
\r
\r
/**\r
  Return all the root bridge instances in an array.\r
\r
  @param Count  Return the count of root bridge instances.\r
\r
  @return All the root bridge instances in an array.\r
          The array should be passed into PciHostBridgeFreeRootBridges()\r
          when it's not used.\r
**/\r
PCI_ROOT_BRIDGE *\r
EFIAPI\r
PciHostBridgeGetRootBridges (\r
  UINTN *Count\r
  )\r
{\r
  EFI_STATUS           Status;\r
  FIRMWARE_CONFIG_ITEM FwCfgItem;\r
  UINTN                FwCfgSize;\r
  UINT64               ExtraRootBridges;\r
  PCI_ROOT_BRIDGE      *Bridges;\r
  UINTN                Initialized;\r
  UINTN                LastRootBridgeNumber;\r
  UINTN                RootBridgeNumber;\r
\r
  *Count = 0;\r
\r
  //\r
  // QEMU provides the number of extra root buses, shortening the exhaustive\r
  // search below. If there is no hint, the feature is missing.\r
  //\r
  Status = QemuFwCfgFindFile ("etc/extra-pci-roots", &FwCfgItem, &FwCfgSize);\r
  if (EFI_ERROR (Status) || FwCfgSize != sizeof ExtraRootBridges) {\r
    ExtraRootBridges = 0;\r
  } else {\r
    QemuFwCfgSelectItem (FwCfgItem);\r
    QemuFwCfgReadBytes (FwCfgSize, &ExtraRootBridges);\r
\r
    if (ExtraRootBridges > PCI_MAX_BUS) {\r
      DEBUG ((EFI_D_ERROR, "%a: invalid count of extra root buses (%Lu) "\r
        "reported by QEMU\n", __FUNCTION__, ExtraRootBridges));\r
      return NULL;\r
    }\r
    DEBUG ((EFI_D_INFO, "%a: %Lu extra root buses reported by QEMU\n",\r
      __FUNCTION__, ExtraRootBridges));\r
  }\r
\r
  //\r
  // Allocate the "main" root bridge, and any extra root bridges.\r
  //\r
  Bridges = AllocatePool ((1 + (UINTN)ExtraRootBridges) * sizeof *Bridges);\r
  if (Bridges == NULL) {\r
    DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
    return NULL;\r
  }\r
  Initialized = 0;\r
\r
  //\r
  // The "main" root bus is always there.\r
  //\r
  LastRootBridgeNumber = 0;\r
\r
  //\r
  // Scan all other root buses. If function 0 of any device on a bus returns a\r
  // VendorId register value different from all-bits-one, then that bus is\r
  // alive.\r
  //\r
  for (RootBridgeNumber = 1;\r
       RootBridgeNumber <= PCI_MAX_BUS && Initialized < ExtraRootBridges;\r
       ++RootBridgeNumber) {\r
    UINTN Device;\r
\r
    for (Device = 0; Device <= PCI_MAX_DEVICE; ++Device) {\r
      if (PciRead16 (PCI_LIB_ADDRESS (RootBridgeNumber, Device, 0,\r
                       PCI_VENDOR_ID_OFFSET)) != MAX_UINT16) {\r
        break;\r
      }\r
    }\r
    if (Device <= PCI_MAX_DEVICE) {\r
      //\r
      // Found the next root bus. We can now install the *previous* one,\r
      // because now we know how big a bus number range *that* one has, for any\r
      // subordinate buses that might exist behind PCI bridges hanging off it.\r
      //\r
      Status = InitRootBridge ((UINT8)LastRootBridgeNumber,\r
                 (UINT8)(RootBridgeNumber - 1), &Bridges[Initialized]);\r
      if (EFI_ERROR (Status)) {\r
        goto FreeBridges;\r
      }\r
      ++Initialized;\r
      LastRootBridgeNumber = RootBridgeNumber;\r
    }\r
  }\r
\r
  //\r
  // Install the last root bus (which might be the only, ie. main, root bus, if\r
  // we've found no extra root buses).\r
  //\r
  Status = InitRootBridge ((UINT8)LastRootBridgeNumber, PCI_MAX_BUS,\r
             &Bridges[Initialized]);\r
  if (EFI_ERROR (Status)) {\r
    goto FreeBridges;\r
  }\r
  ++Initialized;\r
\r
  *Count = Initialized;\r
  return Bridges;\r
\r
FreeBridges:\r
  while (Initialized > 0) {\r
    --Initialized;\r
    UninitRootBridge (&Bridges[Initialized]);\r
  }\r
\r
  FreePool (Bridges);\r
  return NULL;\r
}\r
\r
\r
/**\r
  Free the root bridge instances array returned from\r
  PciHostBridgeGetRootBridges().\r
\r
  @param  The root bridge instances array.\r
  @param  The count of the array.\r
**/\r
VOID\r
EFIAPI\r
PciHostBridgeFreeRootBridges (\r
  PCI_ROOT_BRIDGE *Bridges,\r
  UINTN           Count\r
  )\r
{\r
  if (Bridges == NULL && Count == 0) {\r
    return;\r
  }\r
  ASSERT (Bridges != NULL && Count > 0);\r
\r
  do {\r
    --Count;\r
    UninitRootBridge (&Bridges[Count]);\r
  } while (Count > 0);\r
\r
  FreePool (Bridges);\r
}\r
\r
\r
/**\r
  Inform the platform that the resource conflict happens.\r
\r
  @param HostBridgeHandle Handle of the Host Bridge.\r
  @param Configuration    Pointer to PCI I/O and PCI memory resource\r
                          descriptors. The Configuration contains the resources\r
                          for all the root bridges. The resource for each root\r
                          bridge is terminated with END descriptor and an\r
                          additional END is appended indicating the end of the\r
                          entire resources. The resource descriptor field\r
                          values follow the description in\r
                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
                          .SubmitResources().\r
**/\r
VOID\r
EFIAPI\r
PciHostBridgeResourceConflict (\r
  EFI_HANDLE                        HostBridgeHandle,\r
  VOID                              *Configuration\r
  )\r
{\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
  UINTN                             RootBridgeIndex;\r
  DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));\r
\r
  RootBridgeIndex = 0;\r
  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
    DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));\r
    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {\r
      ASSERT (Descriptor->ResType <\r
              (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /\r
               sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])\r
               )\r
              );\r
      DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",\r
              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],\r
              Descriptor->AddrLen, Descriptor->AddrRangeMax\r
              ));\r
      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
        DEBUG ((EFI_D_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",\r
                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,\r
                ((Descriptor->SpecificFlag &\r
                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE\r
                  ) != 0) ? L" (Prefetchable)" : L""\r
                ));\r
      }\r
    }\r
    //\r
    // Skip the END descriptor for root bridge\r
    //\r
    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);\r
    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(\r
                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1\r
                   );\r
  }\r
}\r
Commit	Line	Data
d85861d7 LE	1	/** @file\r
	2	OVMF's instance of the PCI Host Bridge Library.\r
	3	\r
	4	Copyright (C) 2016, Red Hat, Inc.\r
	5	Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
	6	\r
	7	This program and the accompanying materials are licensed and made available\r
	8	under the terms and conditions of the BSD License which accompanies this\r
	9	distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php.\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
	13	WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	#include <PiDxe.h>\r
46e46eaf LE	17	\r
46e46eaf LE	18	#include <IndustryStandard/Pci.h>\r
7daf2401	19	#include <IndustryStandard/Q35MchIch9.h>\r
46e46eaf	20	\r
0dcd1b1b	21	#include <Protocol/PciHostBridgeResourceAllocation.h>\r
a5ece62d LE	22	#include <Protocol/PciRootBridgeIo.h>\r
a5ece62d LE	23	\r
65de2ef5	24	#include <Library/BaseMemoryLib.h>\r
d85861d7	25	#include <Library/DebugLib.h>\r
1f4e2299	26	#include <Library/DevicePathLib.h>\r
46e46eaf LE	27	#include <Library/MemoryAllocationLib.h>\r
	28	#include <Library/PciHostBridgeLib.h>\r
	29	#include <Library/PciLib.h>\r
	30	#include <Library/QemuFwCfgLib.h>\r
	31	\r
d85861d7	32	\r
1f4e2299 LE	33	#pragma pack(1)\r
	34	typedef struct {\r
	35	ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
	36	EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
	37	} OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
	38	#pragma pack ()\r
	39	\r
	40	\r
d85861d7 LE	41	GLOBAL_REMOVE_IF_UNREFERENCED\r
	42	CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {\r
	43	L"Mem", L"I/O", L"Bus"\r
	44	};\r
	45	\r
46e46eaf	46	\r
1f4e2299 LE	47	STATIC\r
	48	CONST\r
	49	OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {\r
	50	{\r
	51	{\r
	52	ACPI_DEVICE_PATH,\r
	53	ACPI_DP,\r
	54	{\r
	55	(UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
	56	(UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
	57	}\r
	58	},\r
	59	EISA_PNP_ID(0x0A03), // HID\r
	60	0 // UID\r
	61	},\r
	62	\r
	63	{\r
	64	END_DEVICE_PATH_TYPE,\r
	65	END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
	66	{\r
	67	END_DEVICE_PATH_LENGTH,\r
	68	0\r
	69	}\r
	70	}\r
	71	};\r
	72	\r
	73	\r
46e46eaf LE	74	/**\r
	75	Initialize a PCI_ROOT_BRIDGE structure.\r
	76	\r
	77	param[in] RootBusNumber The bus number to store in RootBus.\r
	78	\r
	79	param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
	80	assigned to any subordinate bus found behind any\r
	81	PCI bridge hanging off this root bus.\r
	82	\r
	83	The caller is repsonsible for ensuring that\r
	84	RootBusNumber <= MaxSubBusNumber. If\r
	85	RootBusNumber equals MaxSubBusNumber, then the\r
	86	root bus has no room for subordinate buses.\r
	87	\r
	88	param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
	89	caller) that should be filled in by this\r
	90	function.\r
	91	\r
	92	@retval EFI_SUCCESS Initialization successful. A device path\r
	93	consisting of an ACPI device path node, with\r
	94	UID = RootBusNumber, has been allocated and\r
	95	linked into RootBus.\r
	96	\r
	97	@retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
	98	**/\r
	99	STATIC\r
	100	EFI_STATUS\r
	101	InitRootBridge (\r
	102	IN UINT8 RootBusNumber,\r
	103	IN UINT8 MaxSubBusNumber,\r
	104	OUT PCI_ROOT_BRIDGE *RootBus\r
	105	)\r
	106	{\r
1f4e2299 LE	107	OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
1f4e2299 LE	108	\r
65de2ef5 LE	109	//\r
	110	// Be safe if other fields are added to PCI_ROOT_BRIDGE later.\r
	111	//\r
	112	ZeroMem (RootBus, sizeof *RootBus);\r
	113	\r
	114	RootBus->Segment = 0;\r
	115	\r
a5ece62d LE	116	RootBus->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO \|\r
	117	EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO \|\r
	118	EFI_PCI_ATTRIBUTE_ISA_IO_16 \|\r
	119	EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO \|\r
	120	EFI_PCI_ATTRIBUTE_VGA_MEMORY \|\r
	121	EFI_PCI_ATTRIBUTE_VGA_IO_16 \|\r
	122	EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
	123	RootBus->Attributes = RootBus->Supports;\r
	124	\r
c789d61d LE	125	RootBus->DmaAbove4G = FALSE;\r
c789d61d LE	126	\r
0dcd1b1b	127	RootBus->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
c3933ccb	128	RootBus->PMem.Base = MAX_UINT64;\r
0dcd1b1b	129	RootBus->PMem.Limit = 0;\r
c3933ccb	130	RootBus->PMemAbove4G.Base = MAX_UINT64;\r
0dcd1b1b	131	RootBus->PMemAbove4G.Limit = 0;\r
c3933ccb	132	RootBus->MemAbove4G.Base = MAX_UINT64;\r
0dcd1b1b LE	133	RootBus->MemAbove4G.Limit = 0;\r
0dcd1b1b LE	134	\r
4f5eff81 LE	135	if (PcdGet64 (PcdPciMmio64Size) > 0) {\r
	136	RootBus->AllocationAttributes \|= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
	137	RootBus->MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r
	138	RootBus->MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r
	139	(PcdGet64 (PcdPciMmio64Size) - 1);\r
	140	}\r
	141	\r
390951c2 LE	142	RootBus->Bus.Base = RootBusNumber;\r
	143	RootBus->Bus.Limit = MaxSubBusNumber;\r
	144	RootBus->Io.Base = PcdGet64 (PcdPciIoBase);\r
	145	RootBus->Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
	146	RootBus->Mem.Base = PcdGet64 (PcdPciMmio32Base);\r
	147	RootBus->Mem.Limit = PcdGet64 (PcdPciMmio32Base) +\r
	148	(PcdGet64 (PcdPciMmio32Size) - 1);\r
	149	\r
7daf2401 LE	150	RootBus->NoExtendedConfigSpace = (PcdGet16 (PcdOvmfHostBridgePciDevId) !=\r
7daf2401 LE	151	INTEL_Q35_MCH_DEVICE_ID);\r
cb81595b	152	\r
1f4e2299 LE	153	DevicePath = AllocateCopyPool (sizeof mRootBridgeDevicePathTemplate,\r
	154	&mRootBridgeDevicePathTemplate);\r
	155	if (DevicePath == NULL) {\r
	156	DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
	157	return EFI_OUT_OF_RESOURCES;\r
	158	}\r
	159	DevicePath->AcpiDevicePath.UID = RootBusNumber;\r
	160	RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
	161	\r
	162	DEBUG ((EFI_D_INFO,\r
	163	"%a: populated root bus %d, with room for %d subordinate bus(es)\n",\r
	164	__FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));\r
	165	return EFI_SUCCESS;\r
46e46eaf LE	166	}\r
	167	\r
	168	\r
	169	/**\r
	170	Uninitialize a PCI_ROOT_BRIDGE structure set up with InitRootBridge().\r
	171	\r
	172	param[in] RootBus The PCI_ROOT_BRIDGE structure, allocated by the caller and\r
	173	initialized with InitRootBridge(), that should be\r
	174	uninitialized. This function doesn't free RootBus.\r
	175	**/\r
	176	STATIC\r
	177	VOID\r
	178	UninitRootBridge (\r
	179	IN PCI_ROOT_BRIDGE *RootBus\r
	180	)\r
	181	{\r
1f4e2299	182	FreePool (RootBus->DevicePath);\r
46e46eaf LE	183	}\r
	184	\r
	185	\r
d85861d7 LE	186	/**\r
	187	Return all the root bridge instances in an array.\r
	188	\r
	189	@param Count Return the count of root bridge instances.\r
	190	\r
	191	@return All the root bridge instances in an array.\r
	192	The array should be passed into PciHostBridgeFreeRootBridges()\r
	193	when it's not used.\r
	194	**/\r
	195	PCI_ROOT_BRIDGE *\r
	196	EFIAPI\r
	197	PciHostBridgeGetRootBridges (\r
	198	UINTN *Count\r
	199	)\r
	200	{\r
46e46eaf LE	201	EFI_STATUS Status;\r
	202	FIRMWARE_CONFIG_ITEM FwCfgItem;\r
	203	UINTN FwCfgSize;\r
	204	UINT64 ExtraRootBridges;\r
	205	PCI_ROOT_BRIDGE *Bridges;\r
	206	UINTN Initialized;\r
	207	UINTN LastRootBridgeNumber;\r
	208	UINTN RootBridgeNumber;\r
	209	\r
d85861d7	210	*Count = 0;\r
46e46eaf LE	211	\r
	212	//\r
	213	// QEMU provides the number of extra root buses, shortening the exhaustive\r
	214	// search below. If there is no hint, the feature is missing.\r
	215	//\r
	216	Status = QemuFwCfgFindFile ("etc/extra-pci-roots", &FwCfgItem, &FwCfgSize);\r
	217	if (EFI_ERROR (Status) \|\| FwCfgSize != sizeof ExtraRootBridges) {\r
	218	ExtraRootBridges = 0;\r
	219	} else {\r
	220	QemuFwCfgSelectItem (FwCfgItem);\r
	221	QemuFwCfgReadBytes (FwCfgSize, &ExtraRootBridges);\r
	222	\r
	223	if (ExtraRootBridges > PCI_MAX_BUS) {\r
	224	DEBUG ((EFI_D_ERROR, "%a: invalid count of extra root buses (%Lu) "\r
	225	"reported by QEMU\n", __FUNCTION__, ExtraRootBridges));\r
	226	return NULL;\r
	227	}\r
	228	DEBUG ((EFI_D_INFO, "%a: %Lu extra root buses reported by QEMU\n",\r
	229	__FUNCTION__, ExtraRootBridges));\r
	230	}\r
	231	\r
	232	//\r
	233	// Allocate the "main" root bridge, and any extra root bridges.\r
	234	//\r
	235	Bridges = AllocatePool ((1 + (UINTN)ExtraRootBridges) * sizeof *Bridges);\r
	236	if (Bridges == NULL) {\r
	237	DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
	238	return NULL;\r
	239	}\r
	240	Initialized = 0;\r
	241	\r
	242	//\r
	243	// The "main" root bus is always there.\r
	244	//\r
	245	LastRootBridgeNumber = 0;\r
	246	\r
	247	//\r
	248	// Scan all other root buses. If function 0 of any device on a bus returns a\r
	249	// VendorId register value different from all-bits-one, then that bus is\r
	250	// alive.\r
	251	//\r
	252	for (RootBridgeNumber = 1;\r
	253	RootBridgeNumber <= PCI_MAX_BUS && Initialized < ExtraRootBridges;\r
	254	++RootBridgeNumber) {\r
	255	UINTN Device;\r
	256	\r
	257	for (Device = 0; Device <= PCI_MAX_DEVICE; ++Device) {\r
	258	if (PciRead16 (PCI_LIB_ADDRESS (RootBridgeNumber, Device, 0,\r
	259	PCI_VENDOR_ID_OFFSET)) != MAX_UINT16) {\r
	260	break;\r
	261	}\r
	262	}\r
	263	if (Device <= PCI_MAX_DEVICE) {\r
	264	//\r
	265	// Found the next root bus. We can now install the previous one,\r
	266	// because now we know how big a bus number range that one has, for any\r
	267	// subordinate buses that might exist behind PCI bridges hanging off it.\r
	268	//\r
	269	Status = InitRootBridge ((UINT8)LastRootBridgeNumber,\r
	270	(UINT8)(RootBridgeNumber - 1), &Bridges[Initialized]);\r
	271	if (EFI_ERROR (Status)) {\r
	272	goto FreeBridges;\r
	273	}\r
	274	++Initialized;\r
275	LastRootBridgeNumber = RootBridgeNumber;\r
276	}\r
277	}\r
278	\r
279	//\r
280	// Install the last root bus (which might be the only, ie. main, root bus, if\r
281	// we've found no extra root buses).\r
282	//\r
283	Status = InitRootBridge ((UINT8)LastRootBridgeNumber, PCI_MAX_BUS,\r
284	&Bridges[Initialized]);\r
285	if (EFI_ERROR (Status)) {\r
286	goto FreeBridges;\r
287	}\r
288	++Initialized;\r
289	\r
290	*Count = Initialized;\r
291	return Bridges;\r
292	\r
293	FreeBridges:\r
294	while (Initialized > 0) {\r
295	--Initialized;\r
296	UninitRootBridge (&Bridges[Initialized]);\r
297	}\r
298	\r
299	FreePool (Bridges);\r
d85861d7 LE	300	return NULL;\r
	301	}\r
	302	\r
46e46eaf	303	\r
d85861d7 LE	304	/**\r
	305	Free the root bridge instances array returned from\r
	306	PciHostBridgeGetRootBridges().\r
	307	\r
	308	@param The root bridge instances array.\r
	309	@param The count of the array.\r
	310	**/\r
	311	VOID\r
	312	EFIAPI\r
	313	PciHostBridgeFreeRootBridges (\r
	314	PCI_ROOT_BRIDGE *Bridges,\r
	315	UINTN Count\r
	316	)\r
	317	{\r
dc4d6467 LE	318	if (Bridges == NULL && Count == 0) {\r
	319	return;\r
	320	}\r
	321	ASSERT (Bridges != NULL && Count > 0);\r
	322	\r
	323	do {\r
	324	--Count;\r
	325	UninitRootBridge (&Bridges[Count]);\r
	326	} while (Count > 0);\r
	327	\r
	328	FreePool (Bridges);\r
d85861d7 LE	329	}\r
d85861d7 LE	330	\r
46e46eaf	331	\r
d85861d7 LE	332	/**\r
	333	Inform the platform that the resource conflict happens.\r
	334	\r
	335	@param HostBridgeHandle Handle of the Host Bridge.\r
	336	@param Configuration Pointer to PCI I/O and PCI memory resource\r
	337	descriptors. The Configuration contains the resources\r
	338	for all the root bridges. The resource for each root\r
	339	bridge is terminated with END descriptor and an\r
	340	additional END is appended indicating the end of the\r
	341	entire resources. The resource descriptor field\r
	342	values follow the description in\r
	343	EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
	344	.SubmitResources().\r
	345	**/\r
	346	VOID\r
	347	EFIAPI\r
	348	PciHostBridgeResourceConflict (\r
	349	EFI_HANDLE HostBridgeHandle,\r
	350	VOID *Configuration\r
	351	)\r
	352	{\r
	353	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r
	354	UINTN RootBridgeIndex;\r
	355	DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));\r
	356	\r
	357	RootBridgeIndex = 0;\r
	358	Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
	359	while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
	360	DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));\r
	361	for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {\r
	362	ASSERT (Descriptor->ResType <\r
	363	(sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /\r
	364	sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])\r
	365	)\r
	366	);\r
	367	DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",\r
	368	mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],\r
	369	Descriptor->AddrLen, Descriptor->AddrRangeMax\r
	370	));\r
	371	if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {\r
	372	DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",\r
	373	Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,\r
	374	((Descriptor->SpecificFlag &\r
	375	EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE\r
	376	) != 0) ? L" (Prefetchable)" : L""\r
	377	));\r
	378	}\r
	379	}\r
	380	//\r
	381	// Skip the END descriptor for root bridge\r
	382	//\r
	383	ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);\r
	384	Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(\r
	385	(EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1\r
	386	);\r
	387	}\r
	388	}\r