]> git.proxmox.com Git - mirror_edk2.git/blame - OvmfPkg/Library/PciHostBridgeLib/XenSupport.c
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UefiCpuPkg/PiSmmCpuDxeSmm: remove superfluous ENDs from NASM source
[mirror_edk2.git] / OvmfPkg / Library / PciHostBridgeLib / XenSupport.c
CommitLineData
49effaf2
RN		 1/** @file\r
2 Scan the entire PCI bus for root bridges to support OVMF above Xen.\r
3\r
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
5\r
6 This program and the accompanying materials are licensed and made available\r
7 under the terms and conditions of the BSD License which accompanies this\r
8 distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15#include <PiDxe.h>\r
16\r
17#include <IndustryStandard/Pci.h>\r
18#include <IndustryStandard/Q35MchIch9.h>\r
19\r
20#include <Protocol/PciHostBridgeResourceAllocation.h>\r
21#include <Protocol/PciRootBridgeIo.h>\r
22\r
23#include <Library/BaseMemoryLib.h>\r
24#include <Library/DebugLib.h>\r
25#include <Library/MemoryAllocationLib.h>\r
26#include <Library/PciHostBridgeLib.h>\r
27#include <Library/PciLib.h>\r
28#include "PciHostBridge.h"\r
29\r
30STATIC\r
31VOID\r
32PcatPciRootBridgeBarExisted (\r
33 IN UINT64 Address,\r
34 OUT UINT32 *OriginalValue,\r
35 OUT UINT32 *Value\r
36 )\r
37{\r
38 //\r
39 // Preserve the original value\r
40 //\r
41 *OriginalValue = PciRead32 (Address);\r
42\r
43 //\r
44 // Disable timer interrupt while the BAR is probed\r
45 //\r
46 DisableInterrupts ();\r
47\r
48 PciWrite32 (Address, 0xFFFFFFFF);\r
49 *Value = PciRead32 (Address);\r
50 PciWrite32 (Address, *OriginalValue);\r
51\r
52 //\r
53 // Enable interrupt\r
54 //\r
55 EnableInterrupts ();\r
56}\r
57\r
58STATIC\r
59VOID\r
60PcatPciRootBridgeParseBars (\r
61 IN UINT16 Command,\r
62 IN UINTN Bus,\r
63 IN UINTN Device,\r
64 IN UINTN Function,\r
65 IN UINTN BarOffsetBase,\r
66 IN UINTN BarOffsetEnd,\r
67 IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
68 IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
69 IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
70 IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
71 IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
72\r
73)\r
74{\r
75 UINT32 OriginalValue;\r
76 UINT32 Value;\r
77 UINT32 OriginalUpperValue;\r
78 UINT32 UpperValue;\r
79 UINT64 Mask;\r
80 UINTN Offset;\r
81 UINT64 Base;\r
82 UINT64 Length;\r
83 UINT64 Limit;\r
84 PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
85\r
86 for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
87 PcatPciRootBridgeBarExisted (\r
88 PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
89 &OriginalValue, &Value\r
90 );\r
91 if (Value == 0) {\r
92 continue;\r
93 }\r
94 if ((Value & BIT0) == BIT0) {\r
95 //\r
96 // IO Bar\r
97 //\r
98 if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
99 Mask = 0xfffffffc;\r
100 Base = OriginalValue & Mask;\r
101 Length = ((~(Value & Mask)) & Mask) + 0x04;\r
102 if (!(Value & 0xFFFF0000)) {\r
103 Length &= 0x0000FFFF;\r
104 }\r
105 Limit = Base + Length - 1;\r
106\r
107 if (Base < Limit) {\r
108 if (Io->Base > Base) {\r
109 Io->Base = Base;\r
110 }\r
111 if (Io->Limit < Limit) {\r
112 Io->Limit = Limit;\r
113 }\r
114 }\r
115 }\r
116 } else {\r
117 //\r
118 // Mem Bar\r
119 //\r
120 if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
121\r
122 Mask = 0xfffffff0;\r
123 Base = OriginalValue & Mask;\r
124 Length = Value & Mask;\r
125\r
126 if ((Value & (BIT1 | BIT2)) == 0) {\r
127 //\r
128 // 32bit\r
129 //\r
130 Length = ((~Length) + 1) & 0xffffffff;\r
131\r
132 if ((Value & BIT3) == BIT3) {\r
133 MemAperture = PMem;\r
134 } else {\r
135 MemAperture = Mem;\r
136 }\r
137 } else {\r
138 //\r
139 // 64bit\r
140 //\r
141 Offset += 4;\r
142 PcatPciRootBridgeBarExisted (\r
143 PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
144 &OriginalUpperValue,\r
145 &UpperValue\r
146 );\r
147\r
148 Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
149 Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
150 Length = (~Length) + 1;\r
151\r
152 if ((Value & BIT3) == BIT3) {\r
153 MemAperture = PMemAbove4G;\r
154 } else {\r
155 MemAperture = MemAbove4G;\r
156 }\r
157 }\r
158\r
159 Limit = Base + Length - 1;\r
160 if (Base < Limit) {\r
161 if (MemAperture->Base > Base) {\r
162 MemAperture->Base = Base;\r
163 }\r
164 if (MemAperture->Limit < Limit) {\r
165 MemAperture->Limit = Limit;\r
166 }\r
167 }\r
168 }\r
169 }\r
170 }\r
171}\r
172\r
173PCI_ROOT_BRIDGE *\r
174ScanForRootBridges (\r
175 UINTN *NumberOfRootBridges\r
176 )\r
177{\r
178 UINTN PrimaryBus;\r
179 UINTN SubBus;\r
180 UINT8 Device;\r
181 UINT8 Function;\r
182 UINTN NumberOfDevices;\r
183 UINT64 Address;\r
184 PCI_TYPE01 Pci;\r
185 UINT64 Attributes;\r
186 UINT64 Base;\r
187 UINT64 Limit;\r
188 UINT64 Value;\r
189 PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r
190 PCI_ROOT_BRIDGE *RootBridges;\r
191 UINTN BarOffsetEnd;\r
192\r
193\r
194 *NumberOfRootBridges = 0;\r
195 RootBridges = NULL;\r
196\r
197 //\r
198 // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
199 // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
200 // root bridge's subordinate bus number + 1.\r
201 //\r
202 for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
203 SubBus = PrimaryBus;\r
204 Attributes = 0;\r
205 Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
206 Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;\r
207 //\r
208 // Scan all the PCI devices on the primary bus of the PCI root bridge\r
209 //\r
210 for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
211\r
212 for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
213\r
214 //\r
215 // Compute the PCI configuration address of the PCI device to probe\r
216 //\r
217 Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
218\r
219 //\r
220 // Read the Vendor ID from the PCI Configuration Header\r
221 //\r
222 if (PciRead16 (Address) == MAX_UINT16) {\r
223 if (Function == 0) {\r
224 //\r
225 // If the PCI Configuration Read fails, or a PCI device does not\r
226 // exist, then skip this entire PCI device\r
227 //\r
228 break;\r
229 } else {\r
230 //\r
231 // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
232 // PCI function.\r
233 //\r
234 continue;\r
235 }\r
236 }\r
237\r
238 //\r
239 // Read the entire PCI Configuration Header\r
240 //\r
241 PciReadBuffer (Address, sizeof (Pci), &Pci);\r
242\r
243 //\r
244 // Increment the number of PCI device found on the primary bus of the\r
245 // PCI root bridge\r
246 //\r
247 NumberOfDevices++;\r
248\r
249 //\r
250 // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
251 // register of the PCI Config Header\r
252 //\r
253 if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
254 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
255 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
256 }\r
257\r
258 BarOffsetEnd = 0;\r
259\r
260 //\r
261 // PCI-PCI Bridge\r
262 //\r
263 if (IS_PCI_BRIDGE (&Pci)) {\r
264 //\r
265 // Get the Bus range that the PPB is decoding\r
266 //\r
267 if (Pci.Bridge.SubordinateBus > SubBus) {\r
268 //\r
269 // If the suborinate bus number of the PCI-PCI bridge is greater\r
270 // than the PCI root bridge's current subordinate bus number,\r
271 // then update the PCI root bridge's subordinate bus number\r
272 //\r
273 SubBus = Pci.Bridge.SubordinateBus;\r
274 }\r
275\r
276 //\r
277 // Get the I/O range that the PPB is decoding\r
278 //\r
279 Value = Pci.Bridge.IoBase & 0x0f;\r
280 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
281 Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
282 if (Value == BIT0) {\r
283 Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
284 Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
285 }\r
286 if (Base < Limit) {\r
287 if (Io.Base > Base) {\r
288 Io.Base = Base;\r
289 }\r
290 if (Io.Limit < Limit) {\r
291 Io.Limit = Limit;\r
292 }\r
293 }\r
294\r
295 //\r
296 // Get the Memory range that the PPB is decoding\r
297 //\r
298 Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
299 Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
300 if (Base < Limit) {\r
301 if (Mem.Base > Base) {\r
302 Mem.Base = Base;\r
303 }\r
304 if (Mem.Limit < Limit) {\r
305 Mem.Limit = Limit;\r
306 }\r
307 }\r
308\r
309 //\r
310 // Get the Prefetchable Memory range that the PPB is decoding\r
311 //\r
312 Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
313 Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
314 Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
315 << 16) | 0xfffff;\r
316 MemAperture = &PMem;\r
317 if (Value == BIT0) {\r
318 Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
319 Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
320 MemAperture = &PMemAbove4G;\r
321 }\r
322 if (Base < Limit) {\r
323 if (MemAperture->Base > Base) {\r
324 MemAperture->Base = Base;\r
325 }\r
326 if (MemAperture->Limit < Limit) {\r
327 MemAperture->Limit = Limit;\r
328 }\r
329 }\r
330\r
331 //\r
332 // Look at the PPB Configuration for legacy decoding attributes\r
333 //\r
334 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
335 == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
336 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
337 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
338 Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
339 }\r
340 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
341 == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
342 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
343 Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
344 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
345 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
346 != 0) {\r
347 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
348 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
349 }\r
350 }\r
351\r
352 BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
353 } else {\r
354 //\r
355 // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
356 // Ranges, and Prefetchable Memory Ranges the device is decoding\r
357 //\r
358 if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
359 BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
360 }\r
361 }\r
362\r
363 PcatPciRootBridgeParseBars (\r
364 Pci.Hdr.Command,\r
365 PrimaryBus,\r
366 Device,\r
367 Function,\r
368 OFFSET_OF (PCI_TYPE00, Device.Bar),\r
369 BarOffsetEnd,\r
370 &Io,\r
371 &Mem, &MemAbove4G,\r
372 &PMem, &PMemAbove4G\r
373 );\r
374\r
375 //\r
376 // See if the PCI device is an IDE controller\r
377 //\r
378 if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
379 PCI_CLASS_MASS_STORAGE_IDE)) {\r
380 if (Pci.Hdr.ClassCode[0] & 0x80) {\r
381 Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
382 Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
383 }\r
384 if (Pci.Hdr.ClassCode[0] & 0x01) {\r
385 Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
386 }\r
387 if (Pci.Hdr.ClassCode[0] & 0x04) {\r
388 Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
389 }\r
390 }\r
391\r
392 //\r
393 // See if the PCI device is a legacy VGA controller or\r
394 // a standard VGA controller\r
395 //\r
396 if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
397 IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
398 ) {\r
399 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
400 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
401 Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
402 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
403 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
404 }\r
405\r
406 //\r
407 // See if the PCI Device is a PCI - ISA or PCI - EISA\r
408 // or ISA_POSITIVIE_DECODE Bridge device\r
409 //\r
410 if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
411 if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
412 Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
413 Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
414 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
415 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
416 Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
417 }\r
418 }\r
419\r
420 //\r
421 // If this device is not a multi function device, then skip the rest\r
422 // of this PCI device\r
423 //\r
424 if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
425 break;\r
426 }\r
427 }\r
428 }\r
429\r
430 //\r
431 // If at least one PCI device was found on the primary bus of this PCI\r
432 // root bridge, then the PCI root bridge exists.\r
433 //\r
434 if (NumberOfDevices > 0) {\r
435 RootBridges = ReallocatePool (\r
436 (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
437 (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
438 RootBridges\r
439 );\r
440 ASSERT (RootBridges != NULL);\r
441 InitRootBridge (\r
442 Attributes, Attributes, 0,\r
443 (UINT8) PrimaryBus, (UINT8) SubBus,\r
444 &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r
445 &RootBridges[*NumberOfRootBridges]\r
446 );\r
447 RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
448 //\r
449 // Increment the index for the next PCI Root Bridge\r
450 //\r
451 (*NumberOfRootBridges)++;\r
452 }\r
453 }\r
454\r
455 return RootBridges;\r
456}\r
EFI Development Kit II mirror for PVE