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86d71589 | 1 | /** @file\r |
b1bfdd65 | 2 | The CPU specific programming for PiSmmCpuDxeSmm module.\r |
86d71589 | 3 | \r |
b1bfdd65 | 4 | Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r |
86d71589 | 5 | \r |
b1bfdd65 LE |
6 | This program and the accompanying materials are licensed and made available\r |
7 | under the terms and conditions of the BSD License which accompanies this\r | |
8 | distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
86d71589 | 10 | \r |
b1bfdd65 LE |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r |
12 | WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
86d71589 PB |
13 | **/\r |
14 | \r | |
86d71589 | 15 | #include <Library/BaseLib.h>\r |
4036b4e5 | 16 | #include <Library/BaseMemoryLib.h>\r |
4a9b250b | 17 | #include <Library/DebugLib.h>\r |
4a9b250b | 18 | #include <Library/SmmCpuFeaturesLib.h>\r |
4036b4e5 | 19 | #include <Library/SmmServicesTableLib.h>\r |
4a9b250b | 20 | #include <PiSmm.h>\r |
c1fcd80b | 21 | #include <Register/QemuSmramSaveStateMap.h>\r |
86d71589 | 22 | \r |
4036b4e5 PB |
23 | //\r |
24 | // EFER register LMA bit\r | |
25 | //\r | |
26 | #define LMA BIT10\r | |
27 | \r | |
86d71589 PB |
28 | /**\r |
29 | The constructor function\r | |
30 | \r | |
31 | @param[in] ImageHandle The firmware allocated handle for the EFI image.\r | |
32 | @param[in] SystemTable A pointer to the EFI System Table.\r | |
33 | \r | |
34 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r | |
35 | \r | |
36 | **/\r | |
37 | EFI_STATUS\r | |
38 | EFIAPI\r | |
39 | SmmCpuFeaturesLibConstructor (\r | |
40 | IN EFI_HANDLE ImageHandle,\r | |
41 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
42 | )\r | |
43 | {\r | |
86d71589 | 44 | //\r |
d7e71b29 | 45 | // No need to program SMRRs on our virtual platform.\r |
86d71589 | 46 | //\r |
86d71589 PB |
47 | return EFI_SUCCESS;\r |
48 | }\r | |
49 | \r | |
50 | /**\r | |
51 | Called during the very first SMI into System Management Mode to initialize\r | |
52 | CPU features, including SMBASE, for the currently executing CPU. Since this\r | |
53 | is the first SMI, the SMRAM Save State Map is at the default address of\r | |
54 | SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r | |
55 | CPU is specified by CpuIndex and CpuIndex can be used to access information\r | |
56 | about the currently executing CPU in the ProcessorInfo array and the\r | |
57 | HotPlugCpuData data structure.\r | |
58 | \r | |
59 | @param[in] CpuIndex The index of the CPU to initialize. The value\r | |
60 | must be between 0 and the NumberOfCpus field in\r | |
61 | the System Management System Table (SMST).\r | |
62 | @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r | |
63 | was elected as monarch during System Management\r | |
64 | Mode initialization.\r | |
65 | FALSE if the CpuIndex is not the index of the CPU\r | |
66 | that was elected as monarch during System\r | |
67 | Management Mode initialization.\r | |
68 | @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r | |
69 | structures. ProcessorInfo[CpuIndex] contains the\r | |
70 | information for the currently executing CPU.\r | |
71 | @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r | |
72 | contains the ApidId and SmBase arrays.\r | |
73 | **/\r | |
74 | VOID\r | |
75 | EFIAPI\r | |
76 | SmmCpuFeaturesInitializeProcessor (\r | |
77 | IN UINTN CpuIndex,\r | |
78 | IN BOOLEAN IsMonarch,\r | |
79 | IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r | |
80 | IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r | |
81 | )\r | |
82 | {\r | |
c1fcd80b | 83 | QEMU_SMRAM_SAVE_STATE_MAP *CpuState;\r |
86d71589 PB |
84 | \r |
85 | //\r | |
86 | // Configure SMBASE.\r | |
87 | //\r | |
b1bfdd65 LE |
88 | CpuState = (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(\r |
89 | SMM_DEFAULT_SMBASE +\r | |
90 | SMRAM_SAVE_STATE_MAP_OFFSET\r | |
91 | );\r | |
c1fcd80b PB |
92 | if ((CpuState->x86.SMMRevId & 0xFFFF) == 0) {\r |
93 | CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r | |
94 | } else {\r | |
95 | CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r | |
96 | }\r | |
86d71589 PB |
97 | \r |
98 | //\r | |
d7e71b29 | 99 | // No need to program SMRRs on our virtual platform.\r |
86d71589 | 100 | //\r |
86d71589 PB |
101 | }\r |
102 | \r | |
103 | /**\r | |
104 | This function updates the SMRAM save state on the currently executing CPU\r | |
105 | to resume execution at a specific address after an RSM instruction. This\r | |
106 | function must evaluate the SMRAM save state to determine the execution mode\r | |
107 | the RSM instruction resumes and update the resume execution address with\r | |
108 | either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r | |
109 | flag in the SMRAM save state must always be cleared. This function returns\r | |
110 | the value of the instruction pointer from the SMRAM save state that was\r | |
111 | replaced. If this function returns 0, then the SMRAM save state was not\r | |
112 | modified.\r | |
113 | \r | |
114 | This function is called during the very first SMI on each CPU after\r | |
115 | SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r | |
116 | to signal that the SMBASE of each CPU has been updated before the default\r | |
117 | SMBASE address is used for the first SMI to the next CPU.\r | |
118 | \r | |
119 | @param[in] CpuIndex The index of the CPU to hook. The value\r | |
120 | must be between 0 and the NumberOfCpus\r | |
b1bfdd65 LE |
121 | field in the System Management System\r |
122 | Table (SMST).\r | |
86d71589 PB |
123 | @param[in] CpuState Pointer to SMRAM Save State Map for the\r |
124 | currently executing CPU.\r | |
125 | @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r | |
126 | 32-bit execution mode from 64-bit SMM.\r | |
127 | @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r | |
128 | same execution mode as SMM.\r | |
129 | \r | |
130 | @retval 0 This function did modify the SMRAM save state.\r | |
131 | @retval > 0 The original instruction pointer value from the SMRAM save state\r | |
132 | before it was replaced.\r | |
133 | **/\r | |
134 | UINT64\r | |
135 | EFIAPI\r | |
136 | SmmCpuFeaturesHookReturnFromSmm (\r | |
137 | IN UINTN CpuIndex,\r | |
138 | IN SMRAM_SAVE_STATE_MAP *CpuState,\r | |
139 | IN UINT64 NewInstructionPointer32,\r | |
140 | IN UINT64 NewInstructionPointer\r | |
141 | )\r | |
142 | {\r | |
c1fcd80b | 143 | UINT64 OriginalInstructionPointer;\r |
b1bfdd65 | 144 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r |
4036b4e5 | 145 | \r |
b1bfdd65 | 146 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState;\r |
4036b4e5 PB |
147 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r |
148 | OriginalInstructionPointer = (UINT64)CpuSaveState->x86._EIP;\r | |
149 | CpuSaveState->x86._EIP = (UINT32)NewInstructionPointer;\r | |
150 | //\r | |
151 | // Clear the auto HALT restart flag so the RSM instruction returns\r | |
152 | // program control to the instruction following the HLT instruction.\r | |
153 | //\r | |
154 | if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != 0) {\r | |
155 | CpuSaveState->x86.AutoHALTRestart &= ~BIT0;\r | |
156 | }\r | |
157 | } else {\r | |
158 | OriginalInstructionPointer = CpuSaveState->x64._RIP;\r | |
159 | if ((CpuSaveState->x64.IA32_EFER & LMA) == 0) {\r | |
160 | CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer32;\r | |
161 | } else {\r | |
162 | CpuSaveState->x64._RIP = (UINT32)NewInstructionPointer;\r | |
163 | }\r | |
164 | //\r | |
165 | // Clear the auto HALT restart flag so the RSM instruction returns\r | |
166 | // program control to the instruction following the HLT instruction.\r | |
167 | //\r | |
168 | if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != 0) {\r | |
169 | CpuSaveState->x64.AutoHALTRestart &= ~BIT0;\r | |
170 | }\r | |
171 | }\r | |
172 | return OriginalInstructionPointer;\r | |
86d71589 PB |
173 | }\r |
174 | \r | |
175 | /**\r | |
176 | Hook point in normal execution mode that allows the one CPU that was elected\r | |
177 | as monarch during System Management Mode initialization to perform additional\r | |
178 | initialization actions immediately after all of the CPUs have processed their\r | |
179 | first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r | |
180 | into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r | |
181 | **/\r | |
182 | VOID\r | |
183 | EFIAPI\r | |
184 | SmmCpuFeaturesSmmRelocationComplete (\r | |
185 | VOID\r | |
186 | )\r | |
187 | {\r | |
188 | }\r | |
189 | \r | |
190 | /**\r | |
191 | Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is\r | |
192 | returned, then a custom SMI handler is not provided by this library,\r | |
193 | and the default SMI handler must be used.\r | |
194 | \r | |
195 | @retval 0 Use the default SMI handler.\r | |
b1bfdd65 LE |
196 | @retval > 0 Use the SMI handler installed by\r |
197 | SmmCpuFeaturesInstallSmiHandler(). The caller is required to\r | |
198 | allocate enough SMRAM for each CPU to support the size of the\r | |
199 | custom SMI handler.\r | |
86d71589 PB |
200 | **/\r |
201 | UINTN\r | |
202 | EFIAPI\r | |
203 | SmmCpuFeaturesGetSmiHandlerSize (\r | |
204 | VOID\r | |
205 | )\r | |
206 | {\r | |
207 | return 0;\r | |
208 | }\r | |
209 | \r | |
210 | /**\r | |
b1bfdd65 LE |
211 | Install a custom SMI handler for the CPU specified by CpuIndex. This\r |
212 | function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size\r | |
213 | is greater than zero and is called by the CPU that was elected as monarch\r | |
214 | during System Management Mode initialization.\r | |
86d71589 PB |
215 | \r |
216 | @param[in] CpuIndex The index of the CPU to install the custom SMI handler.\r | |
217 | The value must be between 0 and the NumberOfCpus field\r | |
218 | in the System Management System Table (SMST).\r | |
219 | @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.\r | |
220 | @param[in] SmiStack The stack to use when an SMI is processed by the\r | |
221 | the CPU specified by CpuIndex.\r | |
222 | @param[in] StackSize The size, in bytes, if the stack used when an SMI is\r | |
223 | processed by the CPU specified by CpuIndex.\r | |
224 | @param[in] GdtBase The base address of the GDT to use when an SMI is\r | |
225 | processed by the CPU specified by CpuIndex.\r | |
226 | @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is\r | |
227 | processed by the CPU specified by CpuIndex.\r | |
228 | @param[in] IdtBase The base address of the IDT to use when an SMI is\r | |
229 | processed by the CPU specified by CpuIndex.\r | |
230 | @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is\r | |
231 | processed by the CPU specified by CpuIndex.\r | |
232 | @param[in] Cr3 The base address of the page tables to use when an SMI\r | |
233 | is processed by the CPU specified by CpuIndex.\r | |
234 | **/\r | |
235 | VOID\r | |
236 | EFIAPI\r | |
237 | SmmCpuFeaturesInstallSmiHandler (\r | |
238 | IN UINTN CpuIndex,\r | |
239 | IN UINT32 SmBase,\r | |
240 | IN VOID *SmiStack,\r | |
241 | IN UINTN StackSize,\r | |
242 | IN UINTN GdtBase,\r | |
243 | IN UINTN GdtSize,\r | |
244 | IN UINTN IdtBase,\r | |
245 | IN UINTN IdtSize,\r | |
246 | IN UINT32 Cr3\r | |
247 | )\r | |
248 | {\r | |
249 | }\r | |
250 | \r | |
251 | /**\r | |
252 | Determines if MTRR registers must be configured to set SMRAM cache-ability\r | |
253 | when executing in System Management Mode.\r | |
254 | \r | |
255 | @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r | |
256 | @retval FALSE MTRR registers do not need to be configured to set SMRAM\r | |
257 | cache-ability.\r | |
258 | **/\r | |
259 | BOOLEAN\r | |
260 | EFIAPI\r | |
261 | SmmCpuFeaturesNeedConfigureMtrrs (\r | |
262 | VOID\r | |
263 | )\r | |
264 | {\r | |
d7e71b29 | 265 | return FALSE;\r |
86d71589 PB |
266 | }\r |
267 | \r | |
268 | /**\r | |
b1bfdd65 LE |
269 | Disable SMRR register if SMRR is supported and\r |
270 | SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r | |
86d71589 PB |
271 | **/\r |
272 | VOID\r | |
273 | EFIAPI\r | |
274 | SmmCpuFeaturesDisableSmrr (\r | |
275 | VOID\r | |
276 | )\r | |
277 | {\r | |
d7e71b29 PB |
278 | //\r |
279 | // No SMRR support, nothing to do\r | |
280 | //\r | |
86d71589 PB |
281 | }\r |
282 | \r | |
283 | /**\r | |
b1bfdd65 LE |
284 | Enable SMRR register if SMRR is supported and\r |
285 | SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.\r | |
86d71589 PB |
286 | **/\r |
287 | VOID\r | |
288 | EFIAPI\r | |
289 | SmmCpuFeaturesReenableSmrr (\r | |
290 | VOID\r | |
291 | )\r | |
292 | {\r | |
d7e71b29 PB |
293 | //\r |
294 | // No SMRR support, nothing to do\r | |
295 | //\r | |
86d71589 PB |
296 | }\r |
297 | \r | |
298 | /**\r | |
299 | Processor specific hook point each time a CPU enters System Management Mode.\r | |
300 | \r | |
301 | @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r | |
302 | must be between 0 and the NumberOfCpus field in the\r | |
303 | System Management System Table (SMST).\r | |
304 | **/\r | |
305 | VOID\r | |
306 | EFIAPI\r | |
307 | SmmCpuFeaturesRendezvousEntry (\r | |
308 | IN UINTN CpuIndex\r | |
309 | )\r | |
310 | {\r | |
311 | //\r | |
d7e71b29 | 312 | // No SMRR support, nothing to do\r |
86d71589 | 313 | //\r |
86d71589 PB |
314 | }\r |
315 | \r | |
316 | /**\r | |
317 | Processor specific hook point each time a CPU exits System Management Mode.\r | |
318 | \r | |
b1bfdd65 LE |
319 | @param[in] CpuIndex The index of the CPU that is exiting SMM. The value\r |
320 | must be between 0 and the NumberOfCpus field in the\r | |
321 | System Management System Table (SMST).\r | |
86d71589 PB |
322 | **/\r |
323 | VOID\r | |
324 | EFIAPI\r | |
325 | SmmCpuFeaturesRendezvousExit (\r | |
326 | IN UINTN CpuIndex\r | |
327 | )\r | |
328 | {\r | |
329 | }\r | |
330 | \r | |
331 | /**\r | |
332 | Check to see if an SMM register is supported by a specified CPU.\r | |
333 | \r | |
334 | @param[in] CpuIndex The index of the CPU to check for SMM register support.\r | |
335 | The value must be between 0 and the NumberOfCpus field\r | |
336 | in the System Management System Table (SMST).\r | |
337 | @param[in] RegName Identifies the SMM register to check for support.\r | |
338 | \r | |
339 | @retval TRUE The SMM register specified by RegName is supported by the CPU\r | |
340 | specified by CpuIndex.\r | |
341 | @retval FALSE The SMM register specified by RegName is not supported by the\r | |
342 | CPU specified by CpuIndex.\r | |
343 | **/\r | |
344 | BOOLEAN\r | |
345 | EFIAPI\r | |
346 | SmmCpuFeaturesIsSmmRegisterSupported (\r | |
347 | IN UINTN CpuIndex,\r | |
348 | IN SMM_REG_NAME RegName\r | |
349 | )\r | |
350 | {\r | |
d7e71b29 | 351 | ASSERT (RegName == SmmRegFeatureControl);\r |
86d71589 PB |
352 | return FALSE;\r |
353 | }\r | |
354 | \r | |
355 | /**\r | |
356 | Returns the current value of the SMM register for the specified CPU.\r | |
357 | If the SMM register is not supported, then 0 is returned.\r | |
358 | \r | |
359 | @param[in] CpuIndex The index of the CPU to read the SMM register. The\r | |
360 | value must be between 0 and the NumberOfCpus field in\r | |
361 | the System Management System Table (SMST).\r | |
362 | @param[in] RegName Identifies the SMM register to read.\r | |
363 | \r | |
364 | @return The value of the SMM register specified by RegName from the CPU\r | |
365 | specified by CpuIndex.\r | |
366 | **/\r | |
367 | UINT64\r | |
368 | EFIAPI\r | |
369 | SmmCpuFeaturesGetSmmRegister (\r | |
370 | IN UINTN CpuIndex,\r | |
371 | IN SMM_REG_NAME RegName\r | |
372 | )\r | |
373 | {\r | |
d7e71b29 PB |
374 | //\r |
375 | // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.\r | |
376 | // The last of these should actually be SmmRegSmmDisable, so we can just\r | |
377 | // return FALSE.\r | |
378 | //\r | |
86d71589 PB |
379 | return 0;\r |
380 | }\r | |
381 | \r | |
382 | /**\r | |
383 | Sets the value of an SMM register on a specified CPU.\r | |
384 | If the SMM register is not supported, then no action is performed.\r | |
385 | \r | |
386 | @param[in] CpuIndex The index of the CPU to write the SMM register. The\r | |
387 | value must be between 0 and the NumberOfCpus field in\r | |
388 | the System Management System Table (SMST).\r | |
389 | @param[in] RegName Identifies the SMM register to write.\r | |
390 | registers are read-only.\r | |
391 | @param[in] Value The value to write to the SMM register.\r | |
392 | **/\r | |
393 | VOID\r | |
394 | EFIAPI\r | |
395 | SmmCpuFeaturesSetSmmRegister (\r | |
396 | IN UINTN CpuIndex,\r | |
397 | IN SMM_REG_NAME RegName,\r | |
398 | IN UINT64 Value\r | |
399 | )\r | |
400 | {\r | |
d7e71b29 | 401 | ASSERT (FALSE);\r |
86d71589 PB |
402 | }\r |
403 | \r | |
4036b4e5 | 404 | ///\r |
b1bfdd65 LE |
405 | /// Macro used to simplify the lookup table entries of type\r |
406 | /// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r | |
4036b4e5 | 407 | ///\r |
c1fcd80b | 408 | #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)\r |
4036b4e5 PB |
409 | \r |
410 | ///\r | |
b1bfdd65 LE |
411 | /// Macro used to simplify the lookup table entries of type\r |
412 | /// CPU_SMM_SAVE_STATE_REGISTER_RANGE\r | |
4036b4e5 PB |
413 | ///\r |
414 | #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r | |
415 | \r | |
416 | ///\r | |
417 | /// Structure used to describe a range of registers\r | |
418 | ///\r | |
419 | typedef struct {\r | |
420 | EFI_SMM_SAVE_STATE_REGISTER Start;\r | |
421 | EFI_SMM_SAVE_STATE_REGISTER End;\r | |
422 | UINTN Length;\r | |
423 | } CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r | |
424 | \r | |
425 | ///\r | |
426 | /// Structure used to build a lookup table to retrieve the widths and offsets\r | |
427 | /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r | |
428 | ///\r | |
429 | \r | |
430 | #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1\r | |
431 | \r | |
432 | typedef struct {\r | |
433 | UINT8 Width32;\r | |
434 | UINT8 Width64;\r | |
435 | UINT16 Offset32;\r | |
436 | UINT16 Offset64Lo;\r | |
437 | UINT16 Offset64Hi;\r | |
438 | BOOLEAN Writeable;\r | |
439 | } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r | |
440 | \r | |
441 | ///\r | |
b1bfdd65 | 442 | /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r |
4036b4e5 PB |
443 | /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r |
444 | ///\r | |
ea992760 | 445 | STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r |
b1bfdd65 LE |
446 | SMM_REGISTER_RANGE (\r |
447 | EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,\r | |
448 | EFI_SMM_SAVE_STATE_REGISTER_LDTINFO\r | |
449 | ),\r | |
450 | SMM_REGISTER_RANGE (\r | |
451 | EFI_SMM_SAVE_STATE_REGISTER_ES,\r | |
452 | EFI_SMM_SAVE_STATE_REGISTER_RIP\r | |
453 | ),\r | |
454 | SMM_REGISTER_RANGE (\r | |
455 | EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,\r | |
456 | EFI_SMM_SAVE_STATE_REGISTER_CR4\r | |
457 | ),\r | |
4036b4e5 PB |
458 | { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r |
459 | };\r | |
460 | \r | |
461 | ///\r | |
b1bfdd65 LE |
462 | /// Lookup table used to retrieve the widths and offsets associated with each\r |
463 | /// supported EFI_SMM_SAVE_STATE_REGISTER value\r | |
4036b4e5 | 464 | ///\r |
ea992760 | 465 | STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r |
b1bfdd65 LE |
466 | {\r |
467 | 0, // Width32\r | |
468 | 0, // Width64\r | |
469 | 0, // Offset32\r | |
470 | 0, // Offset64Lo\r | |
471 | 0, // Offset64Hi\r | |
472 | FALSE // Writeable\r | |
473 | }, // Reserved\r | |
4036b4e5 PB |
474 | \r |
475 | //\r | |
476 | // CPU Save State registers defined in PI SMM CPU Protocol.\r | |
477 | //\r | |
b1bfdd65 LE |
478 | {\r |
479 | 0, // Width32\r | |
480 | 8, // Width64\r | |
481 | 0, // Offset32\r | |
482 | SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo\r | |
483 | SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi\r | |
484 | FALSE // Writeable\r | |
485 | }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4\r | |
486 | \r | |
487 | {\r | |
488 | 0, // Width32\r | |
489 | 8, // Width64\r | |
490 | 0, // Offset32\r | |
491 | SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo\r | |
492 | SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi\r | |
493 | FALSE // Writeable\r | |
494 | }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5\r | |
495 | \r | |
496 | {\r | |
497 | 0, // Width32\r | |
498 | 8, // Width64\r | |
499 | 0, // Offset32\r | |
500 | SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo\r | |
501 | SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi\r | |
502 | FALSE // Writeable\r | |
503 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6\r | |
504 | \r | |
505 | {\r | |
506 | 0, // Width32\r | |
507 | 0, // Width64\r | |
508 | 0, // Offset32\r | |
509 | SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo\r | |
510 | SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi\r | |
511 | FALSE // Writeable\r | |
512 | }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r | |
513 | \r | |
514 | {\r | |
515 | 0, // Width32\r | |
516 | 0, // Width64\r | |
517 | 0, // Offset32\r | |
518 | SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo\r | |
519 | SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi\r | |
520 | FALSE // Writeable\r | |
521 | }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r | |
522 | \r | |
523 | {\r | |
524 | 0, // Width32\r | |
525 | 0, // Width64\r | |
526 | 0, // Offset32\r | |
527 | SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo\r | |
528 | SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi\r | |
529 | FALSE // Writeable\r | |
530 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r | |
531 | \r | |
532 | {\r | |
533 | 0, // Width32\r | |
534 | 0, // Width64\r | |
535 | 0, // Offset32\r | |
536 | 0, // Offset64Lo\r | |
537 | 0 + 4, // Offset64Hi\r | |
538 | FALSE // Writeable\r | |
539 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10\r | |
540 | \r | |
541 | {\r | |
542 | 4, // Width32\r | |
543 | 4, // Width64\r | |
544 | SMM_CPU_OFFSET (x86._ES), // Offset32\r | |
545 | SMM_CPU_OFFSET (x64._ES), // Offset64Lo\r | |
546 | 0, // Offset64Hi\r | |
547 | FALSE // Writeable\r | |
548 | }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20\r | |
549 | \r | |
550 | {\r | |
551 | 4, // Width32\r | |
552 | 4, // Width64\r | |
553 | SMM_CPU_OFFSET (x86._CS), // Offset32\r | |
554 | SMM_CPU_OFFSET (x64._CS), // Offset64Lo\r | |
555 | 0, // Offset64Hi\r | |
556 | FALSE // Writeable\r | |
557 | }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21\r | |
558 | \r | |
559 | {\r | |
560 | 4, // Width32\r | |
561 | 4, // Width64\r | |
562 | SMM_CPU_OFFSET (x86._SS), // Offset32\r | |
563 | SMM_CPU_OFFSET (x64._SS), // Offset64Lo\r | |
564 | 0, // Offset64Hi\r | |
565 | FALSE // Writeable\r | |
566 | }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22\r | |
567 | \r | |
568 | {\r | |
569 | 4, // Width32\r | |
570 | 4, // Width64\r | |
571 | SMM_CPU_OFFSET (x86._DS), // Offset32\r | |
572 | SMM_CPU_OFFSET (x64._DS), // Offset64Lo\r | |
573 | 0, // Offset64Hi\r | |
574 | FALSE // Writeable\r | |
575 | }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23\r | |
576 | \r | |
577 | {\r | |
578 | 4, // Width32\r | |
579 | 4, // Width64\r | |
580 | SMM_CPU_OFFSET (x86._FS), // Offset32\r | |
581 | SMM_CPU_OFFSET (x64._FS), // Offset64Lo\r | |
582 | 0, // Offset64Hi\r | |
583 | FALSE // Writeable\r | |
584 | }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24\r | |
585 | \r | |
586 | {\r | |
587 | 4, // Width32\r | |
588 | 4, // Width64\r | |
589 | SMM_CPU_OFFSET (x86._GS), // Offset32\r | |
590 | SMM_CPU_OFFSET (x64._GS), // Offset64Lo\r | |
591 | 0, // Offset64Hi\r | |
592 | FALSE // Writeable\r | |
593 | }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25\r | |
594 | \r | |
595 | {\r | |
596 | 0, // Width32\r | |
597 | 4, // Width64\r | |
598 | 0, // Offset32\r | |
599 | SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo\r | |
600 | 0, // Offset64Hi\r | |
601 | FALSE // Writeable\r | |
602 | }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r | |
603 | \r | |
604 | {\r | |
605 | 4, // Width32\r | |
606 | 4, // Width64\r | |
607 | SMM_CPU_OFFSET (x86._TR), // Offset32\r | |
608 | SMM_CPU_OFFSET (x64._TR), // Offset64Lo\r | |
609 | 0, // Offset64Hi\r | |
610 | FALSE // Writeable\r | |
611 | }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27\r | |
612 | \r | |
613 | {\r | |
614 | 4, // Width32\r | |
615 | 8, // Width64\r | |
616 | SMM_CPU_OFFSET (x86._DR7), // Offset32\r | |
617 | SMM_CPU_OFFSET (x64._DR7), // Offset64Lo\r | |
618 | SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi\r | |
619 | FALSE // Writeable\r | |
620 | }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28\r | |
621 | \r | |
622 | {\r | |
623 | 4, // Width32\r | |
624 | 8, // Width64\r | |
625 | SMM_CPU_OFFSET (x86._DR6), // Offset32\r | |
626 | SMM_CPU_OFFSET (x64._DR6), // Offset64Lo\r | |
627 | SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi\r | |
628 | FALSE // Writeable\r | |
629 | }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29\r | |
630 | \r | |
631 | {\r | |
632 | 0, // Width32\r | |
633 | 8, // Width64\r | |
634 | 0, // Offset32\r | |
635 | SMM_CPU_OFFSET (x64._R8), // Offset64Lo\r | |
636 | SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi\r | |
637 | TRUE // Writeable\r | |
638 | }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30\r | |
639 | \r | |
640 | {\r | |
641 | 0, // Width32\r | |
642 | 8, // Width64\r | |
643 | 0, // Offset32\r | |
644 | SMM_CPU_OFFSET (x64._R9), // Offset64Lo\r | |
645 | SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi\r | |
646 | TRUE // Writeable\r | |
647 | }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31\r | |
648 | \r | |
649 | {\r | |
650 | 0, // Width32\r | |
651 | 8, // Width64\r | |
652 | 0, // Offset32\r | |
653 | SMM_CPU_OFFSET (x64._R10), // Offset64Lo\r | |
654 | SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi\r | |
655 | TRUE // Writeable\r | |
656 | }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32\r | |
657 | \r | |
658 | {\r | |
659 | 0, // Width32\r | |
660 | 8, // Width64\r | |
661 | 0, // Offset32\r | |
662 | SMM_CPU_OFFSET (x64._R11), // Offset64Lo\r | |
663 | SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi\r | |
664 | TRUE // Writeable\r | |
665 | }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33\r | |
666 | \r | |
667 | {\r | |
668 | 0, // Width32\r | |
669 | 8, // Width64\r | |
670 | 0, // Offset32\r | |
671 | SMM_CPU_OFFSET (x64._R12), // Offset64Lo\r | |
672 | SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi\r | |
673 | TRUE // Writeable\r | |
674 | }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34\r | |
675 | \r | |
676 | {\r | |
677 | 0, // Width32\r | |
678 | 8, // Width64\r | |
679 | 0, // Offset32\r | |
680 | SMM_CPU_OFFSET (x64._R13), // Offset64Lo\r | |
681 | SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi\r | |
682 | TRUE // Writeable\r | |
683 | }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35\r | |
684 | \r | |
685 | {\r | |
686 | 0, // Width32\r | |
687 | 8, // Width64\r | |
688 | 0, // Offset32\r | |
689 | SMM_CPU_OFFSET (x64._R14), // Offset64Lo\r | |
690 | SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi\r | |
691 | TRUE // Writeable\r | |
692 | }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36\r | |
693 | \r | |
694 | {\r | |
695 | 0, // Width32\r | |
696 | 8, // Width64\r | |
697 | 0, // Offset32\r | |
698 | SMM_CPU_OFFSET (x64._R15), // Offset64Lo\r | |
699 | SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi\r | |
700 | TRUE // Writeable\r | |
701 | }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37\r | |
702 | \r | |
703 | {\r | |
704 | 4, // Width32\r | |
705 | 8, // Width64\r | |
706 | SMM_CPU_OFFSET (x86._EAX), // Offset32\r | |
707 | SMM_CPU_OFFSET (x64._RAX), // Offset64Lo\r | |
708 | SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi\r | |
709 | TRUE // Writeable\r | |
710 | }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38\r | |
711 | \r | |
712 | {\r | |
713 | 4, // Width32\r | |
714 | 8, // Width64\r | |
715 | SMM_CPU_OFFSET (x86._EBX), // Offset32\r | |
716 | SMM_CPU_OFFSET (x64._RBX), // Offset64Lo\r | |
717 | SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi\r | |
718 | TRUE // Writeable\r | |
719 | }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39\r | |
720 | \r | |
721 | {\r | |
722 | 4, // Width32\r | |
723 | 8, // Width64\r | |
724 | SMM_CPU_OFFSET (x86._ECX), // Offset32\r | |
725 | SMM_CPU_OFFSET (x64._RCX), // Offset64Lo\r | |
726 | SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi\r | |
727 | TRUE // Writeable\r | |
728 | }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40\r | |
729 | \r | |
730 | {\r | |
731 | 4, // Width32\r | |
732 | 8, // Width64\r | |
733 | SMM_CPU_OFFSET (x86._EDX), // Offset32\r | |
734 | SMM_CPU_OFFSET (x64._RDX), // Offset64Lo\r | |
735 | SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi\r | |
736 | TRUE // Writeable\r | |
737 | }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41\r | |
738 | \r | |
739 | {\r | |
740 | 4, // Width32\r | |
741 | 8, // Width64\r | |
742 | SMM_CPU_OFFSET (x86._ESP), // Offset32\r | |
743 | SMM_CPU_OFFSET (x64._RSP), // Offset64Lo\r | |
744 | SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi\r | |
745 | TRUE // Writeable\r | |
746 | }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42\r | |
747 | \r | |
748 | {\r | |
749 | 4, // Width32\r | |
750 | 8, // Width64\r | |
751 | SMM_CPU_OFFSET (x86._EBP), // Offset32\r | |
752 | SMM_CPU_OFFSET (x64._RBP), // Offset64Lo\r | |
753 | SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi\r | |
754 | TRUE // Writeable\r | |
755 | }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43\r | |
756 | \r | |
757 | {\r | |
758 | 4, // Width32\r | |
759 | 8, // Width64\r | |
760 | SMM_CPU_OFFSET (x86._ESI), // Offset32\r | |
761 | SMM_CPU_OFFSET (x64._RSI), // Offset64Lo\r | |
762 | SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi\r | |
763 | TRUE // Writeable\r | |
764 | }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44\r | |
765 | \r | |
766 | {\r | |
767 | 4, // Width32\r | |
768 | 8, // Width64\r | |
769 | SMM_CPU_OFFSET (x86._EDI), // Offset32\r | |
770 | SMM_CPU_OFFSET (x64._RDI), // Offset64Lo\r | |
771 | SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi\r | |
772 | TRUE // Writeable\r | |
773 | }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45\r | |
774 | \r | |
775 | {\r | |
776 | 4, // Width32\r | |
777 | 8, // Width64\r | |
778 | SMM_CPU_OFFSET (x86._EIP), // Offset32\r | |
779 | SMM_CPU_OFFSET (x64._RIP), // Offset64Lo\r | |
780 | SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi\r | |
781 | TRUE // Writeable\r | |
782 | }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46\r | |
783 | \r | |
784 | {\r | |
785 | 4, // Width32\r | |
786 | 8, // Width64\r | |
787 | SMM_CPU_OFFSET (x86._EFLAGS), // Offset32\r | |
788 | SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo\r | |
789 | SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi\r | |
790 | TRUE // Writeable\r | |
791 | }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51\r | |
792 | \r | |
793 | {\r | |
794 | 4, // Width32\r | |
795 | 8, // Width64\r | |
796 | SMM_CPU_OFFSET (x86._CR0), // Offset32\r | |
797 | SMM_CPU_OFFSET (x64._CR0), // Offset64Lo\r | |
798 | SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi\r | |
799 | FALSE // Writeable\r | |
800 | }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52\r | |
801 | \r | |
802 | {\r | |
803 | 4, // Width32\r | |
804 | 8, // Width64\r | |
805 | SMM_CPU_OFFSET (x86._CR3), // Offset32\r | |
806 | SMM_CPU_OFFSET (x64._CR3), // Offset64Lo\r | |
807 | SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi\r | |
808 | FALSE // Writeable\r | |
809 | }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53\r | |
810 | \r | |
811 | {\r | |
812 | 0, // Width32\r | |
813 | 4, // Width64\r | |
814 | 0, // Offset32\r | |
815 | SMM_CPU_OFFSET (x64._CR4), // Offset64Lo\r | |
816 | SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi\r | |
817 | FALSE // Writeable\r | |
818 | }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54\r | |
4036b4e5 PB |
819 | };\r |
820 | \r | |
821 | //\r | |
822 | // No support for I/O restart\r | |
823 | //\r | |
824 | \r | |
825 | /**\r | |
826 | Read information from the CPU save state.\r | |
827 | \r | |
828 | @param Register Specifies the CPU register to read form the save state.\r | |
829 | \r | |
830 | @retval 0 Register is not valid\r | |
831 | @retval >0 Index into mSmmCpuWidthOffset[] associated with Register\r | |
832 | \r | |
833 | **/\r | |
ea992760 LE |
834 | STATIC\r |
835 | UINTN\r | |
4036b4e5 PB |
836 | GetRegisterIndex (\r |
837 | IN EFI_SMM_SAVE_STATE_REGISTER Register\r | |
838 | )\r | |
839 | {\r | |
840 | UINTN Index;\r | |
841 | UINTN Offset;\r | |
842 | \r | |
b1bfdd65 LE |
843 | for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;\r |
844 | mSmmCpuRegisterRanges[Index].Length != 0;\r | |
845 | Index++) {\r | |
846 | if (Register >= mSmmCpuRegisterRanges[Index].Start &&\r | |
847 | Register <= mSmmCpuRegisterRanges[Index].End) {\r | |
4036b4e5 PB |
848 | return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r |
849 | }\r | |
850 | Offset += mSmmCpuRegisterRanges[Index].Length;\r | |
851 | }\r | |
852 | return 0;\r | |
853 | }\r | |
854 | \r | |
855 | /**\r | |
856 | Read a CPU Save State register on the target processor.\r | |
857 | \r | |
b1bfdd65 LE |
858 | This function abstracts the differences that whether the CPU Save State\r |
859 | register is in the IA32 CPU Save State Map or X64 CPU Save State Map.\r | |
4036b4e5 | 860 | \r |
b1bfdd65 LE |
861 | This function supports reading a CPU Save State register in SMBase relocation\r |
862 | handler.\r | |
4036b4e5 | 863 | \r |
b1bfdd65 LE |
864 | @param[in] CpuIndex Specifies the zero-based index of the CPU save\r |
865 | state.\r | |
4036b4e5 | 866 | @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.\r |
b1bfdd65 LE |
867 | @param[in] Width The number of bytes to read from the CPU save\r |
868 | state.\r | |
869 | @param[out] Buffer Upon return, this holds the CPU register value\r | |
870 | read from the save state.\r | |
4036b4e5 PB |
871 | \r |
872 | @retval EFI_SUCCESS The register was read from Save State.\r | |
b1bfdd65 LE |
873 | @retval EFI_NOT_FOUND The register is not defined for the Save State\r |
874 | of Processor.\r | |
4036b4e5 PB |
875 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r |
876 | \r | |
877 | **/\r | |
ea992760 LE |
878 | STATIC\r |
879 | EFI_STATUS\r | |
4036b4e5 PB |
880 | ReadSaveStateRegisterByIndex (\r |
881 | IN UINTN CpuIndex,\r | |
882 | IN UINTN RegisterIndex,\r | |
883 | IN UINTN Width,\r | |
884 | OUT VOID *Buffer\r | |
885 | )\r | |
886 | {\r | |
c1fcd80b | 887 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r |
4036b4e5 | 888 | \r |
c1fcd80b | 889 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r |
4036b4e5 PB |
890 | \r |
891 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r | |
892 | //\r | |
b1bfdd65 LE |
893 | // If 32-bit mode width is zero, then the specified register can not be\r |
894 | // accessed\r | |
4036b4e5 PB |
895 | //\r |
896 | if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r | |
897 | return EFI_NOT_FOUND;\r | |
898 | }\r | |
899 | \r | |
900 | //\r | |
b1bfdd65 LE |
901 | // If Width is bigger than the 32-bit mode width, then the specified\r |
902 | // register can not be accessed\r | |
4036b4e5 PB |
903 | //\r |
904 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r | |
905 | return EFI_INVALID_PARAMETER;\r | |
906 | }\r | |
907 | \r | |
908 | //\r | |
909 | // Write return buffer\r | |
910 | //\r | |
911 | ASSERT(CpuSaveState != NULL);\r | |
b1bfdd65 LE |
912 | CopyMem (\r |
913 | Buffer,\r | |
914 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r | |
915 | Width\r | |
916 | );\r | |
4036b4e5 PB |
917 | } else {\r |
918 | //\r | |
b1bfdd65 LE |
919 | // If 64-bit mode width is zero, then the specified register can not be\r |
920 | // accessed\r | |
4036b4e5 PB |
921 | //\r |
922 | if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r | |
923 | return EFI_NOT_FOUND;\r | |
924 | }\r | |
925 | \r | |
926 | //\r | |
b1bfdd65 LE |
927 | // If Width is bigger than the 64-bit mode width, then the specified\r |
928 | // register can not be accessed\r | |
4036b4e5 PB |
929 | //\r |
930 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r | |
931 | return EFI_INVALID_PARAMETER;\r | |
932 | }\r | |
933 | \r | |
934 | //\r | |
935 | // Write lower 32-bits of return buffer\r | |
936 | //\r | |
b1bfdd65 LE |
937 | CopyMem (\r |
938 | Buffer,\r | |
939 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r | |
940 | MIN (4, Width)\r | |
941 | );\r | |
4036b4e5 PB |
942 | if (Width >= 4) {\r |
943 | //\r | |
944 | // Write upper 32-bits of return buffer\r | |
945 | //\r | |
b1bfdd65 LE |
946 | CopyMem (\r |
947 | (UINT8 *)Buffer + 4,\r | |
948 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r | |
949 | Width - 4\r | |
950 | );\r | |
4036b4e5 PB |
951 | }\r |
952 | }\r | |
953 | return EFI_SUCCESS;\r | |
954 | }\r | |
955 | \r | |
86d71589 PB |
956 | /**\r |
957 | Read an SMM Save State register on the target processor. If this function\r | |
958 | returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r | |
959 | SMM Save Sate register.\r | |
960 | \r | |
961 | @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r | |
962 | value must be between 0 and the NumberOfCpus field in\r | |
963 | the System Management System Table (SMST).\r | |
964 | @param[in] Register The SMM Save State register to read.\r | |
965 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
966 | @param[out] Buffer Upon return, this holds the CPU register value read\r | |
967 | from the save state.\r | |
968 | \r | |
969 | @retval EFI_SUCCESS The register was read from Save State.\r | |
970 | @retval EFI_INVALID_PARAMTER Buffer is NULL.\r | |
b1bfdd65 LE |
971 | @retval EFI_UNSUPPORTED This function does not support reading\r |
972 | Register.\r | |
86d71589 PB |
973 | **/\r |
974 | EFI_STATUS\r | |
975 | EFIAPI\r | |
976 | SmmCpuFeaturesReadSaveStateRegister (\r | |
977 | IN UINTN CpuIndex,\r | |
978 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
979 | IN UINTN Width,\r | |
980 | OUT VOID *Buffer\r | |
981 | )\r | |
982 | {\r | |
c1fcd80b PB |
983 | UINTN RegisterIndex;\r |
984 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r | |
4036b4e5 PB |
985 | \r |
986 | //\r | |
987 | // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA\r | |
988 | //\r | |
989 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r | |
990 | //\r | |
991 | // Only byte access is supported for this register\r | |
992 | //\r | |
993 | if (Width != 1) {\r | |
994 | return EFI_INVALID_PARAMETER;\r | |
995 | }\r | |
996 | \r | |
c1fcd80b | 997 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r |
4036b4e5 PB |
998 | \r |
999 | //\r | |
1000 | // Check CPU mode\r | |
1001 | //\r | |
1002 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r | |
1003 | *(UINT8 *)Buffer = 32;\r | |
1004 | } else {\r | |
1005 | *(UINT8 *)Buffer = 64;\r | |
1006 | }\r | |
1007 | \r | |
1008 | return EFI_SUCCESS;\r | |
1009 | }\r | |
1010 | \r | |
1011 | //\r | |
1012 | // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO\r | |
1013 | //\r | |
1014 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r | |
1015 | return EFI_NOT_FOUND;\r | |
1016 | }\r | |
1017 | \r | |
1018 | //\r | |
1019 | // Convert Register to a register lookup table index. Let\r | |
1020 | // PiSmmCpuDxeSmm implement other special registers (currently\r | |
1021 | // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r | |
1022 | //\r | |
1023 | RegisterIndex = GetRegisterIndex (Register);\r | |
1024 | if (RegisterIndex == 0) {\r | |
b1bfdd65 LE |
1025 | return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r |
1026 | EFI_NOT_FOUND :\r | |
1027 | EFI_UNSUPPORTED);\r | |
4036b4e5 PB |
1028 | }\r |
1029 | \r | |
1030 | return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);\r | |
86d71589 PB |
1031 | }\r |
1032 | \r | |
1033 | /**\r | |
1034 | Writes an SMM Save State register on the target processor. If this function\r | |
1035 | returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r | |
1036 | SMM Save Sate register.\r | |
1037 | \r | |
1038 | @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r | |
1039 | value must be between 0 and the NumberOfCpus field in\r | |
1040 | the System Management System Table (SMST).\r | |
1041 | @param[in] Register The SMM Save State register to write.\r | |
1042 | @param[in] Width The number of bytes to write to the CPU save state.\r | |
1043 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
1044 | \r | |
1045 | @retval EFI_SUCCESS The register was written to Save State.\r | |
1046 | @retval EFI_INVALID_PARAMTER Buffer is NULL.\r | |
b1bfdd65 LE |
1047 | @retval EFI_UNSUPPORTED This function does not support writing\r |
1048 | Register.\r | |
86d71589 PB |
1049 | **/\r |
1050 | EFI_STATUS\r | |
1051 | EFIAPI\r | |
1052 | SmmCpuFeaturesWriteSaveStateRegister (\r | |
1053 | IN UINTN CpuIndex,\r | |
1054 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
1055 | IN UINTN Width,\r | |
1056 | IN CONST VOID *Buffer\r | |
1057 | )\r | |
1058 | {\r | |
c1fcd80b PB |
1059 | UINTN RegisterIndex;\r |
1060 | QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState;\r | |
4036b4e5 PB |
1061 | \r |
1062 | //\r | |
1063 | // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored\r | |
1064 | //\r | |
1065 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {\r | |
1066 | return EFI_SUCCESS;\r | |
1067 | }\r | |
1068 | \r | |
1069 | //\r | |
1070 | // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported\r | |
1071 | //\r | |
1072 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {\r | |
1073 | return EFI_NOT_FOUND;\r | |
1074 | }\r | |
1075 | \r | |
1076 | //\r | |
1077 | // Convert Register to a register lookup table index. Let\r | |
1078 | // PiSmmCpuDxeSmm implement other special registers (currently\r | |
1079 | // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).\r | |
1080 | //\r | |
1081 | RegisterIndex = GetRegisterIndex (Register);\r | |
1082 | if (RegisterIndex == 0) {\r | |
b1bfdd65 LE |
1083 | return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?\r |
1084 | EFI_NOT_FOUND :\r | |
1085 | EFI_UNSUPPORTED);\r | |
4036b4e5 PB |
1086 | }\r |
1087 | \r | |
c1fcd80b | 1088 | CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r |
4036b4e5 PB |
1089 | \r |
1090 | //\r | |
1091 | // Do not write non-writable SaveState, because it will cause exception.\r | |
b1bfdd65 | 1092 | //\r |
4036b4e5 PB |
1093 | if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {\r |
1094 | return EFI_UNSUPPORTED;\r | |
1095 | }\r | |
1096 | \r | |
1097 | //\r | |
1098 | // Check CPU mode\r | |
1099 | //\r | |
1100 | if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {\r | |
1101 | //\r | |
b1bfdd65 LE |
1102 | // If 32-bit mode width is zero, then the specified register can not be\r |
1103 | // accessed\r | |
4036b4e5 PB |
1104 | //\r |
1105 | if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {\r | |
1106 | return EFI_NOT_FOUND;\r | |
1107 | }\r | |
1108 | \r | |
1109 | //\r | |
b1bfdd65 LE |
1110 | // If Width is bigger than the 32-bit mode width, then the specified\r |
1111 | // register can not be accessed\r | |
4036b4e5 PB |
1112 | //\r |
1113 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r | |
1114 | return EFI_INVALID_PARAMETER;\r | |
1115 | }\r | |
1116 | //\r | |
1117 | // Write SMM State register\r | |
1118 | //\r | |
1119 | ASSERT (CpuSaveState != NULL);\r | |
b1bfdd65 LE |
1120 | CopyMem (\r |
1121 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,\r | |
1122 | Buffer,\r | |
1123 | Width\r | |
1124 | );\r | |
4036b4e5 PB |
1125 | } else {\r |
1126 | //\r | |
b1bfdd65 LE |
1127 | // If 64-bit mode width is zero, then the specified register can not be\r |
1128 | // accessed\r | |
4036b4e5 PB |
1129 | //\r |
1130 | if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {\r | |
1131 | return EFI_NOT_FOUND;\r | |
1132 | }\r | |
1133 | \r | |
1134 | //\r | |
b1bfdd65 LE |
1135 | // If Width is bigger than the 64-bit mode width, then the specified\r |
1136 | // register can not be accessed\r | |
4036b4e5 PB |
1137 | //\r |
1138 | if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {\r | |
1139 | return EFI_INVALID_PARAMETER;\r | |
1140 | }\r | |
1141 | \r | |
1142 | //\r | |
1143 | // Write lower 32-bits of SMM State register\r | |
1144 | //\r | |
b1bfdd65 LE |
1145 | CopyMem (\r |
1146 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,\r | |
1147 | Buffer,\r | |
1148 | MIN (4, Width)\r | |
1149 | );\r | |
4036b4e5 PB |
1150 | if (Width >= 4) {\r |
1151 | //\r | |
1152 | // Write upper 32-bits of SMM State register\r | |
1153 | //\r | |
b1bfdd65 LE |
1154 | CopyMem (\r |
1155 | (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,\r | |
1156 | (UINT8 *)Buffer + 4,\r | |
1157 | Width - 4\r | |
1158 | );\r | |
4036b4e5 PB |
1159 | }\r |
1160 | }\r | |
1161 | return EFI_SUCCESS;\r | |
86d71589 PB |
1162 | }\r |
1163 | \r | |
1164 | /**\r | |
1165 | This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r | |
1166 | notification is completely processed.\r | |
1167 | **/\r | |
1168 | VOID\r | |
1169 | EFIAPI\r | |
1170 | SmmCpuFeaturesCompleteSmmReadyToLock (\r | |
1171 | VOID\r | |
1172 | )\r | |
1173 | {\r | |
1174 | }\r | |
1175 | \r | |
1176 | /**\r | |
b1bfdd65 LE |
1177 | This API provides a method for a CPU to allocate a specific region for\r |
1178 | storing page tables.\r | |
86d71589 PB |
1179 | \r |
1180 | This API can be called more once to allocate memory for page tables.\r | |
1181 | \r | |
b1bfdd65 LE |
1182 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns\r |
1183 | a pointer to the allocated buffer. The buffer returned is aligned on a 4KB\r | |
1184 | boundary. If Pages is 0, then NULL is returned. If there is not enough\r | |
1185 | memory remaining to satisfy the request, then NULL is returned.\r | |
86d71589 | 1186 | \r |
b1bfdd65 LE |
1187 | This function can also return NULL if there is no preference on where the\r |
1188 | page tables are allocated in SMRAM.\r | |
86d71589 PB |
1189 | \r |
1190 | @param Pages The number of 4 KB pages to allocate.\r | |
1191 | \r | |
1192 | @return A pointer to the allocated buffer for page tables.\r | |
1193 | @retval NULL Fail to allocate a specific region for storing page tables,\r | |
b1bfdd65 LE |
1194 | Or there is no preference on where the page tables are\r |
1195 | allocated in SMRAM.\r | |
86d71589 PB |
1196 | \r |
1197 | **/\r | |
1198 | VOID *\r | |
1199 | EFIAPI\r | |
1200 | SmmCpuFeaturesAllocatePageTableMemory (\r | |
1201 | IN UINTN Pages\r | |
1202 | )\r | |
1203 | {\r | |
1204 | return NULL;\r | |
1205 | }\r | |
1206 | \r |