[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

/**@file\r
  Platform PEI driver\r
\r
  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
  { EfiACPIMemoryNVS,       0x004 },\r
  { EfiACPIReclaimMemory,   0x008 },\r
  { EfiReservedMemoryType,  0x004 },\r
  { EfiRuntimeServicesData, 0x024 },\r
  { EfiRuntimeServicesCode, 0x030 },\r
  { EfiBootServicesCode,    0x180 },\r
  { EfiBootServicesData,    0xF00 },\r
  { EfiMaxMemoryType,       0x000 }\r
};\r
\r
\r
EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gEfiPeiMasterBootModePpiGuid,\r
    NULL\r
  }\r
};\r
\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_RESERVED,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddIoMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddUntestedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddUntestedMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
VOID\r
MemMapInitialization (\r
  VOID\r
  )\r
{\r
  //\r
  // Create Memory Type Information HOB\r
  //\r
  BuildGuidDataHob (\r
    &gEfiMemoryTypeInformationGuid,\r
    mDefaultMemoryTypeInformation,\r
    sizeof(mDefaultMemoryTypeInformation)\r
    );\r
\r
  //\r
  // Add PCI IO Port space available for PCI resource allocations.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_IO,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
    0xC000,\r
    0x4000\r
    );\r
\r
  //\r
  // Video memory + Legacy BIOS region\r
  //\r
  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
  if (!mXen) {\r
    UINT32  TopOfLowRam;\r
    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
\r
    //\r
    // address       purpose   size\r
    // ------------  --------  -------------------------\r
    // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
    // 0xFC000000    gap                           44 MB\r
    // 0xFEC00000    IO-APIC                        4 KB\r
    // 0xFEC01000    gap                         1020 KB\r
    // 0xFED00000    HPET                           1 KB\r
    // 0xFED00400    gap                         1023 KB\r
    // 0xFEE00000    LAPIC                          1 MB\r
    //\r
    AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
                         BASE_2GB : TopOfLowRam, 0xFC000000);\r
    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
    AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
    AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
  }\r
}\r
\r
\r
VOID\r
MiscInitialization (\r
  VOID\r
  )\r
{\r
  //\r
  // Disable A20 Mask\r
  //\r
  IoOr8 (0x92, BIT1);\r
\r
  //\r
  // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
  //\r
  BuildCpuHob (36, 16);\r
\r
  //\r
  // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
  // example by Xen) and skip the setup here. This matches the logic in\r
  // AcpiTimerLibConstructor ().\r
  //\r
  if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
    //\r
    // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
    // 1. set PMBA\r
    //\r
    PciAndThenOr32 (\r
      PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
      (UINT32) ~0xFFC0,\r
      PcdGet16 (PcdAcpiPmBaseAddress)\r
      );\r
\r
    //\r
    // 2. set PCICMD/IOSE\r
    //\r
    PciOr8 (\r
      PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
      EFI_PCI_COMMAND_IO_SPACE\r
      );\r
\r
    //\r
    // 3. set PMREGMISC/PMIOSE\r
    //\r
    PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
  }\r
}\r
\r
\r
VOID\r
BootModeInitialization (\r
  )\r
{\r
  EFI_STATUS Status;\r
\r
  Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = PeiServicesInstallPpi (mPpiBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
VOID\r
ReserveEmuVariableNvStore (\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS VariableStore;\r
\r
  //\r
  // Allocate storage for NV variables early on so it will be\r
  // at a consistent address.  Since VM memory is preserved\r
  // across reboots, this allows the NV variable storage to survive\r
  // a VM reboot.\r
  //\r
  VariableStore =\r
    (EFI_PHYSICAL_ADDRESS)(UINTN)\r
      AllocateAlignedRuntimePages (\r
        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
        );\r
  DEBUG ((EFI_D_INFO,\r
          "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
          VariableStore,\r
          (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
        ));\r
  PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
}\r
\r
\r
VOID\r
DebugDumpCmos (\r
  VOID\r
  )\r
{\r
  UINTN  Loop;\r
\r
  DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
  for (Loop = 0; Loop < 0x80; Loop++) {\r
    if ((Loop % 0x10) == 0) {\r
      DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
    }\r
    DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
    if ((Loop % 0x10) == 0xf) {\r
      DEBUG ((EFI_D_INFO, "\n"));\r
    }\r
  }\r
}\r
\r
\r
/**\r
  Perform Platform PEI initialization.\r
\r
  @param  FileHandle      Handle of the file being invoked.\r
  @param  PeiServices     Describes the list of possible PEI Services.\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePlatform (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
  DebugDumpCmos ();\r
\r
  XenDetect ();\r
\r
  BootModeInitialization ();\r
\r
  PublishPeiMemory ();\r
\r
  InitializeRamRegions ();\r
\r
  if (mXen) {\r
    DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
    InitializeXen ();\r
  }\r
\r
  ReserveEmuVariableNvStore ();\r
\r
  PeiFvInitialization ();\r
\r
  MemMapInitialization ();\r
\r
  MiscInitialization ();\r
\r
  return EFI_SUCCESS;\r
}\r
Commit	Line	Data
49ba9447	1	/**@file\r
	2	Platform PEI driver\r
	3	\r
869b17cc	4	Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
eec7d420	5	Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
eec7d420	6	\r
56d7640a	7	This program and the accompanying materials\r
49ba9447	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	//\r
	18	// The package level header files this module uses\r
	19	//\r
	20	#include <PiPei.h>\r
	21	\r
	22	//\r
	23	// The Library classes this module consumes\r
	24	//\r
	25	#include <Library/DebugLib.h>\r
	26	#include <Library/HobLib.h>\r
	27	#include <Library/IoLib.h>\r
77ba993c	28	#include <Library/MemoryAllocationLib.h>\r
77ba993c	29	#include <Library/PcdLib.h>\r
49ba9447	30	#include <Library/PciLib.h>\r
49ba9447	31	#include <Library/PeimEntryPoint.h>\r
9ed65b10	32	#include <Library/PeiServicesLib.h>\r
49ba9447	33	#include <Library/ResourcePublicationLib.h>\r
49ba9447	34	#include <Guid/MemoryTypeInformation.h>\r
9ed65b10	35	#include <Ppi/MasterBootMode.h>\r
931a0c74	36	#include <IndustryStandard/Pci22.h>\r
49ba9447	37	\r
49ba9447	38	#include "Platform.h"\r
3ca15914	39	#include "Cmos.h"\r
49ba9447	40	\r
	41	EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
	42	{ EfiACPIMemoryNVS, 0x004 },\r
991d9563	43	{ EfiACPIReclaimMemory, 0x008 },\r
55cdb67a	44	{ EfiReservedMemoryType, 0x004 },\r
991d9563	45	{ EfiRuntimeServicesData, 0x024 },\r
	46	{ EfiRuntimeServicesCode, 0x030 },\r
	47	{ EfiBootServicesCode, 0x180 },\r
	48	{ EfiBootServicesData, 0xF00 },\r
49ba9447	49	{ EfiMaxMemoryType, 0x000 }\r
	50	};\r
	51	\r
	52	\r
9ed65b10	53	EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
	54	{\r
	55	EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
	56	&gEfiPeiMasterBootModePpiGuid,\r
	57	NULL\r
	58	}\r
	59	};\r
	60	\r
	61	\r
49ba9447	62	VOID\r
	63	AddIoMemoryBaseSizeHob (\r
	64	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	65	UINT64 MemorySize\r
	66	)\r
	67	{\r
991d9563	68	BuildResourceDescriptorHob (\r
991d9563	69	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447	70	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	71	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	72	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
991d9563	73	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	74	MemoryBase,\r
	75	MemorySize\r
	76	);\r
	77	}\r
	78	\r
eec7d420	79	VOID\r
	80	AddReservedMemoryBaseSizeHob (\r
	81	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	82	UINT64 MemorySize\r
	83	)\r
	84	{\r
	85	BuildResourceDescriptorHob (\r
	86	EFI_RESOURCE_MEMORY_RESERVED,\r
	87	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	88	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	89	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	90	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
	91	MemoryBase,\r
	92	MemorySize\r
	93	);\r
	94	}\r
49ba9447	95	\r
	96	VOID\r
	97	AddIoMemoryRangeHob (\r
	98	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	99	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	100	)\r
	101	{\r
	102	AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	103	}\r
	104	\r
	105	\r
	106	VOID\r
	107	AddMemoryBaseSizeHob (\r
	108	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	109	UINT64 MemorySize\r
	110	)\r
	111	{\r
991d9563	112	BuildResourceDescriptorHob (\r
991d9563	113	EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447	114	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	115	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	116	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	117	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	118	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	119	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE \|\r
991d9563	120	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	121	MemoryBase,\r
	122	MemorySize\r
	123	);\r
	124	}\r
	125	\r
	126	\r
	127	VOID\r
	128	AddMemoryRangeHob (\r
	129	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	130	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	131	)\r
	132	{\r
	133	AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	134	}\r
	135	\r
c0e10976	136	\r
	137	VOID\r
	138	AddUntestedMemoryBaseSizeHob (\r
	139	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	140	UINT64 MemorySize\r
	141	)\r
	142	{\r
	143	BuildResourceDescriptorHob (\r
	144	EFI_RESOURCE_SYSTEM_MEMORY,\r
	145	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	146	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	147	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	148	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	149	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	150	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
	151	MemoryBase,\r
	152	MemorySize\r
	153	);\r
	154	}\r
	155	\r
	156	\r
	157	VOID\r
	158	AddUntestedMemoryRangeHob (\r
	159	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	160	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	161	)\r
	162	{\r
	163	AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	164	}\r
	165	\r
bb6a9a93	166	VOID\r
4b455f7b	167	MemMapInitialization (\r
bb6a9a93 WL	168	VOID\r
	169	)\r
	170	{\r
bb6a9a93 WL	171	//\r
	172	// Create Memory Type Information HOB\r
	173	//\r
	174	BuildGuidDataHob (\r
	175	&gEfiMemoryTypeInformationGuid,\r
	176	mDefaultMemoryTypeInformation,\r
	177	sizeof(mDefaultMemoryTypeInformation)\r
	178	);\r
	179	\r
	180	//\r
	181	// Add PCI IO Port space available for PCI resource allocations.\r
	182	//\r
	183	BuildResourceDescriptorHob (\r
	184	EFI_RESOURCE_IO,\r
	185	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	186	EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
	187	0xC000,\r
	188	0x4000\r
	189	);\r
	190	\r
	191	//\r
	192	// Video memory + Legacy BIOS region\r
	193	//\r
	194	AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
	195	\r
4b455f7b JJ	196	if (!mXen) {\r
	197	UINT32 TopOfLowRam;\r
	198	TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
49ba9447	199	\r
4b455f7b JJ	200	//\r
	201	// address purpose size\r
	202	// ------------ -------- -------------------------\r
	203	// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
	204	// 0xFC000000 gap 44 MB\r
	205	// 0xFEC00000 IO-APIC 4 KB\r
	206	// 0xFEC01000 gap 1020 KB\r
	207	// 0xFED00000 HPET 1 KB\r
	208	// 0xFED00400 gap 1023 KB\r
	209	// 0xFEE00000 LAPIC 1 MB\r
	210	//\r
	211	AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
	212	BASE_2GB : TopOfLowRam, 0xFC000000);\r
	213	AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
	214	AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
	215	AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
4b455f7b	216	}\r
49ba9447	217	}\r
	218	\r
	219	\r
	220	VOID\r
	221	MiscInitialization (\r
0e20a186	222	VOID\r
49ba9447	223	)\r
	224	{\r
	225	//\r
	226	// Disable A20 Mask\r
	227	//\r
55cdb67a	228	IoOr8 (0x92, BIT1);\r
49ba9447	229	\r
	230	//\r
	231	// Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
	232	//\r
	233	BuildCpuHob (36, 16);\r
c756b2ab	234	\r
0e20a186	235	//\r
	236	// If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
	237	// example by Xen) and skip the setup here. This matches the logic in\r
	238	// AcpiTimerLibConstructor ().\r
	239	//\r
	240	if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
eec7d420	241	//\r
931a0c74	242	// The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
931a0c74	243	// 1. set PMBA\r
eec7d420	244	//\r
931a0c74	245	PciAndThenOr32 (\r
	246	PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
	247	(UINT32) ~0xFFC0,\r
	248	PcdGet16 (PcdAcpiPmBaseAddress)\r
	249	);\r
	250	\r
	251	//\r
	252	// 2. set PCICMD/IOSE\r
	253	//\r
	254	PciOr8 (\r
	255	PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
	256	EFI_PCI_COMMAND_IO_SPACE\r
	257	);\r
	258	\r
	259	//\r
	260	// 3. set PMREGMISC/PMIOSE\r
	261	//\r
	262	PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
eec7d420	263	}\r
49ba9447	264	}\r
	265	\r
	266	\r
9ed65b10	267	VOID\r
	268	BootModeInitialization (\r
	269	)\r
	270	{\r
667bf1e4	271	EFI_STATUS Status;\r
	272	\r
	273	Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
	274	ASSERT_EFI_ERROR (Status);\r
	275	\r
	276	Status = PeiServicesInstallPpi (mPpiBootMode);\r
	277	ASSERT_EFI_ERROR (Status);\r
9ed65b10	278	}\r
	279	\r
	280	\r
77ba993c	281	VOID\r
	282	ReserveEmuVariableNvStore (\r
	283	)\r
	284	{\r
	285	EFI_PHYSICAL_ADDRESS VariableStore;\r
	286	\r
	287	//\r
	288	// Allocate storage for NV variables early on so it will be\r
	289	// at a consistent address. Since VM memory is preserved\r
	290	// across reboots, this allows the NV variable storage to survive\r
	291	// a VM reboot.\r
	292	//\r
	293	VariableStore =\r
	294	(EFI_PHYSICAL_ADDRESS)(UINTN)\r
9edb2933	295	AllocateAlignedRuntimePages (\r
cce992ac WL	296	EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
cce992ac WL	297	PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1	298	);\r
77ba993c	299	DEBUG ((EFI_D_INFO,\r
	300	"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
	301	VariableStore,\r
29a3f139	302	(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c	303	));\r
	304	PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
	305	}\r
	306	\r
	307	\r
3ca15914	308	VOID\r
	309	DebugDumpCmos (\r
	310	VOID\r
	311	)\r
	312	{\r
	313	UINTN Loop;\r
	314	\r
	315	DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
	316	\r
	317	for (Loop = 0; Loop < 0x80; Loop++) {\r
	318	if ((Loop % 0x10) == 0) {\r
	319	DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
	320	}\r
	321	DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
	322	if ((Loop % 0x10) == 0xf) {\r
	323	DEBUG ((EFI_D_INFO, "\n"));\r
	324	}\r
	325	}\r
	326	}\r
	327	\r
	328	\r
49ba9447	329	/**\r
	330	Perform Platform PEI initialization.\r
	331	\r
	332	@param FileHandle Handle of the file being invoked.\r
	333	@param PeiServices Describes the list of possible PEI Services.\r
	334	\r
	335	@return EFI_SUCCESS The PEIM initialized successfully.\r
	336	\r
	337	**/\r
	338	EFI_STATUS\r
	339	EFIAPI\r
	340	InitializePlatform (\r
	341	IN EFI_PEI_FILE_HANDLE FileHandle,\r
	342	IN CONST EFI_PEI_SERVICES **PeiServices\r
	343	)\r
	344	{\r
	345	DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
	346	\r
3ca15914	347	DebugDumpCmos ();\r
3ca15914	348	\r
b98b4941	349	XenDetect ();\r
c7ea55b9	350	\r
869b17cc JJ	351	BootModeInitialization ();\r
869b17cc JJ	352	\r
f76e9eba JJ	353	PublishPeiMemory ();\r
f76e9eba JJ	354	\r
2818c158	355	InitializeRamRegions ();\r
49ba9447	356	\r
b621bb0a	357	if (mXen) {\r
c7ea55b9	358	DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
b98b4941	359	InitializeXen ();\r
c7ea55b9	360	}\r
eec7d420	361	\r
77ba993c	362	ReserveEmuVariableNvStore ();\r
77ba993c	363	\r
49ba9447	364	PeiFvInitialization ();\r
49ba9447	365	\r
4b455f7b	366	MemMapInitialization ();\r
49ba9447	367	\r
0e20a186	368	MiscInitialization ();\r
49ba9447	369	\r
	370	return EFI_SUCCESS;\r
	371	}\r