Commit | Line | Data |
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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
869b17cc | 4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
56d7640a | 7 | This program and the accompanying materials\r |
49ba9447 | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
5133d1f1 | 25 | #include <Library/BaseLib.h>\r |
49ba9447 | 26 | #include <Library/DebugLib.h>\r |
27 | #include <Library/HobLib.h>\r | |
28 | #include <Library/IoLib.h>\r | |
77ba993c | 29 | #include <Library/MemoryAllocationLib.h>\r |
30 | #include <Library/PcdLib.h>\r | |
49ba9447 | 31 | #include <Library/PciLib.h>\r |
32 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 33 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 34 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 35 | #include <Library/ResourcePublicationLib.h>\r |
36 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 37 | #include <Ppi/MasterBootMode.h>\r |
931a0c74 | 38 | #include <IndustryStandard/Pci22.h>\r |
97380beb | 39 | #include <OvmfPlatforms.h>\r |
49ba9447 | 40 | \r |
41 | #include "Platform.h"\r | |
3ca15914 | 42 | #include "Cmos.h"\r |
49ba9447 | 43 | \r |
44 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
45 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 46 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 47 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 48 | { EfiRuntimeServicesData, 0x024 },\r |
49 | { EfiRuntimeServicesCode, 0x030 },\r | |
50 | { EfiBootServicesCode, 0x180 },\r | |
51 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 52 | { EfiMaxMemoryType, 0x000 }\r |
53 | };\r | |
54 | \r | |
55 | \r | |
9ed65b10 | 56 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
57 | {\r | |
58 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
59 | &gEfiPeiMasterBootModePpiGuid,\r | |
60 | NULL\r | |
61 | }\r | |
62 | };\r | |
63 | \r | |
64 | \r | |
589756c7 PA |
65 | UINT16 mHostBridgeDevId;\r |
66 | \r | |
979420df JJ |
67 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
68 | \r | |
7cdba634 JJ |
69 | BOOLEAN mS3Supported = FALSE;\r |
70 | \r | |
979420df | 71 | \r |
49ba9447 | 72 | VOID\r |
73 | AddIoMemoryBaseSizeHob (\r | |
74 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
75 | UINT64 MemorySize\r | |
76 | )\r | |
77 | {\r | |
991d9563 | 78 | BuildResourceDescriptorHob (\r |
79 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 80 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
81 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
82 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 83 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 84 | MemoryBase,\r |
85 | MemorySize\r | |
86 | );\r | |
87 | }\r | |
88 | \r | |
eec7d420 | 89 | VOID\r |
90 | AddReservedMemoryBaseSizeHob (\r | |
91 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
cdef34ec LE |
92 | UINT64 MemorySize,\r |
93 | BOOLEAN Cacheable\r | |
eec7d420 | 94 | )\r |
95 | {\r | |
96 | BuildResourceDescriptorHob (\r | |
97 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
98 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
100 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
cdef34ec LE |
101 | (Cacheable ?\r |
102 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
103 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
104 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
105 | 0\r | |
106 | ) |\r | |
eec7d420 | 107 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
108 | MemoryBase,\r | |
109 | MemorySize\r | |
110 | );\r | |
111 | }\r | |
49ba9447 | 112 | \r |
113 | VOID\r | |
114 | AddIoMemoryRangeHob (\r | |
115 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
116 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
117 | )\r | |
118 | {\r | |
119 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
120 | }\r | |
121 | \r | |
122 | \r | |
123 | VOID\r | |
124 | AddMemoryBaseSizeHob (\r | |
125 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
126 | UINT64 MemorySize\r | |
127 | )\r | |
128 | {\r | |
991d9563 | 129 | BuildResourceDescriptorHob (\r |
130 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 131 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
132 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
133 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
134 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
135 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
136 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 137 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 138 | MemoryBase,\r |
139 | MemorySize\r | |
140 | );\r | |
141 | }\r | |
142 | \r | |
143 | \r | |
144 | VOID\r | |
145 | AddMemoryRangeHob (\r | |
146 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
147 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
148 | )\r | |
149 | {\r | |
150 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
151 | }\r | |
152 | \r | |
c0e10976 | 153 | \r |
154 | VOID\r | |
155 | AddUntestedMemoryBaseSizeHob (\r | |
156 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
157 | UINT64 MemorySize\r | |
158 | )\r | |
159 | {\r | |
160 | BuildResourceDescriptorHob (\r | |
161 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
162 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
163 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
164 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
165 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
166 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
167 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r | |
168 | MemoryBase,\r | |
169 | MemorySize\r | |
170 | );\r | |
171 | }\r | |
172 | \r | |
173 | \r | |
174 | VOID\r | |
175 | AddUntestedMemoryRangeHob (\r | |
176 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
177 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
178 | )\r | |
179 | {\r | |
180 | AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
181 | }\r | |
182 | \r | |
bb6a9a93 | 183 | VOID\r |
4b455f7b | 184 | MemMapInitialization (\r |
bb6a9a93 WL |
185 | VOID\r |
186 | )\r | |
187 | {\r | |
bb6a9a93 WL |
188 | //\r |
189 | // Create Memory Type Information HOB\r | |
190 | //\r | |
191 | BuildGuidDataHob (\r | |
192 | &gEfiMemoryTypeInformationGuid,\r | |
193 | mDefaultMemoryTypeInformation,\r | |
194 | sizeof(mDefaultMemoryTypeInformation)\r | |
195 | );\r | |
196 | \r | |
197 | //\r | |
198 | // Add PCI IO Port space available for PCI resource allocations.\r | |
199 | //\r | |
200 | BuildResourceDescriptorHob (\r | |
201 | EFI_RESOURCE_IO,\r | |
202 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
203 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
e705f899 LE |
204 | PcdGet64 (PcdPciIoBase),\r |
205 | PcdGet64 (PcdPciIoSize)\r | |
bb6a9a93 WL |
206 | );\r |
207 | \r | |
208 | //\r | |
209 | // Video memory + Legacy BIOS region\r | |
210 | //\r | |
211 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
212 | \r | |
4b455f7b JJ |
213 | if (!mXen) {\r |
214 | UINT32 TopOfLowRam;\r | |
7b8fe635 | 215 | UINT64 PciExBarBase;\r |
c68d3a69 | 216 | UINT32 PciBase;\r |
03845e90 | 217 | UINT32 PciSize;\r |
c68d3a69 | 218 | \r |
4b455f7b | 219 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r |
c68d3a69 LE |
220 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
221 | //\r | |
7b8fe635 LE |
222 | // The MMCONFIG area is expected to fall between the top of low RAM and\r |
223 | // the base of the 32-bit PCI host aperture.\r | |
c68d3a69 | 224 | //\r |
7b8fe635 LE |
225 | PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r |
226 | ASSERT (TopOfLowRam <= PciExBarBase);\r | |
227 | ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r | |
228 | PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r | |
c68d3a69 LE |
229 | } else {\r |
230 | PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r | |
231 | }\r | |
49ba9447 | 232 | \r |
4b455f7b JJ |
233 | //\r |
234 | // address purpose size\r | |
235 | // ------------ -------- -------------------------\r | |
236 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
237 | // 0xFC000000 gap 44 MB\r | |
238 | // 0xFEC00000 IO-APIC 4 KB\r | |
239 | // 0xFEC01000 gap 1020 KB\r | |
240 | // 0xFED00000 HPET 1 KB\r | |
90721ba5 PA |
241 | // 0xFED00400 gap 111 KB\r |
242 | // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r | |
243 | // 0xFED20000 gap 896 KB\r | |
4b455f7b JJ |
244 | // 0xFEE00000 LAPIC 1 MB\r |
245 | //\r | |
03845e90 LE |
246 | PciSize = 0xFC000000 - PciBase;\r |
247 | AddIoMemoryBaseSizeHob (PciBase, PciSize);\r | |
248 | PcdSet64 (PcdPciMmio32Base, PciBase);\r | |
249 | PcdSet64 (PcdPciMmio32Size, PciSize);\r | |
4b455f7b JJ |
250 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r |
251 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
90721ba5 PA |
252 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r |
253 | AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r | |
7b8fe635 LE |
254 | //\r |
255 | // Note: there should be an\r | |
256 | //\r | |
257 | // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r | |
258 | //\r | |
259 | // call below, just like the one above for RCBA. However, Linux insists\r | |
260 | // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r | |
261 | // "reserved memory" -- Linux does not content itself with a simple gap\r | |
262 | // in the memory map wherever the MCFG ACPI table points to.\r | |
263 | //\r | |
264 | // This appears to be a safety measure. The PCI Firmware Specification\r | |
265 | // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r | |
266 | // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r | |
267 | // [...]". (Emphasis added here.)\r | |
268 | //\r | |
269 | // Normally we add memory resource descriptor HOBs in\r | |
270 | // QemuInitializeRam(), and pre-allocate from those with memory\r | |
271 | // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r | |
272 | // is most definitely not RAM; so, as an exception, cover it with\r | |
273 | // uncacheable reserved memory right here.\r | |
274 | //\r | |
275 | AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r | |
276 | BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r | |
277 | EfiReservedMemoryType);\r | |
90721ba5 | 278 | }\r |
4b455f7b | 279 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r |
4b455f7b | 280 | }\r |
49ba9447 | 281 | }\r |
282 | \r | |
ab081a50 LE |
283 | EFI_STATUS\r |
284 | GetNamedFwCfgBoolean (\r | |
285 | IN CHAR8 *FwCfgFileName,\r | |
286 | OUT BOOLEAN *Setting\r | |
287 | )\r | |
288 | {\r | |
289 | EFI_STATUS Status;\r | |
290 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
291 | UINTN FwCfgSize;\r | |
292 | UINT8 Value[3];\r | |
293 | \r | |
294 | Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r | |
295 | if (EFI_ERROR (Status)) {\r | |
296 | return Status;\r | |
297 | }\r | |
298 | if (FwCfgSize > sizeof Value) {\r | |
299 | return EFI_BAD_BUFFER_SIZE;\r | |
300 | }\r | |
301 | QemuFwCfgSelectItem (FwCfgItem);\r | |
302 | QemuFwCfgReadBytes (FwCfgSize, Value);\r | |
303 | \r | |
304 | if ((FwCfgSize == 1) ||\r | |
305 | (FwCfgSize == 2 && Value[1] == '\n') ||\r | |
306 | (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r | |
307 | switch (Value[0]) {\r | |
308 | case '0':\r | |
309 | case 'n':\r | |
310 | case 'N':\r | |
311 | *Setting = FALSE;\r | |
312 | return EFI_SUCCESS;\r | |
313 | \r | |
314 | case '1':\r | |
315 | case 'y':\r | |
316 | case 'Y':\r | |
317 | *Setting = TRUE;\r | |
318 | return EFI_SUCCESS;\r | |
319 | \r | |
320 | default:\r | |
321 | break;\r | |
322 | }\r | |
323 | }\r | |
324 | return EFI_PROTOCOL_ERROR;\r | |
325 | }\r | |
326 | \r | |
327 | #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r | |
328 | do { \\r | |
329 | BOOLEAN Setting; \\r | |
330 | \\r | |
331 | if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r | |
332 | "opt/ovmf/" #TokenName, &Setting))) { \\r | |
333 | PcdSetBool (TokenName, Setting); \\r | |
334 | } \\r | |
335 | } while (0)\r | |
336 | \r | |
337 | VOID\r | |
338 | NoexecDxeInitialization (\r | |
339 | VOID\r | |
340 | )\r | |
341 | {\r | |
342 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r | |
343 | UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r | |
344 | }\r | |
49ba9447 | 345 | \r |
7b8fe635 LE |
346 | VOID\r |
347 | PciExBarInitialization (\r | |
348 | VOID\r | |
349 | )\r | |
350 | {\r | |
351 | union {\r | |
352 | UINT64 Uint64;\r | |
353 | UINT32 Uint32[2];\r | |
354 | } PciExBarBase;\r | |
355 | \r | |
356 | //\r | |
357 | // We only support the 256MB size for the MMCONFIG area:\r | |
358 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
359 | //\r | |
360 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
361 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
362 | //\r | |
363 | // Note that (b) also ensures that the minimum address width we have\r | |
364 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
365 | // for DXE's page tables to cover the MMCONFIG area.\r | |
366 | //\r | |
367 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
368 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
369 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
370 | \r | |
371 | //\r | |
372 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
373 | //\r | |
374 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
375 | \r | |
376 | //\r | |
377 | // Program the high register. Then program the low register, setting the\r | |
378 | // MMCONFIG area size and enabling decoding at once.\r | |
379 | //\r | |
380 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
381 | PciWrite32 (\r | |
382 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
383 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
384 | );\r | |
385 | }\r | |
386 | \r | |
49ba9447 | 387 | VOID\r |
388 | MiscInitialization (\r | |
0e20a186 | 389 | VOID\r |
49ba9447 | 390 | )\r |
391 | {\r | |
97380beb GS |
392 | UINTN PmCmd;\r |
393 | UINTN Pmba;\r | |
e2ab3f81 GS |
394 | UINTN AcpiCtlReg;\r |
395 | UINT8 AcpiEnBit;\r | |
97380beb | 396 | \r |
49ba9447 | 397 | //\r |
398 | // Disable A20 Mask\r | |
399 | //\r | |
55cdb67a | 400 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 401 | \r |
402 | //\r | |
86a14b0a LE |
403 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r |
404 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
405 | // S3 resume as well, so we build it unconditionally.)\r | |
49ba9447 | 406 | //\r |
86a14b0a | 407 | BuildCpuHob (mPhysMemAddressWidth, 16);\r |
c756b2ab | 408 | \r |
97380beb | 409 | //\r |
589756c7 | 410 | // Determine platform type and save Host Bridge DID to PCD\r |
97380beb | 411 | //\r |
589756c7 | 412 | switch (mHostBridgeDevId) {\r |
97380beb | 413 | case INTEL_82441_DEVICE_ID:\r |
e2ab3f81 | 414 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r |
da372167 LE |
415 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r |
416 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r | |
417 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
97380beb GS |
418 | break;\r |
419 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
e2ab3f81 | 420 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r |
bc9d05d6 LE |
421 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r |
422 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r | |
423 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
97380beb GS |
424 | break;\r |
425 | default:\r | |
426 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
589756c7 | 427 | __FUNCTION__, mHostBridgeDevId));\r |
97380beb GS |
428 | ASSERT (FALSE);\r |
429 | return;\r | |
430 | }\r | |
589756c7 | 431 | PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r |
97380beb | 432 | \r |
0e20a186 | 433 | //\r |
e2ab3f81 GS |
434 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r |
435 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
436 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
0e20a186 | 437 | //\r |
e2ab3f81 | 438 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r |
eec7d420 | 439 | //\r |
e2ab3f81 | 440 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r |
931a0c74 | 441 | // 1. set PMBA\r |
eec7d420 | 442 | //\r |
97380beb | 443 | PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r |
931a0c74 | 444 | \r |
445 | //\r | |
446 | // 2. set PCICMD/IOSE\r | |
447 | //\r | |
97380beb | 448 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 449 | \r |
450 | //\r | |
e2ab3f81 | 451 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r |
931a0c74 | 452 | //\r |
e2ab3f81 | 453 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r |
eec7d420 | 454 | }\r |
90721ba5 PA |
455 | \r |
456 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
457 | //\r | |
458 | // Set Root Complex Register Block BAR\r | |
459 | //\r | |
460 | PciWrite32 (\r | |
461 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
462 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
463 | );\r | |
7b8fe635 LE |
464 | \r |
465 | //\r | |
466 | // Set PCI Express Register Range Base Address\r | |
467 | //\r | |
468 | PciExBarInitialization ();\r | |
90721ba5 | 469 | }\r |
49ba9447 | 470 | }\r |
471 | \r | |
472 | \r | |
9ed65b10 | 473 | VOID\r |
474 | BootModeInitialization (\r | |
8f5ca05b | 475 | VOID\r |
9ed65b10 | 476 | )\r |
477 | {\r | |
8f5ca05b LE |
478 | EFI_STATUS Status;\r |
479 | \r | |
480 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 481 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 482 | }\r |
9be75189 | 483 | CmosWrite8 (0xF, 0x00);\r |
667bf1e4 | 484 | \r |
979420df | 485 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 486 | ASSERT_EFI_ERROR (Status);\r |
487 | \r | |
488 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
489 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 490 | }\r |
491 | \r | |
492 | \r | |
77ba993c | 493 | VOID\r |
494 | ReserveEmuVariableNvStore (\r | |
495 | )\r | |
496 | {\r | |
497 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
498 | \r | |
499 | //\r | |
500 | // Allocate storage for NV variables early on so it will be\r | |
501 | // at a consistent address. Since VM memory is preserved\r | |
502 | // across reboots, this allows the NV variable storage to survive\r | |
503 | // a VM reboot.\r | |
504 | //\r | |
505 | VariableStore =\r | |
506 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
9edb2933 | 507 | AllocateAlignedRuntimePages (\r |
cce992ac WL |
508 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r |
509 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
27f58ea1 | 510 | );\r |
77ba993c | 511 | DEBUG ((EFI_D_INFO,\r |
512 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
513 | VariableStore,\r | |
29a3f139 | 514 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 515 | ));\r |
516 | PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
517 | }\r | |
518 | \r | |
519 | \r | |
3ca15914 | 520 | VOID\r |
521 | DebugDumpCmos (\r | |
522 | VOID\r | |
523 | )\r | |
524 | {\r | |
6394c35a | 525 | UINT32 Loop;\r |
3ca15914 | 526 | \r |
527 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
528 | \r | |
529 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
530 | if ((Loop % 0x10) == 0) {\r | |
531 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
532 | }\r | |
533 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
534 | if ((Loop % 0x10) == 0xf) {\r | |
535 | DEBUG ((EFI_D_INFO, "\n"));\r | |
536 | }\r | |
537 | }\r | |
538 | }\r | |
539 | \r | |
540 | \r | |
5133d1f1 LE |
541 | VOID\r |
542 | S3Verification (\r | |
543 | VOID\r | |
544 | )\r | |
545 | {\r | |
546 | #if defined (MDE_CPU_X64)\r | |
547 | if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r | |
548 | DEBUG ((EFI_D_ERROR,\r | |
549 | "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r | |
550 | DEBUG ((EFI_D_ERROR,\r | |
551 | "%a: Please disable S3 on the QEMU command line (see the README),\n",\r | |
552 | __FUNCTION__));\r | |
553 | DEBUG ((EFI_D_ERROR,\r | |
554 | "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r | |
555 | ASSERT (FALSE);\r | |
556 | CpuDeadLoop ();\r | |
557 | }\r | |
558 | #endif\r | |
559 | }\r | |
560 | \r | |
561 | \r | |
49ba9447 | 562 | /**\r |
563 | Perform Platform PEI initialization.\r | |
564 | \r | |
565 | @param FileHandle Handle of the file being invoked.\r | |
566 | @param PeiServices Describes the list of possible PEI Services.\r | |
567 | \r | |
568 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
569 | \r | |
570 | **/\r | |
571 | EFI_STATUS\r | |
572 | EFIAPI\r | |
573 | InitializePlatform (\r | |
574 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
575 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
576 | )\r | |
577 | {\r | |
578 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r | |
579 | \r | |
3ca15914 | 580 | DebugDumpCmos ();\r |
581 | \r | |
b98b4941 | 582 | XenDetect ();\r |
c7ea55b9 | 583 | \r |
7cdba634 JJ |
584 | if (QemuFwCfgS3Enabled ()) {\r |
585 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
586 | mS3Supported = TRUE;\r | |
587 | }\r | |
588 | \r | |
5133d1f1 | 589 | S3Verification ();\r |
869b17cc | 590 | BootModeInitialization ();\r |
bc89fe48 | 591 | AddressWidthInitialization ();\r |
869b17cc | 592 | \r |
f76e9eba JJ |
593 | PublishPeiMemory ();\r |
594 | \r | |
2818c158 | 595 | InitializeRamRegions ();\r |
49ba9447 | 596 | \r |
b621bb0a | 597 | if (mXen) {\r |
c7ea55b9 | 598 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 599 | InitializeXen ();\r |
c7ea55b9 | 600 | }\r |
eec7d420 | 601 | \r |
589756c7 PA |
602 | //\r |
603 | // Query Host Bridge DID\r | |
604 | //\r | |
605 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
606 | \r | |
bd386eaf JJ |
607 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
608 | ReserveEmuVariableNvStore ();\r | |
bd386eaf | 609 | PeiFvInitialization ();\r |
bd386eaf | 610 | MemMapInitialization ();\r |
ab081a50 | 611 | NoexecDxeInitialization ();\r |
bd386eaf | 612 | }\r |
49ba9447 | 613 | \r |
0e20a186 | 614 | MiscInitialization ();\r |
49ba9447 | 615 | \r |
616 | return EFI_SUCCESS;\r | |
617 | }\r |