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OvmfPkg: enable PIIX4 IO space in the PEI phase
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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49ba9447 1/**@file\r
2 Platform PEI driver\r
3\r
eec7d420 4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
56d7640a 7 This program and the accompanying materials\r
49ba9447 8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
25#include <Library/DebugLib.h>\r
26#include <Library/HobLib.h>\r
27#include <Library/IoLib.h>\r
77ba993c 28#include <Library/MemoryAllocationLib.h>\r
29#include <Library/PcdLib.h>\r
49ba9447 30#include <Library/PciLib.h>\r
31#include <Library/PeimEntryPoint.h>\r
9ed65b10 32#include <Library/PeiServicesLib.h>\r
49ba9447 33#include <Library/ResourcePublicationLib.h>\r
34#include <Guid/MemoryTypeInformation.h>\r
9ed65b10 35#include <Ppi/MasterBootMode.h>\r
931a0c74 36#include <IndustryStandard/Pci22.h>\r
49ba9447 37\r
38#include "Platform.h"\r
3ca15914 39#include "Cmos.h"\r
49ba9447 40\r
41EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
42 { EfiACPIMemoryNVS, 0x004 },\r
991d9563 43 { EfiACPIReclaimMemory, 0x008 },\r
55cdb67a 44 { EfiReservedMemoryType, 0x004 },\r
991d9563 45 { EfiRuntimeServicesData, 0x024 },\r
46 { EfiRuntimeServicesCode, 0x030 },\r
47 { EfiBootServicesCode, 0x180 },\r
48 { EfiBootServicesData, 0xF00 },\r
49ba9447 49 { EfiMaxMemoryType, 0x000 }\r
50};\r
51\r
52\r
9ed65b10 53EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
54 {\r
55 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
56 &gEfiPeiMasterBootModePpiGuid,\r
57 NULL\r
58 }\r
59};\r
60\r
61\r
49ba9447 62VOID\r
63AddIoMemoryBaseSizeHob (\r
64 EFI_PHYSICAL_ADDRESS MemoryBase,\r
65 UINT64 MemorySize\r
66 )\r
67{\r
991d9563 68 BuildResourceDescriptorHob (\r
69 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447 70 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
71 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
72 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
991d9563 73 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 74 MemoryBase,\r
75 MemorySize\r
76 );\r
77}\r
78\r
eec7d420 79VOID\r
80AddReservedMemoryBaseSizeHob (\r
81 EFI_PHYSICAL_ADDRESS MemoryBase,\r
82 UINT64 MemorySize\r
83 )\r
84{\r
85 BuildResourceDescriptorHob (\r
86 EFI_RESOURCE_MEMORY_RESERVED,\r
87 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
88 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
89 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
90 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
91 MemoryBase,\r
92 MemorySize\r
93 );\r
94}\r
49ba9447 95\r
96VOID\r
97AddIoMemoryRangeHob (\r
98 EFI_PHYSICAL_ADDRESS MemoryBase,\r
99 EFI_PHYSICAL_ADDRESS MemoryLimit\r
100 )\r
101{\r
102 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
103}\r
104\r
105\r
106VOID\r
107AddMemoryBaseSizeHob (\r
108 EFI_PHYSICAL_ADDRESS MemoryBase,\r
109 UINT64 MemorySize\r
110 )\r
111{\r
991d9563 112 BuildResourceDescriptorHob (\r
113 EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447 114 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
115 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
116 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
117 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
118 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
119 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
991d9563 120 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 121 MemoryBase,\r
122 MemorySize\r
123 );\r
124}\r
125\r
126\r
127VOID\r
128AddMemoryRangeHob (\r
129 EFI_PHYSICAL_ADDRESS MemoryBase,\r
130 EFI_PHYSICAL_ADDRESS MemoryLimit\r
131 )\r
132{\r
133 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
134}\r
135\r
c0e10976 136\r
137VOID\r
138AddUntestedMemoryBaseSizeHob (\r
139 EFI_PHYSICAL_ADDRESS MemoryBase,\r
140 UINT64 MemorySize\r
141 )\r
142{\r
143 BuildResourceDescriptorHob (\r
144 EFI_RESOURCE_SYSTEM_MEMORY,\r
145 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
146 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
147 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
148 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
149 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
150 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
151 MemoryBase,\r
152 MemorySize\r
153 );\r
154}\r
155\r
156\r
157VOID\r
158AddUntestedMemoryRangeHob (\r
159 EFI_PHYSICAL_ADDRESS MemoryBase,\r
160 EFI_PHYSICAL_ADDRESS MemoryLimit\r
161 )\r
162{\r
163 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
164}\r
165\r
166\r
49ba9447 167VOID\r
168MemMapInitialization (\r
55cdb67a 169 EFI_PHYSICAL_ADDRESS TopOfMemory\r
49ba9447 170 )\r
171{\r
172 //\r
173 // Create Memory Type Information HOB\r
174 //\r
175 BuildGuidDataHob (\r
176 &gEfiMemoryTypeInformationGuid,\r
177 mDefaultMemoryTypeInformation,\r
178 sizeof(mDefaultMemoryTypeInformation)\r
179 );\r
180\r
991d9563 181 //\r
182 // Add PCI IO Port space available for PCI resource allocations.\r
183 //\r
184 BuildResourceDescriptorHob (\r
185 EFI_RESOURCE_IO,\r
eec7d420 186 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
187 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
188 0xC000,\r
189 0x4000\r
991d9563 190 );\r
191\r
192 //\r
cb678aa8 193 // Video memory + Legacy BIOS region\r
49ba9447 194 //\r
cb678aa8 195 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
49ba9447 196\r
197 //\r
cb678aa8 198 // address purpose size\r
199 // ------------ -------- -------------------------\r
67fe5bed 200 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
201 // 0xFC000000 gap 44 MB\r
cb678aa8 202 // 0xFEC00000 IO-APIC 4 KB\r
203 // 0xFEC01000 gap 1020 KB\r
204 // 0xFED00000 HPET 1 KB\r
205 // 0xFED00400 gap 1023 KB\r
206 // 0xFEE00000 LAPIC 1 MB\r
49ba9447 207 //\r
67fe5bed 208 AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
cb678aa8 209 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
210 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
211 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
49ba9447 212}\r
213\r
214\r
215VOID\r
216MiscInitialization (\r
eec7d420 217 BOOLEAN Xen\r
49ba9447 218 )\r
219{\r
220 //\r
221 // Disable A20 Mask\r
222 //\r
55cdb67a 223 IoOr8 (0x92, BIT1);\r
49ba9447 224\r
225 //\r
226 // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
227 //\r
228 BuildCpuHob (36, 16);\r
c756b2ab 229\r
eec7d420 230 if (!Xen) {\r
231 //\r
931a0c74 232 // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
233 // 1. set PMBA\r
eec7d420 234 //\r
931a0c74 235 PciAndThenOr32 (\r
236 PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
237 (UINT32) ~0xFFC0,\r
238 PcdGet16 (PcdAcpiPmBaseAddress)\r
239 );\r
240\r
241 //\r
242 // 2. set PCICMD/IOSE\r
243 //\r
244 PciOr8 (\r
245 PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
246 EFI_PCI_COMMAND_IO_SPACE\r
247 );\r
248\r
249 //\r
250 // 3. set PMREGMISC/PMIOSE\r
251 //\r
252 PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
eec7d420 253 }\r
49ba9447 254}\r
255\r
256\r
9ed65b10 257VOID\r
258BootModeInitialization (\r
259 )\r
260{\r
667bf1e4 261 EFI_STATUS Status;\r
262\r
263 Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
264 ASSERT_EFI_ERROR (Status);\r
265\r
266 Status = PeiServicesInstallPpi (mPpiBootMode);\r
267 ASSERT_EFI_ERROR (Status);\r
9ed65b10 268}\r
269\r
270\r
77ba993c 271VOID\r
272ReserveEmuVariableNvStore (\r
273 )\r
274{\r
275 EFI_PHYSICAL_ADDRESS VariableStore;\r
276\r
277 //\r
278 // Allocate storage for NV variables early on so it will be\r
279 // at a consistent address. Since VM memory is preserved\r
280 // across reboots, this allows the NV variable storage to survive\r
281 // a VM reboot.\r
282 //\r
283 VariableStore =\r
284 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
27f58ea1 285 AllocateRuntimePool (\r
29a3f139 286 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1 287 );\r
77ba993c 288 DEBUG ((EFI_D_INFO,\r
289 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
290 VariableStore,\r
29a3f139 291 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c 292 ));\r
293 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
294}\r
295\r
296\r
3ca15914 297VOID\r
298DebugDumpCmos (\r
299 VOID\r
300 )\r
301{\r
302 UINTN Loop;\r
303\r
304 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
305\r
306 for (Loop = 0; Loop < 0x80; Loop++) {\r
307 if ((Loop % 0x10) == 0) {\r
308 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
309 }\r
310 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
311 if ((Loop % 0x10) == 0xf) {\r
312 DEBUG ((EFI_D_INFO, "\n"));\r
313 }\r
314 }\r
315}\r
316\r
317\r
49ba9447 318/**\r
319 Perform Platform PEI initialization.\r
320\r
321 @param FileHandle Handle of the file being invoked.\r
322 @param PeiServices Describes the list of possible PEI Services.\r
323\r
324 @return EFI_SUCCESS The PEIM initialized successfully.\r
325\r
326**/\r
327EFI_STATUS\r
328EFIAPI\r
329InitializePlatform (\r
330 IN EFI_PEI_FILE_HANDLE FileHandle,\r
331 IN CONST EFI_PEI_SERVICES **PeiServices\r
332 )\r
333{\r
eec7d420 334 EFI_STATUS Status;\r
55cdb67a 335 EFI_PHYSICAL_ADDRESS TopOfMemory;\r
eec7d420 336 BOOLEAN Xen;\r
55cdb67a 337\r
49ba9447 338 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
339\r
3ca15914 340 DebugDumpCmos ();\r
341\r
55cdb67a 342 TopOfMemory = MemDetect ();\r
49ba9447 343\r
eec7d420 344 Status = InitializeXen ();\r
345 Xen = EFI_ERROR (Status) ? FALSE : TRUE;\r
346\r
77ba993c 347 ReserveEmuVariableNvStore ();\r
348\r
49ba9447 349 PeiFvInitialization ();\r
350\r
55cdb67a 351 MemMapInitialization (TopOfMemory);\r
49ba9447 352\r
eec7d420 353 MiscInitialization (Xen);\r
49ba9447 354\r
9ed65b10 355 BootModeInitialization ();\r
356\r
49ba9447 357 return EFI_SUCCESS;\r
358}\r
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