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OvmfPkg/PlatformPei: Set PcdPciDisableBusEnumeration in InitializeXen
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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49ba9447 1/**@file\r
2 Platform PEI driver\r
3\r
869b17cc 4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
eec7d420 5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
56d7640a 7 This program and the accompanying materials\r
49ba9447 8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
25#include <Library/DebugLib.h>\r
26#include <Library/HobLib.h>\r
27#include <Library/IoLib.h>\r
77ba993c 28#include <Library/MemoryAllocationLib.h>\r
29#include <Library/PcdLib.h>\r
49ba9447 30#include <Library/PciLib.h>\r
31#include <Library/PeimEntryPoint.h>\r
9ed65b10 32#include <Library/PeiServicesLib.h>\r
49ba9447 33#include <Library/ResourcePublicationLib.h>\r
34#include <Guid/MemoryTypeInformation.h>\r
9ed65b10 35#include <Ppi/MasterBootMode.h>\r
931a0c74 36#include <IndustryStandard/Pci22.h>\r
49ba9447 37\r
38#include "Platform.h"\r
3ca15914 39#include "Cmos.h"\r
49ba9447 40\r
41EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
42 { EfiACPIMemoryNVS, 0x004 },\r
991d9563 43 { EfiACPIReclaimMemory, 0x008 },\r
55cdb67a 44 { EfiReservedMemoryType, 0x004 },\r
991d9563 45 { EfiRuntimeServicesData, 0x024 },\r
46 { EfiRuntimeServicesCode, 0x030 },\r
47 { EfiBootServicesCode, 0x180 },\r
48 { EfiBootServicesData, 0xF00 },\r
49ba9447 49 { EfiMaxMemoryType, 0x000 }\r
50};\r
51\r
52\r
9ed65b10 53EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
54 {\r
55 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
56 &gEfiPeiMasterBootModePpiGuid,\r
57 NULL\r
58 }\r
59};\r
60\r
61\r
49ba9447 62VOID\r
63AddIoMemoryBaseSizeHob (\r
64 EFI_PHYSICAL_ADDRESS MemoryBase,\r
65 UINT64 MemorySize\r
66 )\r
67{\r
991d9563 68 BuildResourceDescriptorHob (\r
69 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447 70 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
71 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
72 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
991d9563 73 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 74 MemoryBase,\r
75 MemorySize\r
76 );\r
77}\r
78\r
eec7d420 79VOID\r
80AddReservedMemoryBaseSizeHob (\r
81 EFI_PHYSICAL_ADDRESS MemoryBase,\r
82 UINT64 MemorySize\r
83 )\r
84{\r
85 BuildResourceDescriptorHob (\r
86 EFI_RESOURCE_MEMORY_RESERVED,\r
87 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
88 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
89 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
90 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
91 MemoryBase,\r
92 MemorySize\r
93 );\r
94}\r
49ba9447 95\r
96VOID\r
97AddIoMemoryRangeHob (\r
98 EFI_PHYSICAL_ADDRESS MemoryBase,\r
99 EFI_PHYSICAL_ADDRESS MemoryLimit\r
100 )\r
101{\r
102 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
103}\r
104\r
105\r
106VOID\r
107AddMemoryBaseSizeHob (\r
108 EFI_PHYSICAL_ADDRESS MemoryBase,\r
109 UINT64 MemorySize\r
110 )\r
111{\r
991d9563 112 BuildResourceDescriptorHob (\r
113 EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447 114 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
115 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
116 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
117 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
118 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
119 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
991d9563 120 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 121 MemoryBase,\r
122 MemorySize\r
123 );\r
124}\r
125\r
126\r
127VOID\r
128AddMemoryRangeHob (\r
129 EFI_PHYSICAL_ADDRESS MemoryBase,\r
130 EFI_PHYSICAL_ADDRESS MemoryLimit\r
131 )\r
132{\r
133 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
134}\r
135\r
c0e10976 136\r
137VOID\r
138AddUntestedMemoryBaseSizeHob (\r
139 EFI_PHYSICAL_ADDRESS MemoryBase,\r
140 UINT64 MemorySize\r
141 )\r
142{\r
143 BuildResourceDescriptorHob (\r
144 EFI_RESOURCE_SYSTEM_MEMORY,\r
145 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
146 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
147 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
148 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
149 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
150 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
151 MemoryBase,\r
152 MemorySize\r
153 );\r
154}\r
155\r
156\r
157VOID\r
158AddUntestedMemoryRangeHob (\r
159 EFI_PHYSICAL_ADDRESS MemoryBase,\r
160 EFI_PHYSICAL_ADDRESS MemoryLimit\r
161 )\r
162{\r
163 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
164}\r
165\r
bb6a9a93
WL		 166VOID\r
167XenMemMapInitialization (\r
168 VOID\r
169 )\r
170{\r
bb6a9a93
WL		 171 //\r
172 // Create Memory Type Information HOB\r
173 //\r
174 BuildGuidDataHob (\r
175 &gEfiMemoryTypeInformationGuid,\r
176 mDefaultMemoryTypeInformation,\r
177 sizeof(mDefaultMemoryTypeInformation)\r
178 );\r
179\r
180 //\r
181 // Add PCI IO Port space available for PCI resource allocations.\r
182 //\r
183 BuildResourceDescriptorHob (\r
184 EFI_RESOURCE_IO,\r
185 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
186 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
187 0xC000,\r
188 0x4000\r
189 );\r
190\r
191 //\r
192 // Video memory + Legacy BIOS region\r
193 //\r
194 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
195\r
18f31ada 196 XenPublishRamRegions ();\r
bb6a9a93
WL		 197}\r
198\r
c0e10976 199\r
49ba9447 200VOID\r
201MemMapInitialization (\r
55cdb67a 202 EFI_PHYSICAL_ADDRESS TopOfMemory\r
49ba9447 203 )\r
204{\r
205 //\r
206 // Create Memory Type Information HOB\r
207 //\r
208 BuildGuidDataHob (\r
209 &gEfiMemoryTypeInformationGuid,\r
210 mDefaultMemoryTypeInformation,\r
211 sizeof(mDefaultMemoryTypeInformation)\r
212 );\r
213\r
991d9563 214 //\r
215 // Add PCI IO Port space available for PCI resource allocations.\r
216 //\r
217 BuildResourceDescriptorHob (\r
218 EFI_RESOURCE_IO,\r
eec7d420 219 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
220 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
221 0xC000,\r
222 0x4000\r
991d9563 223 );\r
224\r
225 //\r
cb678aa8 226 // Video memory + Legacy BIOS region\r
49ba9447 227 //\r
cb678aa8 228 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
49ba9447 229\r
230 //\r
cb678aa8 231 // address purpose size\r
232 // ------------ -------- -------------------------\r
67fe5bed 233 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
234 // 0xFC000000 gap 44 MB\r
cb678aa8 235 // 0xFEC00000 IO-APIC 4 KB\r
236 // 0xFEC01000 gap 1020 KB\r
237 // 0xFED00000 HPET 1 KB\r
238 // 0xFED00400 gap 1023 KB\r
239 // 0xFEE00000 LAPIC 1 MB\r
49ba9447 240 //\r
67fe5bed 241 AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);\r
cb678aa8 242 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
243 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
244 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
49ba9447 245}\r
246\r
247\r
248VOID\r
249MiscInitialization (\r
0e20a186 250 VOID\r
49ba9447 251 )\r
252{\r
253 //\r
254 // Disable A20 Mask\r
255 //\r
55cdb67a 256 IoOr8 (0x92, BIT1);\r
49ba9447 257\r
258 //\r
259 // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
260 //\r
261 BuildCpuHob (36, 16);\r
c756b2ab 262\r
0e20a186 263 //\r
264 // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r
265 // example by Xen) and skip the setup here. This matches the logic in\r
266 // AcpiTimerLibConstructor ().\r
267 //\r
268 if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {\r
eec7d420 269 //\r
931a0c74 270 // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r
271 // 1. set PMBA\r
eec7d420 272 //\r
931a0c74 273 PciAndThenOr32 (\r
274 PCI_LIB_ADDRESS (0, 1, 3, 0x40),\r
275 (UINT32) ~0xFFC0,\r
276 PcdGet16 (PcdAcpiPmBaseAddress)\r
277 );\r
278\r
279 //\r
280 // 2. set PCICMD/IOSE\r
281 //\r
282 PciOr8 (\r
283 PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),\r
284 EFI_PCI_COMMAND_IO_SPACE\r
285 );\r
286\r
287 //\r
288 // 3. set PMREGMISC/PMIOSE\r
289 //\r
290 PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);\r
eec7d420 291 }\r
49ba9447 292}\r
293\r
294\r
9ed65b10 295VOID\r
296BootModeInitialization (\r
297 )\r
298{\r
667bf1e4 299 EFI_STATUS Status;\r
300\r
301 Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
302 ASSERT_EFI_ERROR (Status);\r
303\r
304 Status = PeiServicesInstallPpi (mPpiBootMode);\r
305 ASSERT_EFI_ERROR (Status);\r
9ed65b10 306}\r
307\r
308\r
77ba993c 309VOID\r
310ReserveEmuVariableNvStore (\r
311 )\r
312{\r
313 EFI_PHYSICAL_ADDRESS VariableStore;\r
314\r
315 //\r
316 // Allocate storage for NV variables early on so it will be\r
317 // at a consistent address. Since VM memory is preserved\r
318 // across reboots, this allows the NV variable storage to survive\r
319 // a VM reboot.\r
320 //\r
321 VariableStore =\r
322 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
9edb2933 323 AllocateAlignedRuntimePages (\r
cce992ac
WL		 324 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
325 PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1 326 );\r
77ba993c 327 DEBUG ((EFI_D_INFO,\r
328 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
329 VariableStore,\r
29a3f139 330 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c 331 ));\r
332 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
333}\r
334\r
335\r
3ca15914 336VOID\r
337DebugDumpCmos (\r
338 VOID\r
339 )\r
340{\r
341 UINTN Loop;\r
342\r
343 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
344\r
345 for (Loop = 0; Loop < 0x80; Loop++) {\r
346 if ((Loop % 0x10) == 0) {\r
347 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
348 }\r
349 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
350 if ((Loop % 0x10) == 0xf) {\r
351 DEBUG ((EFI_D_INFO, "\n"));\r
352 }\r
353 }\r
354}\r
355\r
356\r
49ba9447 357/**\r
358 Perform Platform PEI initialization.\r
359\r
360 @param FileHandle Handle of the file being invoked.\r
361 @param PeiServices Describes the list of possible PEI Services.\r
362\r
363 @return EFI_SUCCESS The PEIM initialized successfully.\r
364\r
365**/\r
366EFI_STATUS\r
367EFIAPI\r
368InitializePlatform (\r
369 IN EFI_PEI_FILE_HANDLE FileHandle,\r
370 IN CONST EFI_PEI_SERVICES **PeiServices\r
371 )\r
372{\r
55cdb67a 373 EFI_PHYSICAL_ADDRESS TopOfMemory;\r
374\r
447d2641
WL		 375 TopOfMemory = 0;\r
376\r
49ba9447 377 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
378\r
3ca15914 379 DebugDumpCmos ();\r
380\r
b98b4941 381 XenDetect ();\r
c7ea55b9 382\r
869b17cc
JJ		 383 BootModeInitialization ();\r
384\r
f76e9eba
JJ		 385 PublishPeiMemory ();\r
386\r
c191a58f 387 if (!mXen) {\r
447d2641
WL		 388 TopOfMemory = MemDetect ();\r
389 }\r
49ba9447 390\r
b621bb0a 391 if (mXen) {\r
c7ea55b9 392 DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
b98b4941 393 InitializeXen ();\r
c7ea55b9 394 }\r
eec7d420 395\r
77ba993c 396 ReserveEmuVariableNvStore ();\r
397\r
49ba9447 398 PeiFvInitialization ();\r
399\r
b621bb0a 400 if (mXen) {\r
447d2641
WL		 401 XenMemMapInitialization ();\r
402 } else {\r
403 MemMapInitialization (TopOfMemory);\r
404 }\r
49ba9447 405\r
0e20a186 406 MiscInitialization ();\r
49ba9447 407\r
408 return EFI_SUCCESS;\r
409}\r
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