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OvmfPkg: factor the IO aperture shared by all PCI root bridges into PCDs
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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49ba9447 1/**@file\r
2 Platform PEI driver\r
3\r
869b17cc 4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
eec7d420 5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
56d7640a 7 This program and the accompanying materials\r
49ba9447 8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
5133d1f1 25#include <Library/BaseLib.h>\r
49ba9447 26#include <Library/DebugLib.h>\r
27#include <Library/HobLib.h>\r
28#include <Library/IoLib.h>\r
77ba993c 29#include <Library/MemoryAllocationLib.h>\r
30#include <Library/PcdLib.h>\r
49ba9447 31#include <Library/PciLib.h>\r
32#include <Library/PeimEntryPoint.h>\r
9ed65b10 33#include <Library/PeiServicesLib.h>\r
7cdba634 34#include <Library/QemuFwCfgLib.h>\r
49ba9447 35#include <Library/ResourcePublicationLib.h>\r
36#include <Guid/MemoryTypeInformation.h>\r
9ed65b10 37#include <Ppi/MasterBootMode.h>\r
931a0c74 38#include <IndustryStandard/Pci22.h>\r
97380beb 39#include <OvmfPlatforms.h>\r
49ba9447 40\r
41#include "Platform.h"\r
3ca15914 42#include "Cmos.h"\r
49ba9447 43\r
44EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
45 { EfiACPIMemoryNVS, 0x004 },\r
991d9563 46 { EfiACPIReclaimMemory, 0x008 },\r
55cdb67a 47 { EfiReservedMemoryType, 0x004 },\r
991d9563 48 { EfiRuntimeServicesData, 0x024 },\r
49 { EfiRuntimeServicesCode, 0x030 },\r
50 { EfiBootServicesCode, 0x180 },\r
51 { EfiBootServicesData, 0xF00 },\r
49ba9447 52 { EfiMaxMemoryType, 0x000 }\r
53};\r
54\r
55\r
9ed65b10 56EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
57 {\r
58 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
59 &gEfiPeiMasterBootModePpiGuid,\r
60 NULL\r
61 }\r
62};\r
63\r
64\r
589756c7
PA		 65UINT16 mHostBridgeDevId;\r
66\r
979420df
JJ		 67EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
68\r
7cdba634
JJ		 69BOOLEAN mS3Supported = FALSE;\r
70\r
979420df 71\r
49ba9447 72VOID\r
73AddIoMemoryBaseSizeHob (\r
74 EFI_PHYSICAL_ADDRESS MemoryBase,\r
75 UINT64 MemorySize\r
76 )\r
77{\r
991d9563 78 BuildResourceDescriptorHob (\r
79 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447 80 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
81 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
82 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
991d9563 83 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 84 MemoryBase,\r
85 MemorySize\r
86 );\r
87}\r
88\r
eec7d420 89VOID\r
90AddReservedMemoryBaseSizeHob (\r
91 EFI_PHYSICAL_ADDRESS MemoryBase,\r
cdef34ec
LE		 92 UINT64 MemorySize,\r
93 BOOLEAN Cacheable\r
eec7d420 94 )\r
95{\r
96 BuildResourceDescriptorHob (\r
97 EFI_RESOURCE_MEMORY_RESERVED,\r
98 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
99 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
100 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
cdef34ec
LE		 101 (Cacheable ?\r
102 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
103 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
104 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
105 0\r
106 ) |\r
eec7d420 107 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
108 MemoryBase,\r
109 MemorySize\r
110 );\r
111}\r
49ba9447 112\r
113VOID\r
114AddIoMemoryRangeHob (\r
115 EFI_PHYSICAL_ADDRESS MemoryBase,\r
116 EFI_PHYSICAL_ADDRESS MemoryLimit\r
117 )\r
118{\r
119 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
120}\r
121\r
122\r
123VOID\r
124AddMemoryBaseSizeHob (\r
125 EFI_PHYSICAL_ADDRESS MemoryBase,\r
126 UINT64 MemorySize\r
127 )\r
128{\r
991d9563 129 BuildResourceDescriptorHob (\r
130 EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447 131 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
132 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
133 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
134 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
135 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
136 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
991d9563 137 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 138 MemoryBase,\r
139 MemorySize\r
140 );\r
141}\r
142\r
143\r
144VOID\r
145AddMemoryRangeHob (\r
146 EFI_PHYSICAL_ADDRESS MemoryBase,\r
147 EFI_PHYSICAL_ADDRESS MemoryLimit\r
148 )\r
149{\r
150 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
151}\r
152\r
c0e10976 153\r
154VOID\r
155AddUntestedMemoryBaseSizeHob (\r
156 EFI_PHYSICAL_ADDRESS MemoryBase,\r
157 UINT64 MemorySize\r
158 )\r
159{\r
160 BuildResourceDescriptorHob (\r
161 EFI_RESOURCE_SYSTEM_MEMORY,\r
162 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
163 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
164 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
165 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
166 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
167 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
168 MemoryBase,\r
169 MemorySize\r
170 );\r
171}\r
172\r
173\r
174VOID\r
175AddUntestedMemoryRangeHob (\r
176 EFI_PHYSICAL_ADDRESS MemoryBase,\r
177 EFI_PHYSICAL_ADDRESS MemoryLimit\r
178 )\r
179{\r
180 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
181}\r
182\r
bb6a9a93 183VOID\r
4b455f7b 184MemMapInitialization (\r
bb6a9a93
WL		 185 VOID\r
186 )\r
187{\r
bb6a9a93
WL		 188 //\r
189 // Create Memory Type Information HOB\r
190 //\r
191 BuildGuidDataHob (\r
192 &gEfiMemoryTypeInformationGuid,\r
193 mDefaultMemoryTypeInformation,\r
194 sizeof(mDefaultMemoryTypeInformation)\r
195 );\r
196\r
197 //\r
198 // Add PCI IO Port space available for PCI resource allocations.\r
199 //\r
200 BuildResourceDescriptorHob (\r
201 EFI_RESOURCE_IO,\r
202 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
203 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
e705f899
LE		 204 PcdGet64 (PcdPciIoBase),\r
205 PcdGet64 (PcdPciIoSize)\r
bb6a9a93
WL		 206 );\r
207\r
208 //\r
209 // Video memory + Legacy BIOS region\r
210 //\r
211 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
212\r
4b455f7b
JJ		 213 if (!mXen) {\r
214 UINT32 TopOfLowRam;\r
c68d3a69
LE		 215 UINT32 PciBase;\r
216\r
4b455f7b 217 TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
c68d3a69
LE		 218 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
219 //\r
220 // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
221 // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
222 // the RAM below 4 GB exceed it.\r
223 //\r
224 PciBase = BASE_2GB + BASE_1GB;\r
225 ASSERT (TopOfLowRam <= PciBase);\r
226 } else {\r
227 PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
228 }\r
49ba9447 229\r
4b455f7b
JJ		 230 //\r
231 // address purpose size\r
232 // ------------ -------- -------------------------\r
233 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
234 // 0xFC000000 gap 44 MB\r
235 // 0xFEC00000 IO-APIC 4 KB\r
236 // 0xFEC01000 gap 1020 KB\r
237 // 0xFED00000 HPET 1 KB\r
90721ba5
PA		 238 // 0xFED00400 gap 111 KB\r
239 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
240 // 0xFED20000 gap 896 KB\r
4b455f7b
JJ		 241 // 0xFEE00000 LAPIC 1 MB\r
242 //\r
c68d3a69 243 AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
4b455f7b
JJ		 244 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
245 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
90721ba5
PA		 246 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
247 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
248 }\r
4b455f7b 249 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
4b455f7b 250 }\r
49ba9447 251}\r
252\r
ab081a50
LE		 253EFI_STATUS\r
254GetNamedFwCfgBoolean (\r
255 IN CHAR8 *FwCfgFileName,\r
256 OUT BOOLEAN *Setting\r
257 )\r
258{\r
259 EFI_STATUS Status;\r
260 FIRMWARE_CONFIG_ITEM FwCfgItem;\r
261 UINTN FwCfgSize;\r
262 UINT8 Value[3];\r
263\r
264 Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
265 if (EFI_ERROR (Status)) {\r
266 return Status;\r
267 }\r
268 if (FwCfgSize > sizeof Value) {\r
269 return EFI_BAD_BUFFER_SIZE;\r
270 }\r
271 QemuFwCfgSelectItem (FwCfgItem);\r
272 QemuFwCfgReadBytes (FwCfgSize, Value);\r
273\r
274 if ((FwCfgSize == 1) ||\r
275 (FwCfgSize == 2 && Value[1] == '\n') ||\r
276 (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
277 switch (Value[0]) {\r
278 case '0':\r
279 case 'n':\r
280 case 'N':\r
281 *Setting = FALSE;\r
282 return EFI_SUCCESS;\r
283\r
284 case '1':\r
285 case 'y':\r
286 case 'Y':\r
287 *Setting = TRUE;\r
288 return EFI_SUCCESS;\r
289\r
290 default:\r
291 break;\r
292 }\r
293 }\r
294 return EFI_PROTOCOL_ERROR;\r
295}\r
296\r
297#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
298 do { \\r
299 BOOLEAN Setting; \\r
300 \\r
301 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
302 "opt/ovmf/" #TokenName, &Setting))) { \\r
303 PcdSetBool (TokenName, Setting); \\r
304 } \\r
305 } while (0)\r
306\r
307VOID\r
308NoexecDxeInitialization (\r
309 VOID\r
310 )\r
311{\r
312 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
313 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
314}\r
49ba9447 315\r
316VOID\r
317MiscInitialization (\r
0e20a186 318 VOID\r
49ba9447 319 )\r
320{\r
97380beb
GS		 321 UINTN PmCmd;\r
322 UINTN Pmba;\r
e2ab3f81
GS		 323 UINTN AcpiCtlReg;\r
324 UINT8 AcpiEnBit;\r
97380beb 325\r
49ba9447 326 //\r
327 // Disable A20 Mask\r
328 //\r
55cdb67a 329 IoOr8 (0x92, BIT1);\r
49ba9447 330\r
331 //\r
86a14b0a
LE		 332 // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
333 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
334 // S3 resume as well, so we build it unconditionally.)\r
49ba9447 335 //\r
86a14b0a 336 BuildCpuHob (mPhysMemAddressWidth, 16);\r
c756b2ab 337\r
97380beb 338 //\r
589756c7 339 // Determine platform type and save Host Bridge DID to PCD\r
97380beb 340 //\r
589756c7 341 switch (mHostBridgeDevId) {\r
97380beb 342 case INTEL_82441_DEVICE_ID:\r
e2ab3f81 343 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
da372167
LE		 344 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
345 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
346 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
97380beb
GS		 347 break;\r
348 case INTEL_Q35_MCH_DEVICE_ID:\r
e2ab3f81 349 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
bc9d05d6
LE		 350 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
351 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
352 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
97380beb
GS		 353 break;\r
354 default:\r
355 DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
589756c7 356 __FUNCTION__, mHostBridgeDevId));\r
97380beb
GS		 357 ASSERT (FALSE);\r
358 return;\r
359 }\r
589756c7 360 PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
97380beb 361\r
0e20a186 362 //\r
e2ab3f81
GS		 363 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
364 // has been configured (e.g., by Xen) and skip the setup here.\r
365 // This matches the logic in AcpiTimerLibConstructor ().\r
0e20a186 366 //\r
e2ab3f81 367 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
eec7d420 368 //\r
e2ab3f81 369 // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
931a0c74 370 // 1. set PMBA\r
eec7d420 371 //\r
97380beb 372 PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
931a0c74 373\r
374 //\r
375 // 2. set PCICMD/IOSE\r
376 //\r
97380beb 377 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
931a0c74 378\r
379 //\r
e2ab3f81 380 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
931a0c74 381 //\r
e2ab3f81 382 PciOr8 (AcpiCtlReg, AcpiEnBit);\r
eec7d420 383 }\r
90721ba5
PA		 384\r
385 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
386 //\r
387 // Set Root Complex Register Block BAR\r
388 //\r
389 PciWrite32 (\r
390 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
391 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
392 );\r
393 }\r
49ba9447 394}\r
395\r
396\r
9ed65b10 397VOID\r
398BootModeInitialization (\r
8f5ca05b 399 VOID\r
9ed65b10 400 )\r
401{\r
8f5ca05b
LE		 402 EFI_STATUS Status;\r
403\r
404 if (CmosRead8 (0xF) == 0xFE) {\r
979420df 405 mBootMode = BOOT_ON_S3_RESUME;\r
8f5ca05b 406 }\r
9be75189 407 CmosWrite8 (0xF, 0x00);\r
667bf1e4 408\r
979420df 409 Status = PeiServicesSetBootMode (mBootMode);\r
667bf1e4 410 ASSERT_EFI_ERROR (Status);\r
411\r
412 Status = PeiServicesInstallPpi (mPpiBootMode);\r
413 ASSERT_EFI_ERROR (Status);\r
9ed65b10 414}\r
415\r
416\r
77ba993c 417VOID\r
418ReserveEmuVariableNvStore (\r
419 )\r
420{\r
421 EFI_PHYSICAL_ADDRESS VariableStore;\r
422\r
423 //\r
424 // Allocate storage for NV variables early on so it will be\r
425 // at a consistent address. Since VM memory is preserved\r
426 // across reboots, this allows the NV variable storage to survive\r
427 // a VM reboot.\r
428 //\r
429 VariableStore =\r
430 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
9edb2933 431 AllocateAlignedRuntimePages (\r
cce992ac
WL		 432 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
433 PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1 434 );\r
77ba993c 435 DEBUG ((EFI_D_INFO,\r
436 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
437 VariableStore,\r
29a3f139 438 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c 439 ));\r
440 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
441}\r
442\r
443\r
3ca15914 444VOID\r
445DebugDumpCmos (\r
446 VOID\r
447 )\r
448{\r
6394c35a 449 UINT32 Loop;\r
3ca15914 450\r
451 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
452\r
453 for (Loop = 0; Loop < 0x80; Loop++) {\r
454 if ((Loop % 0x10) == 0) {\r
455 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
456 }\r
457 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
458 if ((Loop % 0x10) == 0xf) {\r
459 DEBUG ((EFI_D_INFO, "\n"));\r
460 }\r
461 }\r
462}\r
463\r
464\r
5133d1f1
LE		 465VOID\r
466S3Verification (\r
467 VOID\r
468 )\r
469{\r
470#if defined (MDE_CPU_X64)\r
471 if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
472 DEBUG ((EFI_D_ERROR,\r
473 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
474 DEBUG ((EFI_D_ERROR,\r
475 "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
476 __FUNCTION__));\r
477 DEBUG ((EFI_D_ERROR,\r
478 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
479 ASSERT (FALSE);\r
480 CpuDeadLoop ();\r
481 }\r
482#endif\r
483}\r
484\r
485\r
49ba9447 486/**\r
487 Perform Platform PEI initialization.\r
488\r
489 @param FileHandle Handle of the file being invoked.\r
490 @param PeiServices Describes the list of possible PEI Services.\r
491\r
492 @return EFI_SUCCESS The PEIM initialized successfully.\r
493\r
494**/\r
495EFI_STATUS\r
496EFIAPI\r
497InitializePlatform (\r
498 IN EFI_PEI_FILE_HANDLE FileHandle,\r
499 IN CONST EFI_PEI_SERVICES **PeiServices\r
500 )\r
501{\r
502 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
503\r
3ca15914 504 DebugDumpCmos ();\r
505\r
b98b4941 506 XenDetect ();\r
c7ea55b9 507\r
7cdba634
JJ		 508 if (QemuFwCfgS3Enabled ()) {\r
509 DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
510 mS3Supported = TRUE;\r
511 }\r
512\r
5133d1f1 513 S3Verification ();\r
869b17cc 514 BootModeInitialization ();\r
bc89fe48 515 AddressWidthInitialization ();\r
869b17cc 516\r
f76e9eba
JJ		 517 PublishPeiMemory ();\r
518\r
2818c158 519 InitializeRamRegions ();\r
49ba9447 520\r
b621bb0a 521 if (mXen) {\r
c7ea55b9 522 DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
b98b4941 523 InitializeXen ();\r
c7ea55b9 524 }\r
eec7d420 525\r
589756c7
PA		 526 //\r
527 // Query Host Bridge DID\r
528 //\r
529 mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
530\r
bd386eaf
JJ		 531 if (mBootMode != BOOT_ON_S3_RESUME) {\r
532 ReserveEmuVariableNvStore ();\r
bd386eaf 533 PeiFvInitialization ();\r
bd386eaf 534 MemMapInitialization ();\r
ab081a50 535 NoexecDxeInitialization ();\r
bd386eaf 536 }\r
49ba9447 537\r
0e20a186 538 MiscInitialization ();\r
49ba9447 539\r
540 return EFI_SUCCESS;\r
541}\r
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