[mirror_edk2.git] / PcAtChipsetPkg / Include / Register / Hpet.h

/** @file\r
  HPET register definitions from the IA-PC HPET (High Precision Event Timers)\r
  Specification, Revision 1.0a, October 2004.\r
\r
  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __HPET_REGISTER_H__\r
#define __HPET_REGISTER_H__\r
\r
///\r
/// HPET General Register Offsets\r
///\r
#define HPET_GENERAL_CAPABILITIES_ID_OFFSET   0x000\r
#define HPET_GENERAL_CONFIGURATION_OFFSET     0x010\r
#define HPET_GENERAL_INTERRUPT_STATUS_OFFSET  0x020\r
\r
///\r
/// HPET Timer Register Offsets\r
///\r
#define HPET_MAIN_COUNTER_OFFSET         0x0F0\r
#define HPET_TIMER_CONFIGURATION_OFFSET  0x100\r
#define HPET_TIMER_COMPARATOR_OFFSET     0x108\r
#define HPET_TIMER_MSI_ROUTE_OFFSET      0x110\r
\r
///\r
/// Stride between sets of HPET Timer Registers\r
///\r
#define HPET_TIMER_STRIDE  0x20\r
\r
#pragma pack(1)\r
\r
///\r
/// HPET General Capabilities and ID Register\r
///\r
typedef union {\r
  struct {\r
    UINT32    Revision           : 8;\r
    UINT32    NumberOfTimers     : 5;\r
    UINT32    CounterSize        : 1;\r
    UINT32    Reserved0          : 1;\r
    UINT32    LegacyRoute        : 1;\r
    UINT32    VendorId           : 16;\r
    UINT32    CounterClockPeriod : 32;\r
  } Bits;\r
  UINT64    Uint64;\r
} HPET_GENERAL_CAPABILITIES_ID_REGISTER;\r
\r
///\r
/// HPET General Configuration Register\r
///\r
typedef union {\r
  struct {\r
    UINT32    MainCounterEnable : 1;\r
    UINT32    LegacyRouteEnable : 1;\r
    UINT32    Reserved0         : 30;\r
    UINT32    Reserved1         : 32;\r
  } Bits;\r
  UINT64    Uint64;\r
} HPET_GENERAL_CONFIGURATION_REGISTER;\r
\r
///\r
/// HPET Timer Configuration Register\r
///\r
typedef union {\r
  struct {\r
    UINT32    Reserved0                   : 1;\r
    UINT32    LevelTriggeredInterrupt     : 1;\r
    UINT32    InterruptEnable             : 1;\r
    UINT32    PeriodicInterruptEnable     : 1;\r
    UINT32    PeriodicInterruptCapability : 1;\r
    UINT32    CounterSizeCapability       : 1;\r
    UINT32    ValueSetEnable              : 1;\r
    UINT32    Reserved1                   : 1;\r
    UINT32    CounterSizeEnable           : 1;\r
    UINT32    InterruptRoute              : 5;\r
    UINT32    MsiInterruptEnable          : 1;\r
    UINT32    MsiInterruptCapability      : 1;\r
    UINT32    Reserved2                   : 16;\r
    UINT32    InterruptRouteCapability;\r
  } Bits;\r
  UINT64    Uint64;\r
} HPET_TIMER_CONFIGURATION_REGISTER;\r
\r
///\r
/// HPET Timer MSI Route Register\r
///\r
typedef union {\r
  struct {\r
    UINT32    Value   : 32;\r
    UINT32    Address : 32;\r
  } Bits;\r
  UINT64    Uint64;\r
} HPET_TIMER_MSI_ROUTE_REGISTER;\r
\r
#pragma pack()\r
\r
#endif\r
Commit	Line	Data
986d1dfb	1	/** @file\r
5a702acd	2	HPET register definitions from the IA-PC HPET (High Precision Event Timers)\r
986d1dfb	3	Specification, Revision 1.0a, October 2004.\r
986d1dfb	4	\r
5a702acd	5	Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
e1d302e5	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
986d1dfb	7	\r
	8	**/\r
	9	\r
	10	#ifndef __HPET_REGISTER_H__\r
	11	#define __HPET_REGISTER_H__\r
	12	\r
	13	///\r
	14	/// HPET General Register Offsets\r
	15	///\r
	16	#define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000\r
	17	#define HPET_GENERAL_CONFIGURATION_OFFSET 0x010\r
	18	#define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020\r
	19	\r
	20	///\r
	21	/// HPET Timer Register Offsets\r
	22	///\r
5220bd21 MK	23	#define HPET_MAIN_COUNTER_OFFSET 0x0F0\r
	24	#define HPET_TIMER_CONFIGURATION_OFFSET 0x100\r
	25	#define HPET_TIMER_COMPARATOR_OFFSET 0x108\r
	26	#define HPET_TIMER_MSI_ROUTE_OFFSET 0x110\r
986d1dfb	27	\r
	28	///\r
	29	/// Stride between sets of HPET Timer Registers\r
	30	///\r
5220bd21	31	#define HPET_TIMER_STRIDE 0x20\r
986d1dfb	32	\r
	33	#pragma pack(1)\r
	34	\r
	35	///\r
	36	/// HPET General Capabilities and ID Register\r
	37	///\r
	38	typedef union {\r
	39	struct {\r
5220bd21 MK	40	UINT32 Revision : 8;\r
	41	UINT32 NumberOfTimers : 5;\r
	42	UINT32 CounterSize : 1;\r
	43	UINT32 Reserved0 : 1;\r
	44	UINT32 LegacyRoute : 1;\r
	45	UINT32 VendorId : 16;\r
	46	UINT32 CounterClockPeriod : 32;\r
986d1dfb	47	} Bits;\r
5220bd21	48	UINT64 Uint64;\r
986d1dfb	49	} HPET_GENERAL_CAPABILITIES_ID_REGISTER;\r
	50	\r
	51	///\r
	52	/// HPET General Configuration Register\r
	53	///\r
	54	typedef union {\r
	55	struct {\r
5220bd21 MK	56	UINT32 MainCounterEnable : 1;\r
	57	UINT32 LegacyRouteEnable : 1;\r
	58	UINT32 Reserved0 : 30;\r
	59	UINT32 Reserved1 : 32;\r
986d1dfb	60	} Bits;\r
5220bd21	61	UINT64 Uint64;\r
986d1dfb	62	} HPET_GENERAL_CONFIGURATION_REGISTER;\r
	63	\r
	64	///\r
	65	/// HPET Timer Configuration Register\r
	66	///\r
	67	typedef union {\r
	68	struct {\r
5220bd21 MK	69	UINT32 Reserved0 : 1;\r
	70	UINT32 LevelTriggeredInterrupt : 1;\r
	71	UINT32 InterruptEnable : 1;\r
	72	UINT32 PeriodicInterruptEnable : 1;\r
	73	UINT32 PeriodicInterruptCapability : 1;\r
	74	UINT32 CounterSizeCapability : 1;\r
	75	UINT32 ValueSetEnable : 1;\r
	76	UINT32 Reserved1 : 1;\r
	77	UINT32 CounterSizeEnable : 1;\r
	78	UINT32 InterruptRoute : 5;\r
	79	UINT32 MsiInterruptEnable : 1;\r
	80	UINT32 MsiInterruptCapability : 1;\r
	81	UINT32 Reserved2 : 16;\r
	82	UINT32 InterruptRouteCapability;\r
986d1dfb	83	} Bits;\r
5220bd21	84	UINT64 Uint64;\r
986d1dfb	85	} HPET_TIMER_CONFIGURATION_REGISTER;\r
	86	\r
	87	///\r
	88	/// HPET Timer MSI Route Register\r
	89	///\r
	90	typedef union {\r
	91	struct {\r
5220bd21 MK	92	UINT32 Value : 32;\r
5220bd21 MK	93	UINT32 Address : 32;\r
986d1dfb	94	} Bits;\r
5220bd21	95	UINT64 Uint64;\r
986d1dfb	96	} HPET_TIMER_MSI_ROUTE_REGISTER;\r
	97	\r
	98	#pragma pack()\r
	99	\r
	100	#endif\r