projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 986d1dfb | 1 | /** @file\r |
| 5a702acd | 2 | I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt\r |
| 986d1dfb | 3 | Controller (IOAPIC), 1996.\r |
| 5a702acd LG |
4 | \r |
| 5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
| 986d1dfb | 6 | This program and the accompanying materials\r |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef __IO_APIC_H__\r | |
| 17 | #define __IO_APIC_H__\r | |
| 18 | \r | |
| 19 | ///\r | |
| 20 | /// I/O APIC Register Offsets\r | |
| 21 | ///\r | |
| 22 | #define IOAPIC_INDEX_OFFSET 0x00\r | |
| 23 | #define IOAPIC_DATA_OFFSET 0x10\r | |
| 24 | \r | |
| 25 | ///\r | |
| 26 | /// I/O APIC Indirect Register Indexes\r | |
| 27 | ///\r | |
| 28 | #define IO_APIC_IDENTIFICATION_REGISTER_INDEX 0x00\r | |
| 29 | #define IO_APIC_VERSION_REGISTER_INDEX 0x01\r | |
| 30 | #define IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX 0x10\r | |
| 31 | \r | |
| 32 | ///\r | |
| 33 | /// I/O APIC Interrupt Deliver Modes\r | |
| 34 | ///\r | |
| 35 | #define IO_APIC_DELIVERY_MODE_FIXED 0\r | |
| 36 | #define IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r | |
| 37 | #define IO_APIC_DELIVERY_MODE_SMI 2\r | |
| 38 | #define IO_APIC_DELIVERY_MODE_NMI 4\r | |
| 39 | #define IO_APIC_DELIVERY_MODE_INIT 5\r | |
| 40 | #define IO_APIC_DELIVERY_MODE_EXTINT 7\r | |
| 41 | \r | |
| 42 | #pragma pack(1)\r | |
| 43 | \r | |
| 44 | typedef union {\r | |
| 45 | struct {\r | |
| 46 | UINT32 Reserved0:24;\r | |
| 47 | UINT32 Identification:4;\r | |
| 48 | UINT32 Reserved1:4;\r | |
| 49 | } Bits;\r | |
| 50 | UINT32 Uint32;\r | |
| 51 | } IO_APIC_IDENTIFICATION_REGISTER;\r | |
| 52 | \r | |
| 53 | typedef union {\r | |
| 54 | struct {\r | |
| 55 | UINT32 Version:8;\r | |
| 56 | UINT32 Reserved0:8;\r | |
| 57 | UINT32 MaximumRedirectionEntry:8;\r | |
| 58 | UINT32 Reserved1:8;\r | |
| 59 | } Bits;\r | |
| 60 | UINT32 Uint32;\r | |
| 61 | } IO_APIC_VERSION_REGISTER;\r | |
| 62 | \r | |
| 63 | typedef union {\r | |
| 64 | struct {\r | |
| 65 | UINT32 Vector: 8;\r | |
| 66 | UINT32 DeliveryMode: 3;\r | |
| 67 | UINT32 DestinationMode: 1;\r | |
| 68 | UINT32 DeliveryStatus: 1;\r | |
| 69 | UINT32 Polarity: 1;\r | |
| 70 | UINT32 RemoteIRR: 1;\r | |
| 71 | UINT32 TriggerMode: 1;\r | |
| 72 | UINT32 Mask: 1;\r | |
| 73 | UINT32 Reserved0: 15;\r | |
| 74 | UINT32 Reserved1: 24;\r | |
| 75 | UINT32 DestinationID: 8;\r | |
| 76 | } Bits;\r | |
| 77 | struct {\r | |
| 78 | UINT32 Low;\r | |
| 79 | UINT32 High;\r | |
| 80 | } Uint32;\r | |
| 81 | UINT64 Uint64;\r | |
| 82 | } IO_APIC_REDIRECTION_TABLE_ENTRY;\r | |
| 83 | \r | |
| 84 | #pragma pack()\r | |
| 85 | \r | |
| 86 | #endif\r |