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Commit | Line | Data |
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83d1ffb9 LG |
1 | /** @file\r |
2 | ACPI Timer implements one instance of Timer Library.\r | |
3 | \r | |
fd501a79 | 4 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r |
e1d302e5 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
83d1ffb9 LG |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include <Base.h>\r | |
10 | #include <Library/TimerLib.h>\r | |
11 | #include <Library/BaseLib.h>\r | |
12 | #include <Library/PcdLib.h>\r | |
13 | #include <Library/PciLib.h>\r | |
14 | #include <Library/IoLib.h>\r | |
15 | #include <Library/DebugLib.h>\r | |
16 | #include <IndustryStandard/Acpi.h>\r | |
17 | \r | |
5220bd21 MK |
18 | GUID mFrequencyHobGuid = {\r |
19 | 0x3fca54f6, 0xe1a2, 0x4b20, { 0xbe, 0x76, 0x92, 0x6b, 0x4b, 0x48, 0xbf, 0xaa }\r | |
20 | };\r | |
fd501a79 | 21 | \r |
83d1ffb9 LG |
22 | /**\r |
23 | Internal function to retrieves the 64-bit frequency in Hz.\r | |
24 | \r | |
25 | Internal function to retrieves the 64-bit frequency in Hz.\r | |
26 | \r | |
27 | @return The frequency in Hz.\r | |
28 | \r | |
29 | **/\r | |
30 | UINT64\r | |
31 | InternalGetPerformanceCounterFrequency (\r | |
32 | VOID\r | |
33 | );\r | |
34 | \r | |
35 | /**\r | |
36 | The constructor function enables ACPI IO space.\r | |
37 | \r | |
38 | If ACPI I/O space not enabled, this function will enable it.\r | |
39 | It will always return RETURN_SUCCESS.\r | |
40 | \r | |
41 | @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.\r | |
42 | \r | |
43 | **/\r | |
44 | RETURN_STATUS\r | |
45 | EFIAPI\r | |
46 | AcpiTimerLibConstructor (\r | |
47 | VOID\r | |
48 | )\r | |
49 | {\r | |
5220bd21 MK |
50 | UINTN Bus;\r |
51 | UINTN Device;\r | |
52 | UINTN Function;\r | |
53 | UINTN EnableRegister;\r | |
54 | UINT8 EnableMask;\r | |
83d1ffb9 LG |
55 | \r |
56 | //\r | |
5a702acd | 57 | // ASSERT for the invalid PCD values. They must be configured to the real value.\r |
83d1ffb9 LG |
58 | //\r |
59 | ASSERT (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) != 0xFFFF);\r | |
60 | ASSERT (PcdGet16 (PcdAcpiIoPortBaseAddress) != 0xFFFF);\r | |
61 | \r | |
62 | //\r | |
5a702acd | 63 | // If the register offset to the BAR for the ACPI I/O Port Base Address is 0x0000, then\r |
aad15888 | 64 | // no PCI register programming is required to enable access to the ACPI registers\r |
83d1ffb9 LG |
65 | // specified by PcdAcpiIoPortBaseAddress\r |
66 | //\r | |
67 | if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) == 0x0000) {\r | |
68 | return RETURN_SUCCESS;\r | |
69 | }\r | |
70 | \r | |
71 | //\r | |
5a702acd | 72 | // ASSERT for the invalid PCD values. They must be configured to the real value.\r |
83d1ffb9 | 73 | //\r |
5220bd21 MK |
74 | ASSERT (PcdGet8 (PcdAcpiIoPciDeviceNumber) != 0xFF);\r |
75 | ASSERT (PcdGet8 (PcdAcpiIoPciFunctionNumber) != 0xFF);\r | |
83d1ffb9 LG |
76 | ASSERT (PcdGet16 (PcdAcpiIoPciEnableRegisterOffset) != 0xFFFF);\r |
77 | \r | |
78 | //\r | |
79 | // Retrieve the PCD values for the PCI configuration space required to program the ACPI I/O Port Base Address\r | |
80 | //\r | |
5220bd21 MK |
81 | Bus = PcdGet8 (PcdAcpiIoPciBusNumber);\r |
82 | Device = PcdGet8 (PcdAcpiIoPciDeviceNumber);\r | |
83 | Function = PcdGet8 (PcdAcpiIoPciFunctionNumber);\r | |
83d1ffb9 | 84 | EnableRegister = PcdGet16 (PcdAcpiIoPciEnableRegisterOffset);\r |
5220bd21 | 85 | EnableMask = PcdGet8 (PcdAcpiIoBarEnableMask);\r |
83d1ffb9 LG |
86 | \r |
87 | //\r | |
88 | // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.\r | |
89 | //\r | |
dde4aedc | 90 | if ((PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister)) & EnableMask) != EnableMask) {\r |
83d1ffb9 LG |
91 | PciWrite16 (\r |
92 | PCI_LIB_ADDRESS (Bus, Device, Function, PcdGet16 (PcdAcpiIoPciBarRegisterOffset)),\r | |
93 | PcdGet16 (PcdAcpiIoPortBaseAddress)\r | |
94 | );\r | |
95 | PciOr8 (\r | |
96 | PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister),\r | |
97 | EnableMask\r | |
98 | );\r | |
99 | }\r | |
5a702acd | 100 | \r |
83d1ffb9 LG |
101 | return RETURN_SUCCESS;\r |
102 | }\r | |
103 | \r | |
104 | /**\r | |
105 | Internal function to retrieve the ACPI I/O Port Base Address.\r | |
106 | \r | |
107 | Internal function to retrieve the ACPI I/O Port Base Address.\r | |
108 | \r | |
109 | @return The 16-bit ACPI I/O Port Base Address.\r | |
110 | \r | |
111 | **/\r | |
112 | UINT16\r | |
113 | InternalAcpiGetAcpiTimerIoPort (\r | |
114 | VOID\r | |
115 | )\r | |
116 | {\r | |
117 | UINT16 Port;\r | |
5a702acd | 118 | \r |
9ff926d6 | 119 | Port = PcdGet16 (PcdAcpiIoPortBaseAddress);\r |
5a702acd | 120 | \r |
83d1ffb9 | 121 | //\r |
5a702acd LG |
122 | // If the register offset to the BAR for the ACPI I/O Port Base Address is not 0x0000, then\r |
123 | // read the PCI register for the ACPI BAR value in case the BAR has been programmed to a\r | |
83d1ffb9 LG |
124 | // value other than PcdAcpiIoPortBaseAddress\r |
125 | //\r | |
126 | if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) != 0x0000) {\r | |
5220bd21 MK |
127 | Port = PciRead16 (\r |
128 | PCI_LIB_ADDRESS (\r | |
129 | PcdGet8 (PcdAcpiIoPciBusNumber),\r | |
130 | PcdGet8 (PcdAcpiIoPciDeviceNumber),\r | |
131 | PcdGet8 (PcdAcpiIoPciFunctionNumber),\r | |
132 | PcdGet16 (PcdAcpiIoPciBarRegisterOffset)\r | |
133 | )\r | |
134 | );\r | |
83d1ffb9 | 135 | }\r |
5a702acd | 136 | \r |
9ff926d6 | 137 | return (Port & PcdGet16 (PcdAcpiIoPortBaseAddressMask)) + PcdGet16 (PcdAcpiPm1TmrOffset);\r |
83d1ffb9 LG |
138 | }\r |
139 | \r | |
140 | /**\r | |
141 | Stalls the CPU for at least the given number of ticks.\r | |
142 | \r | |
143 | Stalls the CPU for at least the given number of ticks. It's invoked by\r | |
144 | MicroSecondDelay() and NanoSecondDelay().\r | |
145 | \r | |
146 | @param Delay A period of time to delay in ticks.\r | |
147 | \r | |
148 | **/\r | |
149 | VOID\r | |
150 | InternalAcpiDelay (\r | |
151 | IN UINT32 Delay\r | |
152 | )\r | |
153 | {\r | |
5220bd21 MK |
154 | UINT16 Port;\r |
155 | UINT32 Ticks;\r | |
156 | UINT32 Times;\r | |
83d1ffb9 LG |
157 | \r |
158 | Port = InternalAcpiGetAcpiTimerIoPort ();\r | |
159 | Times = Delay >> 22;\r | |
160 | Delay &= BIT22 - 1;\r | |
161 | do {\r | |
162 | //\r | |
163 | // The target timer count is calculated here\r | |
164 | //\r | |
b3b58d4d | 165 | Ticks = IoBitFieldRead32 (Port, 0, 23) + Delay;\r |
83d1ffb9 LG |
166 | Delay = BIT22;\r |
167 | //\r | |
168 | // Wait until time out\r | |
169 | // Delay >= 2^23 could not be handled by this function\r | |
170 | // Timer wrap-arounds are handled correctly by this function\r | |
171 | //\r | |
b3b58d4d | 172 | while (((Ticks - IoBitFieldRead32 (Port, 0, 23)) & BIT23) == 0) {\r |
83d1ffb9 LG |
173 | CpuPause ();\r |
174 | }\r | |
175 | } while (Times-- > 0);\r | |
176 | }\r | |
177 | \r | |
178 | /**\r | |
179 | Stalls the CPU for at least the given number of microseconds.\r | |
180 | \r | |
181 | Stalls the CPU for the number of microseconds specified by MicroSeconds.\r | |
182 | \r | |
183 | @param MicroSeconds The minimum number of microseconds to delay.\r | |
184 | \r | |
185 | @return MicroSeconds\r | |
186 | \r | |
187 | **/\r | |
188 | UINTN\r | |
189 | EFIAPI\r | |
190 | MicroSecondDelay (\r | |
191 | IN UINTN MicroSeconds\r | |
192 | )\r | |
193 | {\r | |
194 | InternalAcpiDelay (\r | |
195 | (UINT32)DivU64x32 (\r | |
196 | MultU64x32 (\r | |
197 | MicroSeconds,\r | |
198 | ACPI_TIMER_FREQUENCY\r | |
199 | ),\r | |
200 | 1000000u\r | |
201 | )\r | |
202 | );\r | |
203 | return MicroSeconds;\r | |
204 | }\r | |
205 | \r | |
206 | /**\r | |
207 | Stalls the CPU for at least the given number of nanoseconds.\r | |
208 | \r | |
209 | Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r | |
210 | \r | |
211 | @param NanoSeconds The minimum number of nanoseconds to delay.\r | |
212 | \r | |
213 | @return NanoSeconds\r | |
214 | \r | |
215 | **/\r | |
216 | UINTN\r | |
217 | EFIAPI\r | |
218 | NanoSecondDelay (\r | |
219 | IN UINTN NanoSeconds\r | |
220 | )\r | |
221 | {\r | |
222 | InternalAcpiDelay (\r | |
223 | (UINT32)DivU64x32 (\r | |
224 | MultU64x32 (\r | |
225 | NanoSeconds,\r | |
226 | ACPI_TIMER_FREQUENCY\r | |
227 | ),\r | |
228 | 1000000000u\r | |
229 | )\r | |
230 | );\r | |
231 | return NanoSeconds;\r | |
232 | }\r | |
233 | \r | |
234 | /**\r | |
235 | Retrieves the current value of a 64-bit free running performance counter.\r | |
236 | \r | |
237 | Retrieves the current value of a 64-bit free running performance counter. The\r | |
238 | counter can either count up by 1 or count down by 1. If the physical\r | |
239 | performance counter counts by a larger increment, then the counter values\r | |
240 | must be translated. The properties of the counter can be retrieved from\r | |
241 | GetPerformanceCounterProperties().\r | |
242 | \r | |
243 | @return The current value of the free running performance counter.\r | |
244 | \r | |
245 | **/\r | |
246 | UINT64\r | |
247 | EFIAPI\r | |
248 | GetPerformanceCounter (\r | |
249 | VOID\r | |
250 | )\r | |
251 | {\r | |
252 | return AsmReadTsc ();\r | |
253 | }\r | |
254 | \r | |
255 | /**\r | |
256 | Retrieves the 64-bit frequency in Hz and the range of performance counter\r | |
257 | values.\r | |
258 | \r | |
259 | If StartValue is not NULL, then the value that the performance counter starts\r | |
260 | with immediately after is it rolls over is returned in StartValue. If\r | |
261 | EndValue is not NULL, then the value that the performance counter end with\r | |
262 | immediately before it rolls over is returned in EndValue. The 64-bit\r | |
263 | frequency of the performance counter in Hz is always returned. If StartValue\r | |
264 | is less than EndValue, then the performance counter counts up. If StartValue\r | |
265 | is greater than EndValue, then the performance counter counts down. For\r | |
266 | example, a 64-bit free running counter that counts up would have a StartValue\r | |
267 | of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r | |
268 | that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r | |
269 | \r | |
270 | @param StartValue The value the performance counter starts with when it\r | |
271 | rolls over.\r | |
272 | @param EndValue The value that the performance counter ends with before\r | |
273 | it rolls over.\r | |
274 | \r | |
275 | @return The frequency in Hz.\r | |
276 | \r | |
277 | **/\r | |
278 | UINT64\r | |
279 | EFIAPI\r | |
280 | GetPerformanceCounterProperties (\r | |
237295f4 | 281 | OUT UINT64 *StartValue OPTIONAL,\r |
83d1ffb9 LG |
282 | OUT UINT64 *EndValue OPTIONAL\r |
283 | )\r | |
284 | {\r | |
285 | if (StartValue != NULL) {\r | |
286 | *StartValue = 0;\r | |
287 | }\r | |
288 | \r | |
289 | if (EndValue != NULL) {\r | |
290 | *EndValue = 0xffffffffffffffffULL;\r | |
291 | }\r | |
5220bd21 | 292 | \r |
83d1ffb9 LG |
293 | return InternalGetPerformanceCounterFrequency ();\r |
294 | }\r | |
295 | \r | |
296 | /**\r | |
297 | Converts elapsed ticks of performance counter to time in nanoseconds.\r | |
298 | \r | |
299 | This function converts the elapsed ticks of running performance counter to\r | |
300 | time value in unit of nanoseconds.\r | |
301 | \r | |
302 | @param Ticks The number of elapsed ticks of running performance counter.\r | |
303 | \r | |
304 | @return The elapsed time in nanoseconds.\r | |
305 | \r | |
306 | **/\r | |
307 | UINT64\r | |
308 | EFIAPI\r | |
309 | GetTimeInNanoSecond (\r | |
310 | IN UINT64 Ticks\r | |
311 | )\r | |
312 | {\r | |
313 | UINT64 Frequency;\r | |
314 | UINT64 NanoSeconds;\r | |
315 | UINT64 Remainder;\r | |
316 | INTN Shift;\r | |
317 | \r | |
318 | Frequency = GetPerformanceCounterProperties (NULL, NULL);\r | |
319 | \r | |
320 | //\r | |
321 | // Ticks\r | |
322 | // Time = --------- x 1,000,000,000\r | |
323 | // Frequency\r | |
324 | //\r | |
325 | NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r | |
326 | \r | |
327 | //\r | |
328 | // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r | |
329 | // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r | |
330 | // i.e. highest bit set in Remainder should <= 33.\r | |
331 | //\r | |
5220bd21 MK |
332 | Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r |
333 | Remainder = RShiftU64 (Remainder, (UINTN)Shift);\r | |
334 | Frequency = RShiftU64 (Frequency, (UINTN)Shift);\r | |
83d1ffb9 LG |
335 | NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r |
336 | \r | |
337 | return NanoSeconds;\r | |
338 | }\r | |
62b8b5be SZ |
339 | \r |
340 | /**\r | |
341 | Calculate TSC frequency.\r | |
342 | \r | |
343 | The TSC counting frequency is determined by comparing how far it counts\r | |
a012df5e SZ |
344 | during a 101.4 us period as determined by the ACPI timer.\r |
345 | The ACPI timer is used because it counts at a known frequency.\r | |
346 | The TSC is sampled, followed by waiting 363 counts of the ACPI timer,\r | |
347 | or 101.4 us. The TSC is then sampled again. The difference multiplied by\r | |
348 | 9861 is the TSC frequency. There will be a small error because of the\r | |
349 | overhead of reading the ACPI timer. An attempt is made to determine and\r | |
350 | compensate for this error.\r | |
62b8b5be SZ |
351 | \r |
352 | @return The number of TSC counts per second.\r | |
353 | \r | |
354 | **/\r | |
355 | UINT64\r | |
356 | InternalCalculateTscFrequency (\r | |
357 | VOID\r | |
358 | )\r | |
359 | {\r | |
5220bd21 MK |
360 | UINT64 StartTSC;\r |
361 | UINT64 EndTSC;\r | |
362 | UINT16 TimerAddr;\r | |
363 | UINT32 Ticks;\r | |
364 | UINT64 TscFrequency;\r | |
365 | BOOLEAN InterruptState;\r | |
62b8b5be SZ |
366 | \r |
367 | InterruptState = SaveAndDisableInterrupts ();\r | |
368 | \r | |
369 | TimerAddr = InternalAcpiGetAcpiTimerIoPort ();\r | |
a012df5e SZ |
370 | //\r |
371 | // Compute the number of ticks to wait to measure TSC frequency.\r | |
372 | // Use 363 * 9861 = 3579543 Hz which is within 2 Hz of ACPI_TIMER_FREQUENCY.\r | |
373 | // 363 counts is a calibration time of 101.4 uS.\r | |
374 | //\r | |
b3b58d4d | 375 | Ticks = IoBitFieldRead32 (TimerAddr, 0, 23) + 363;\r |
62b8b5be SZ |
376 | \r |
377 | StartTSC = AsmReadTsc (); // Get base value for the TSC\r | |
378 | //\r | |
a012df5e | 379 | // Wait until the ACPI timer has counted 101.4 us.\r |
62b8b5be | 380 | // Timer wrap-arounds are handled correctly by this function.\r |
a012df5e SZ |
381 | // When the current ACPI timer value is greater than 'Ticks',\r |
382 | // the while loop will exit.\r | |
62b8b5be | 383 | //\r |
b3b58d4d | 384 | while (((Ticks - IoBitFieldRead32 (TimerAddr, 0, 23)) & BIT23) == 0) {\r |
5220bd21 | 385 | CpuPause ();\r |
62b8b5be | 386 | }\r |
5220bd21 | 387 | \r |
a012df5e | 388 | EndTSC = AsmReadTsc (); // TSC value 101.4 us later\r |
62b8b5be SZ |
389 | \r |
390 | TscFrequency = MultU64x32 (\r | |
a012df5e SZ |
391 | (EndTSC - StartTSC), // Number of TSC counts in 101.4 us\r |
392 | 9861 // Number of 101.4 us in a second\r | |
62b8b5be SZ |
393 | );\r |
394 | \r | |
395 | SetInterruptState (InterruptState);\r | |
396 | \r | |
397 | return TscFrequency;\r | |
398 | }\r |