ArmPkg: only attempt buildin MmCommunicationDxe for AArch64
[mirror_edk2.git] / PcAtChipsetPkg / PcAtChipsetPkg.dec
CommitLineData
7b202cb0 1## @file\r
31ed75a9 2# Public definitions for PcAtChipset package.\r
3#\r
4# This package is designed to public interfaces and implementation which follows\r
5# PcAt defacto standard.\r
6#\r
6b9dd13d 7# Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>\r
e78aab9d 8# Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
31ed75a9 9#\r
e1d302e5 10# SPDX-License-Identifier: BSD-2-Clause-Patent\r
31ed75a9 11#\r
7b202cb0 12##\r
31ed75a9 13\r
14[Defines]\r
15 DEC_SPECIFICATION = 0x00010005\r
16 PACKAGE_NAME = PcAtChipsetPkg\r
b414ac4d 17 PACKAGE_UNI_FILE = PcAtChipsetPkg.uni\r
31ed75a9 18 PACKAGE_GUID = B728689A-52D3-4b8c-AE89-2CE5514CC6DC\r
9325f684 19 PACKAGE_VERSION = 0.3\r
31ed75a9 20\r
986d1dfb 21[Includes]\r
22 Include\r
23\r
24[LibraryClasses]\r
25 ## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r
26 #\r
27 IoApicLib|Include/Library/IoApicLib.h\r
5a702acd 28\r
53705ed1 29[Guids]\r
30 gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r
31\r
f5f47471
RN
32#\r
33# [Error.gPcAtChipsetPkgTokenSpaceGuid]\r
34# 0x80000001 | Invalid value provided.\r
35#\r
36\r
986d1dfb 37[PcdsFeatureFlag]\r
b414ac4d
QS
38 ## Indicates the HPET Timer will be configured to use MSI interrupts if the HPET timer supports them, or use I/O APIC interrupts.<BR><BR>\r
39 # TRUE - Configures the HPET Timer to use MSI interrupts if the HPET Timer supports them.<BR>\r
40 # FALSE - Configures the HPET Timer to use I/O APIC interrupts.<BR>\r
41 # @Prompt Configure HPET to use MSI.\r
986d1dfb 42 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetMsiEnable|TRUE|BOOLEAN|0x00001000\r
b414ac4d 43\r
856f592c 44[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r
986d1dfb 45 ## This PCD specifies the base address of the HPET timer.\r
b414ac4d 46 # @Prompt HPET base address.\r
986d1dfb 47 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT32|0x00000009\r
48\r
49 ## This PCD specifies the Local APIC Interrupt Vector for the HPET Timer.\r
b414ac4d 50 # @Prompt HPET local APIC vector.\r
986d1dfb 51 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r
52\r
53b1dd10 53 ## This PCD specifies the default period of the HPET Timer in 100 ns units.\r
986d1dfb 54 # The default value of 100000 100 ns units is the same as 10 ms.\r
b414ac4d 55 # @Prompt Default period of HPET timer.\r
986d1dfb 56 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r
5a702acd 57\r
b414ac4d
QS
58 ## This PCD specifies the base address of the IO APIC.\r
59 # @Prompt IO APIC base address.\r
986d1dfb 60 gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r
1e5fff63
EL
61\r
62 ## This PCD specifies the minimal valid year in RTC.\r
63 # @Prompt Minimal valid year in RTC.\r
64 gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1998|UINT16|0x0000000D\r
65\r
66 ## This PCD specifies the maximal valid year in RTC.\r
67 # @Prompt Maximal valid year in RTC.\r
f5f47471 68 # @Expression 0x80000001 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear < gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear + 100\r
fe320967 69 gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2097|UINT16|0x0000000E\r
5a702acd 70\r
83d1ffb9
LG
71[PcdsFixedAtBuild, PcdsPatchableInModule]\r
72 ## Defines the ACPI register set base address.\r
5a702acd 73 # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
74 # @Prompt ACPI Timer IO Port Address\r
75 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r
76\r
77 ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
78 # @Prompt ACPI Hardware PCI Bus Number\r
79 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r
80\r
81 ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
5a702acd 82 # The invalid 0xFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
83 # @Prompt ACPI Hardware PCI Device Number\r
84 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r
85\r
86 ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
5a702acd 87 # The invalid 0xFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
88 # @Prompt ACPI Hardware PCI Function Number\r
89 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r
5a702acd 90\r
83d1ffb9 91 ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r
5a702acd 92 # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
93 # @Prompt ACPI Hardware PCI Register Offset\r
94 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r
5a702acd 95\r
83d1ffb9
LG
96 ## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r
97 # @Prompt ACPI Hardware PCI Bar Enable BitMask\r
98 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r
5a702acd 99\r
83d1ffb9 100 ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r
5a702acd 101 # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
102 # @Prompt ACPI Hardware PCI Bar Register Offset\r
103 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r
104\r
105 ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.\r
106 # @Prompt Offset to 32-bit Timer register in ACPI BAR\r
107 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008|UINT16|0x00000017\r
b414ac4d 108\r
9ff926d6
LG
109 ## Defines the bit mask to retrieve ACPI IO Port Base Address\r
110 # @Prompt ACPI IO Port Base Address Mask\r
111 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFE|UINT16|0x00000018\r
112\r
a38b89c7
LG
113 ## Reset Control Register address in I/O space.\r
114 # @Prompt Reset Control Register address\r
115 gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlRegister|0x64|UINT64|0x00000019\r
116\r
117 ## 8bit Reset Control Register value for cold reset.\r
118 # @Prompt Reset Control Register value for cold reset\r
119 gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlValueColdReset|0xFE|UINT8|0x0000001A\r
120\r
e78aab9d
LD
121 ## Specifies the initial value for Register_A in RTC.\r
122 # @Prompt Initial value for Register_A in RTC.\r
123 gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x0000001B\r
124\r
125 ## Specifies the initial value for Register_B in RTC.\r
126 # @Prompt Initial value for Register_B in RTC.\r
127 gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x0000001C\r
128\r
129 ## Specifies the initial value for Register_D in RTC.\r
130 # @Prompt Initial value for Register_D in RTC.\r
131 gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0000001D\r
132\r
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RN
133 ## Specifies RTC Index Register address in I/O space.\r
134 # @Prompt RTC Index Register address\r
135 gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E\r
136\r
137 ## Specifies RTC Target Register address in I/O space.\r
138 # @Prompt RTC Target Register address\r
139 gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F\r
140\r
6b9dd13d
RN
141 ## RTC Update Timeout Value(microsecond).\r
142 # @Prompt RTC Update Timeout Value.\r
143 gPcAtChipsetPkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|100000|UINT32|0x00000020\r
144\r
b414ac4d 145[UserExtensions.TianoCore."ExtraFiles"]\r
fe320967 146 PcAtChipsetPkgExtra.uni\r